EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector

Transcription

1 EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector Group Members Uttam Kumar Boda Rajesh Tenukuntla Mohammad M Iftakhar Srikanth Yanamanagandla 1

2 Table of contents 1. Introduction Block Diagram 3 2. Input Buffer Working Schematic Simulation Layout Simulation Analysis 6 3. Ring Oscillator Schematic Simulation Layout 9 4. Frequency Divider Circuit Working Schematic Layout Simulations Output Buffer Schematic Calculation Layout Simulation Multiplexers Schematic Layout Simulations Corners Conclusion References 2

3 1. Introduction The primary goal of our project is to design an e-test pad that works as a frequency selector. E-test pads are structures that are present in the scribe line of wafers. Frequency selection is achieved by using a ring oscillator with a fanout 1 that generates a frequency which is fed to a frequency divider circuit. This circuit is a series of D-Flipflops. The output from each flip flop is fed to a multiplexer. The output signal from the multiplexer is defined by the selection inputs and thus the whole circuit acts as a frequency selector. We carried out all the schematics, layouts and simulations in the Cadence Environment. Virtuoso tools like the schematic editor, layout editor, and symbol editor were used to draw schematics, layouts and symbol respectively. The spectre simulator was used to perform the various simulations shown in this document. DRC, CLDRC and LVS run were successfully made on all the layouts that reside in our project directory. 1.1 Block diagram 8:1 MUX Output Buffer Scope Input Buffer Enable Circuit Ring Oscillator Frequency Divider Frequency Divider Frequency Divider Output Buffer Output Buffer Scope Figure1: Block diagram of the e-test pad 2 Input Buffer An input buffer is used to make the input signal stable without any voltage imperfections 3

4 and also decrease the rise and fall times. This is due to the inverter action of transistors M1 and M2. The buffer used here is a tri-state buffer instead of a normal enable circuit because it was used to pass the signal to the output when enable is high and when the enable is low, the output will be in high impedance state. This is mainly used for data sharing on a single communication bus. 2.1 Working The working of the tri-state buffer is explained in the Table a. When the enable is high, the inputs to the nand and nor circuits get inverted and area given as inputs to transistors M1 and M2 which act as an inverter together. When the enable is low, the outputs of the nand and nor are high and low respectively. So the two transistors are off leaving the output in the high impedance state. The width of PMOS is taken twice that of the NMOS in order to stabilize the dynamic characteristics of the inverter and there by reducing the delay in the output. Figure2: A tri state buffer circuit Enable Data Nand o/p Nor o/p I5 I7 Out 0 X High Low Off Off High Z 1 0 High High Off On Gnd 1 1 Low Low On Off Vdd Table a 2.1 Schematic The schematic of the input buffer is shown in Figure 1. The width for PMOS was taken as 2.10 um and that for the NMOS was taken as 1.05 um. The length was taken as 0.5um 4

5 for both. Symbols were used for nand, nor and inverter as they are flexible to use any where in the entire circuit. Figure 3: schematic of the input buffer 2.2 Simulation The tri state input was given high at Enable in and the input signal was given as a DC. The rise and fall times were taken as 1 ns. The pulse width and period have been taken as 100 ns and 200 ns respectively. The simulation results are shown in figure 2.3 Layout 5

6 A ptran cell and ntran cells were instantiated and a minimal layout was achieved as shown Figure 4. The third inverter stage of the ratio buffer was drawn using folding concept. The ptran cell and ntran cell of the third stage inverter of the ratio buffer were instantiated with a width of 3.15 and m factor of 3 as in the schematic. The three Mosfets in the instantiated cells were connected parallel. The width and length of the layout were 12.9 μm and 27.1 μm respectively. All the n-wells were overlapped to reduce the layout size. Connections were made using li1 and metal1 drawing layers. Figure 4: Layout of the input buffer 2.4 Simulations As shown in the graph, when the enable is given as 1.8v the input pulse with width 25ns and rise time and fall time 3ns will be converted in to perfect periodic pulse train with spikes during the input transition from high to low or low to high. This is because of no load at the output. Also it was observed that when the input signal voltage is 1.6v, the output voltage level was 1.8v. 6

7 Figure 6: simulation analysis of input buffer 3. RING OSCILLATOR A ring oscillator is a device composed of odd number of inverter stages whose output oscillates between two voltage levels. The Inverters are attached in a chain and the output of the last stage is fed back to the first stage. Because a single inverter computes the logical NOT of its input, the last output of a chain of odd number of inverters is the logical NOT of first input. The feed back of this last output to the input causes oscillations. In a ring oscillator every inverter is associated with certain propagation delay. This is because of the delay associated with each gate of the MOSFET. Thus, the output of 7

8 every inverter of a ring oscillator changes a finite amount of time after the input has changed. Hence, adding more inverters to the chain increases the total gate delay, reducing the frequency of oscillation. 3.1 SCHEMATIC OF RING OSCILLATOR The schematic for the ring oscillator is as shown in Figure 7. The ring oscillator has 85 stages of series connected inverters. The output of last stage inverter is fed back to the first stage. A total delay of 22ns is achieved by using 85 stages. Figure 7: Layout of the Ring oscillator 3.2 SIMULATION OF RING OSCILLATOR The simulation graph of the ring oscillator output is as shown in the Figure 8. Delay is the time taken for the input to produce an output. The delay of the ring oscillator is found by measuring half the time period of the output signal. In the graph shown below the total time period of one oscillation is 44ns (approximately) and so the delay of ring oscillator is 22ns (approximately). 8

9 Figure 8: simulation response of the input buffer circuit 3.3 LAYOUT OF RING OSCILLATOR The Layout of 85 stage ring oscillator is as shown in Figure 9. Width of the PMOS is taken as 2.10um and width of NMOS is 1.05um. The layout is arranged in a serpentine manner to reduce the layout area. Figure 9 Layout of an 85 stage ring oscillator 9

10 4. Frequency Divider Circuit The Raw output of the ring oscillator is given to a series of frequency divide by 2 circuits. D-flipflops are used for this purpose. The D-flip flop acts as a transparent latch because it transfers the input to the output when the clock is high and when the clock is low, the previous state of the output is retained. For the signal frequency to be divided by 2 that is the output pulse period to be twice that of the input the output should change the state during the rising or falling edge of the clock. So an Edge triggered D-flip flop can be configured in order to divide the frequency. D-FF can be constru cted using different logic gate implementations but here transmission gates and inverters are used as it decreases the number of gates and also improves the noise margin of the total circuit. As shown in the above figure, 2 level sensitive latches are cascaded to form a positive edge triggered D-flip flop and the clock signals are given in such a way that only one stage is ON at a time. The first stage is called master and the second is called slave. 4.1 Working When the clock is low (T1 T4 on and T2 T3 off), master will sense the input that is the D-input is passed through it and the slave circuit holds the previous state of output. When the clock is high (T1 T4 off and T3 T2 on), the input D is held by the master and passed on to the output by the slave. It can be observed that the total time taken for the input pulse D to traverse to the output is equal to the clock period. The Qbar output is given back to the D-input and clock signal acts as the input. Qbar will always have the reverse state of Q, which is the previous state of D. The Q-output of first stage will be given to the clock input of the next stage as shown in the figure. Totally 10 stages are connected in order to divide the frequency by a factor of Schematic The schematic of a single stage frequency divider consists of 5 inverters and 4 transmission gates. The fifth inverter is used for generating complement of the clock signals. Here symbols are used to draw the schematic for the purpose of modularity. The 10

11 sizes of the transistors are taken as minimum and wire names are used for the similar signals instead of routing from a single pin. A symbol is created for this schematic and is used to connect all the 10 stages. The output signal of previous stage acts as a clock to the transmission gates of the next stage. 4.3 Layout Figure 10 The layout of the single D-flip flop is shown below in which transmission gate and inverter are merged in the master and slave parts of the circuit to minimize the area. 11

12 Metal 1 connections are used for VDD and Gnd connections, poly is used to connect all the gates of the transmission gates that is, for giving the clock signal connections. Licon is used for giving the interconnections in the circuit. The widths and spacing of all the layers are kept minimum. The layout of 10 stages of D-flip flop is done in an optimum area by rotating the stages as required in order to use the same ground rail for 4 stages as shown in the figure. 4.4 Simulations Figure 11 The simulations for 10 stage D flip flops takes long run times in order to see the Output effectively. So here simulations for 2 and 3 stages are shown that is the Frequency is divided by 4 and 8 respectively. Figure 12 12

13 Figure 13 5 Output Buffer Output buffer circuit is required for any output of the circuit that is to be connected to the E-test pad because for the signal to be viewed on an oscilloscope, the capacitance of the probe acts as load for the stage at which it was taken. Normally the standard capacitance of the probe is 10pf. So an output buffer which is capable of driving this capacitance must be designed. 5.1 Schematic 13

14 Figure 14 The schematic consists of chain of inverters with output of one stage given as input to next stage. Minimum ratio of widths was taken for the first stage. Drive means the current needed to change the voltage in given time. As the width of the inverter increases, current increases and so the required voltage is obtained in less time but the disadvantage of using large W/L is the input capacitance will be more which will load the previous stage. So the width of the inverters is increased gradually with the initial stage W/L kept minimum and the number of stages N and the multiplication factor A are chosen such that the delay is minimum. Folding is done for all the stages of the buffer in order to reduce the area. 5.2 Calculation of Cin for finding N A single stage inverter is connected to a load of 100pf load. The delay times Tphl and Tplh are calculated from the observed output as TPHL= 7.9 n TPLH= 4.11 n TPHL= 0.7*Rn*Cload so Rn=234K TPLH= 0.7*Rp*Cload so Rp=117K 14

15 Now the load is removed and the delay times are observed. Then the values of Rn and Rp found above are used for finding Cout. TPHL (without load) =420ps so using TPHL= 0.7*Rn*Cout Cout=2.07fF Cin = 3/2*Cout=3.11fF The number of stages N is N = ln (Cload/Cin) =8.07 Hence the buffer should contain 8 stages with A value equal to e ideally but the final stage size is very big which is unacceptable. So the N value is fixed as 6 and the value of A was calculated as 3.2 which is approximately 3. This output buffer was observed to drive the output as shown in the simulations below. 5.3 Layout The layout is drawn such that it occupies minimum area on the chip. Folding is done for all the stages with different M factors for each stage. The gates of all the parallel Mosfets are connected using poly and drains are connected using metal. The N-wells of each stage are joined in order to reduce the area. Last 2 stages are inverted in order to share the same power rail (gnd). The total layout area is 65um x 55um. 5.4 Simulations 15

16 Figure Multiplexer: 16

17 A multiplexer is a device that combines multiple inputs into an aggregate signal to be transported via a single transmission channel. 1 The input signal that is passed to output is defined by the selection inputs. In general the number of selection inputs for N inputs is defined by N=2 m where N is the number of inputs, m is the number of selection inputs 6.1 Schematic Figure 16 In our project we implement frequency selection using 8:1 multiplexer. The schematic is designed using minimum sized cells. The outputs of each D flip flop (freq divider circuit) is given as inputs A,B,C,D,E,F,G, and H respectively to the multiplexer. The selection inputs S0, S1, S2 are given to the gates of the transistors as shown in the figure. Multiplexer helps in reducing the number of o/p pins on the e-test pad. When the selection inputs are 000 then the output of the inverter in the first block is high making TG1, TG9, TG13 ON, as a result A is passed to the output. Similarly the rest of the inputs are passed to the output depending on the selection inputs. 17

18 6.2 Layout The layout has been drawn according to the schematic. The power connections are given using metal1 drawings and inputs using poly drawings. Licon was used for interconnection and metal 1 was used for routing. Tap contacts are used for substrate connections to Vdd and ground. The layout is as shown below 6.3 Simulations Figure 17 The transient response of the circuit is observed for various inputs. The input signals are pulses with a varied width and period (300nsec and 600nsec respectively in case of G input). The rise time and fall time for each input signal is 1nsec, 1nsec respectively. For 011 case, input G is passed on to the output, which is as shown. The circuit is observed to work successfully for various input signals. 18

19 Figure 18: Simulations of a Multiplexer 19

20 7. Corners The corner simulations are done to check if the circuit function as it is supposed to in all possible cases such as varying temperature and power supply. To check the working of the circuit under different operating conditions the voltage is varied from +10% to 10% of the actual value and the temperature is varied from -35 to 140C. The circuit is simulated for various combinations of these in the typical, fast and slow conditions. The following graphs show the delay for different power supply voltage and temperature. Figure 19. Delay at 140 C and 1.92V in the fast condition 20

21 Figure 20 Delay at -35 C and 1.68 V in the slow condition. At low temperatures, due to the less number of charge carriers the delay is high. As the temperature was increased from -35 to 140 the delay decreased. The following 3D plots show the variation in delay with change in temperature and Vdd. Slow condition delay(ns) temp(c) Vdd(V) Figure 21 21

22 Fast Condition delay(ns) temp(c) Vdd(V) Figure 22 Typical Condution delay(ns) temp(c) vdd(v) Figure 23 Thus the delay of the circuit varies with change in Vdd and the temperature as follows Delay decreases with increase in temperature. Delay decreases with increase in Power Supply Delay decreases as we change the design corners from the Slow to Fast. 22

23 8. Conclusion A ring oscillator is designed to produce a raw frequency of 25Mhz which can be viewed on an oscilloscope and also different frequencies are generated at each divider output which can be selected by using multiplexer. Simulations are performed for each block of the circuit and the performance of the total circuit was evaluated at all the corners by varying the temperature and vdd. The final divided frequency is around 100khz which can be used to drive very large loads as the time period of the signal is high. 9. References 1. CMOS circuit design, layout and simulation, 2 nd edition by R. Jacob baker