Design of an Integrated Image Sensor System

Transcription

1 Institute of Integrated Sensor Systems Dept. of Electrical Engineering and Information Technology Design of an Integrated Image Sensor System Kuan Shang Fall Semester, 2007 Prof. Dr.-Ing. Andreas König

2 Design Goals Individual Task: Row Address Design a APS row sensor with shutter arrangement Row Address Decoder Project1 Project2 Project3 Project4 Project5 Project6 Project7 Project8 Global Task: Reference Voltage Iss Iss Iss Iss Iss Iss Iss Iss Source Follower Load Design a biasing current supply circuit Column Address Row Address Decoder Analog Multiplexer Read Out Amplifier Buffer Amplifier ADC Digital Out Analog Out

3 Overview 1. APS Row Sensor Design 1.1 Characteristics of CMOS Image Sensor Design Configuration Responsibility Transfer Function Output Performance schematic design 1.2 Layout Drawing and simulation 1.3 Results 2. Biasing Current Circuit Design 2.1Application 2.2 Formulas 2.3 Design Parameters 2.4 raw schematic

4 1.1 Characteristics of APS Row Sensor Design Configuration Resolution: 0.35um-4-metal COMS Technology --Austria Microsystems Technology Photo Detector type : N-diffusion Photodiode Fill Factor : Photosensitive Area / Pixel Area Array Size : 4*16 pixels

5 1.1.2 Responsibility Quantum efficiency: measurement of the device s electrical sensitivity to light It depends on absorption and collection of charges For simulation we set Iphoton : 100pA~900pA Conversion Gain: transfer capability from the input electrons to the output voltage C.G= Vout/Number of Electrons = q/c(total) Light Source Q.E Electrons C.G Analog Voltage

6 1.1.3 Transfer Function Dynamic Range: it quantifies the sensor s ability to adequately image both high lights and dark shadow in scene. I max the largest non saturating photocurrent I min the smallest detectable photocurrent Limited by well capacity Q sat Limited by sensor read noise

7 Sensitivity : The ratio of voltage Response to the photo energy illumination Reset Reset Voltage Drop voltage Slope=Sensitivity Tint Output Performance Frame Rate reverse proportional to Readout time Output Voltage Light Intensity

8 1.1.5 Schematic Design vdd Ureset W=1uM L=0.35uM Ushutter Uselect W=5uM L=1uM W=1uM L=0.35uM C=195.6fF W=20uM L=1uM 15uM* 15uM N-diffusion Photodiode 750mv Vdc W=15uM L=1uM GND

9 Single APS Cell Schematic-Shutter Arrangement Simulated with Rest Signal (0.0V-3.3V,Pulse width 100uS,Delay Time 0S)

10 Single APS Cell Schematic-Shutter Arrangement Simulated with Rest Signal (0.8V-3.3V,Pulse width 100uS,Delay Time 0S)

11 1.1.5 Schematic Design vdd V1=0.8V V2=3.3V Pulse Width= 100us Delay Time=0s Ureset W=1uM L=0.35uM Ushutter Uselect W=5uM L=1uM W=1uM L=0.35uM C=195.6fF W=20uM L=1uM 15uM* 15uM N-diffusion Photodiode 750mv Vdc W=15uM L=1uM GND

12 Single APS Cell Schematic-Shutter Arrangement Simulated with Shutter Signal (0.0V-3.3V, Pulse width 270uS Delay Time 0 S)

13 Single APS Cell Schematic-Shutter Arrangement Simulated with Shutter Signal (0.0V-3.3V, Pulse width 540uS Delay Time 0 S)

14 Single APS Cell Schematic-Shutter Arrangement Iphoto(pA) v / Iphoto Vcap V/100pA Vcap V/100pA

15 1.1.5 Schematic Design vdd Ureset W=1uM L=0.35uM V1=0.0V V2=3.3V Pulse Width= 270us Delay Time=0s Ushutter Uselect W=5uM L=1uM W=1uM L=0.35uM C=195.6fF W=20uM L=1uM 15uM* 15uM N-diffusion Photodiode 750mv Vdc W=15uM L=1uM GND

16 Single APS Cell Schematic

17 Single APS Cell Layout

18 Single APS Cell LVS Check

19 Single APS Cell Analog-Extracted

20 Single APS Cell Test Schematic

21 Single APS cell Simulation-Output Voltage

22 Single APS Cell Simulation-Readout Time

23 APS Array Test Simulation

24 APS Array Schematic

25 APS Array Layout

26 APS Array LVS Check

27 APS Array Analog-Extracted

28 APS Array Test Schematic

29 APS Array Simulation

30 1.3 Results Technology 0.35um-4-metal COMS Quantum Efficiency -- Die Size 535.1uM*134.3uM Conversion Gain 0.818uV/e Array Size 4*16 Sensitivity 0.043/100pA Number of Transistor 256 Dynamic Range -- Pixel Size 32.7uM*32.3uM Output Voltage 1.166v (Iphoto =500pA) Photo Detector Type N-diffusion photodiode Readout Time 62.5nS (Iphoto =500pA) Number of Transistor/Pixel 4 Bias Current 51.47uA Fill Factor 21.3%

31 Biasing Current Circuit Design 2.1Application vdd Ureset Ushutter Uselect Vdc GND

32 Biasing Current Circuit Design 2.2 Formulas MOS Current Mirror Accuracy (Iin=Iout) Rout Aspect Ratio Calculation Poor 1 λiout Good 2 gmro Iout ( W / L) 2(1 + λvds 2) = Iin ( W / L)(1 1 + λvds1) Not Good gr m o 2 2

33 Biasing Current Circuit Design 2.3 Design Parameter No. of Project Dimension of Load TX (W/L Ratio) Type of load Transistor No. of Load Transistor Drain Current Project 1 1/1 NMOS uA Project 2 23/1 PMOS uA Project 3 Project4 23/1 NMOS uA Project5 1/2 NMOS uA Project6 15/1 NMOS uA Project uA

34 Biasing Current Circuit Design Raw Schematic

35 Biasing Current Circuit Design Raw Symbol Test

36 The End