Aptina MT9P111 5 Megapixel, 1/4 Inch Optical Format, System-on-Chip (SoC) CMOS Image Sensor

Transcription

1 Aptina MT9P111 5 Megapixel, 1/4 Inch Optical Format, System-on-Chip (SoC) CMOS Image Sensor Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Imager Process Review Some of the information is this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. IPR JMRF Revision 1.0 Published: December 17, 2009

3 Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Camera Module and Image Sensor Die 2.2 Die Features 2.3 Die Utilization Analysis 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral MOS Transistors 3.7 Poly Capacitors 3.8 Fuses 3.9 Isolation 3.10 Wells and Substrate 4 Pixel Analysis 4.1 Pixel Overview and Schematic 4.2 Planar Pixel Analysis 4.3 Cross-Sectional Pixel Analysis 5 SRAM Analysis 5.1 Overview 5.2 Planar SRAM Analysis 6 Critical Dimensions 6.1 Die Utilization 6.2 Die Features 6.3 Dielectrics 6.4 Metallization 6.5 Vias and Contacts

4 Imager Process Review 6.6 Peripheral MOS Transistors 6.7 Isolation 6.8 Wells and Substrate 6.9 Pixel Analysis 7 References 8 Statement of Measurement Uncertainty and Scope Variation About Chipworks

5 Overview Overview 1.1 List of Figures 2 Device Overview Camera Module Tilt View Camera Module Top Camera Module Side Camera Module X-Ray Side View Camera Module Bottom Lens Assembly Underside Image Sensor Housing Image Sensor Die and Substrate K28A Die Photograph Die Markings K28A Die Photograph Microlenses and Color Filters Removed K28A Die Photograph at Poly Analysis Sites Die Corner (A) Die Corner (B) Die Corner (C) Die Corner (D) Pixel Array Corner (A) Pixel Array Corner (B) Pixel Array Corner (C) Pixel Array Corner (D) Detail of Pixel Array Pixel Pitch Minimum Pitch Bond Pads Fuse Array Overview Fuse Array Detail (Depot Sample) Annotated Die Photograph NAND Equivalent Cell 3 Process Analysis Die Thickness Die Edge Die Seal Overview Detail of Die Seal General Structure Periphery General Structure Pixel Array Bond Pad Overview Detail of Bond Pad Passivation and IMD Passivation TEM IMD IMD 1 and PMD

6 Overview Minimum Pitch Metal Metal 3 and Metal 4 TEM Minimum Pitch Metal Metal 2 and Metal 3 TEM Minimum Pitch Metal Minimum Pitch Metal 1 (Logic Region) Metal 1 and Metal 2 TEM Minimum Pitch Via 3s Minimum Pitch Via 2s Via 1s and Via 2s TEM Minimum Pitch Via 1s Minimum Pitch Contacts Contacts TEM MOS Transistor Oxide Etch Contacted Gate Pitch Logic Transistor TEM Logic Gate Stack TEM Logic Gate Dielectric TEM NMOS Transistors Si Etch PMOS Transistors Si Etch Gate Wrap (Pixel Transfer Transistor) Pixel Array Column Capacitors at Poly (A) Pixel Array Column Capacitors at Poly (B) Pixel Array Column Capacitor Capacitor Contact Top Plate Capacitor Contact Bottom Plate Fuse Overview Intact Fuse Link Opened Fuse Link Minimum Width STI (Logic Region) Minimum Width STI (Pixel Array) STI Thickness P-Epi and Peripheral N-Well SCM SRAM Well Structure SCM Pixel Array Well Boundary SCM SCM Overview of Pixel Array Substrate Doping SRP Analysis Sites Pixel Array and Peripheral P-well SRP Analysis Site Peripheral N-well Peripheral N-well SRP Peripheral P-well and P-epi SRP Pixel Array SRP

7 Overview Pixel Analysis Pixel Schematic Microlens Array Tilt View (A) Microlens Array Tilt View (B) Microlens Array Tilt View (C) Microlens Array Pixel at Metal Pixel at Metal 1 and Via Pixel at Poly Pixel at Poly Nitride AR Removed Pixel at Diffusion Bevel SCM of Pixel Isolation Bevel SCM of N-Photocathode Optical Waveguide Above Metal Optical Waveguide Near Top (No Delineation) Optical Waveguide Near Bottom (No Delineation) Reference Pixels Top Left Reference Pixels Top Right Reference Pixels Bottom Right Reference Pixels Bottom Left Reference Pixels at Diffusion Pixel Cross Sections Top Edge of Pixel Array Start of Active Pixels Top of Pixel Array Detail of Pixel Array Dielectric Etch Back Top of Pixel Array Detail of Shielded Pixels Top of Pixel Array Pixels at Center of Array (Section A) Start of Active Pixels Bottom of Pixel Array Detail of Bottom Edge of Pixel Array Start of Active Pixels Left Edge of Pixel Array Edge Pixels (Microlens Shift at Horizontal Edge of Array) Pixel Overview Microlens and Lens Buffer Layer Red-Green Filter Pairs SEM Blue-Green Filter Pairs SEM Red Filter TEM Green Filter (in Red-Green Row) TEM Blue Filter TEM Green Filter (in Blue-Green Row) TEM Optical Waveguide (Section A) Optical Waveguide (Section B) TEM

8 Overview TEM-EDS Spectrum of Optical Waveguide Fill Pixel AR Layer TEM Transfer Gates (Parallel to Row Select, Section B) TEM Detailed Transfer Gate (Parallel to Row Select, Section B) TEM Transfer Gate Oxide TEM Transfer Gate Contact (Section C) TEM Pixel Substrate Doping (Section B) SCM N-Photocathode (Section B) SCM Readout Transistors Silicon Etch (Section D) TEM Overview of Readout Transistors (Section D) T5 (Reset) Gate Length (Section D) TEM T5 (Reset) Gate Width (Section A) T6 (Source Follower) Gate Length (Section D) TEM T6 (Source Follower) Gate Width (Section E) T7 (Row Select) Gate Length (Section D) TEM T7 (Row Select) Gate Width (Section F) Transfer Gate Finger (Section G) 5 SRAM Analysis SRAM Cell Schematic SRAM at Metal 2 Word View SRAM at Metal 2 Bit View SRAM at Metal 1 Word View SRAM at Metal 1 Bit View SRAM at Poly Word View SRAM at Poly Bit View SRAM at Diffusion Word View SRAM at Diffusion Bit View

9 Overview List of Tables 1 Overview Device Identification Device Summary Process Summary 2 Device Overview Die Utilization Die, Bond Pad, and Standard Cell Dimensions 3 Process Analysis Measured Dielectric Thicknesses Metallization Thicknesses Metallization Width and Pitch Via and Contact Dimensions Peripheral MOS Transistor and Poly Dimensions Isolation Critical Dimensions Well Depths and Die Thicknesses 4 Pixel Analysis Pixel Horizontal Dimensions Pixel Transistor Dimensions Pixel Vertical Dimensions TEM-EDS Elemental Pixel BEOL Analysis Summary 6 Critical Dimensions Die Utilization Die, Bond Pad, and Standard Cell Dimensions Measured Dielectric Thicknesses Metallization Thicknesses Metallization Width and Pitch Via and Contact Dimensions Peripheral MOS Transistor and Poly Dimensions Isolation Critical Dimensions Well Depths and Die Thicknesses Pixel Horizontal Dimensions Pixel Transistor Dimensions Pixel Vertical Dimensions TEM-EDS Elemental Pixel BEOL Analysis Summary