Simulation of High Resistivity (CMOS) Pixels

Transcription

1 Simulation of High Resistivity (CMOS) Pixels Stefan Lauxtermann, Kadri Vural Sensor Creations Inc. AIDA-2020 CMOS Simulation Workshop May 13 th 2016

2 OUTLINE 1. Definition of High Resistivity Pixel Also referred to as Deep Depletion (DD) or Fully Depleted (FD) Pixel 2. Challenges of High Resistivity Pixels Parasitic Bipolar Transistors 3. Advantages of High Resistivity Pixels Broad Spectral Sensitivity High Snapshot shutter Efficiency Nanosecond exposure time control High radiation tolerance 4. Summary 2

3 What is a Monolithic Deep Depletion (DD) CMOS Image Sensor (CIS)? Standard CIS (color) Deep Depletion CIS NMOS transistor Pixel Photodiode Pixel Color Filter Micro lenses Passivation layer (e.g. HfO 2 ) Electrical drift field V Only backside illuminated devices considered Deep Depletion CMOS Sensors have Thicker Active Absorption Region Than Standard CIS AR Coating Backside Electrode 3

4 Comparison of Standard versus Deep Depletion CMOS Sensor Standard CIS Deep Depletion CIS Fabrication Process CMOS CMOS with modifications Pixel Circuitry NMOS or PMOS (but not both) NMOS + PMOS Material Resistivity <10 Ohm x cm >1 kohm x cm Sensor Thickness < 10micron > 10micron Charge Collection Diffusion Drift Backside Electrode No Yes (unless EPI with build in field) Main application Visible cameras (mostly consumer) UV NIR cameras (scientific, industrial) Photo Sensor Pinned Photodiode PIN Photodiode Main Pixel Type 4T 3T (or derivative) Minimum pixel pitch 1 micron 4 micron Dark Current <10pA/cm 2 > 100pA/cm 2 (depending on thickness) Optoelectronic Performance of DD-CMOS Comparable to DD-CCDs (although not demonstrated in single CMOS device yet) 4

5 Comparison of Deep Depletion CMOS Technologies Optimum Performance Lowest Manufacturing Cost Least Developed Very few products hybrid FPA (not monolithic) 3D-IC (pseudo monolithic) Custom EPI layer (no backside contact) monolithic DD CMOS using high rho silicon 5

6 SCI s Deep Depletion CMOS Technology Well Structure 0V NMOS Deep Pwell PMOS PD N -- substrate µm -V back Deep P-well required to isolate circuitry from High Resistivity Silicon Electrons are collected by lateral and vertical drift fields. Deep Depletion Sensor is 3D structure with vertical and lateral Parasitic Bipolar Transistors 6

7 thickness thickness Electrostatic Potential in Thick Photodiodes with Backside Bias 0 mm front side Standard Silicon N Implant regions 3.4V High Rho Silicon 100 mm back side 100 mm thickness 0 mm -10.4V 100 mm thickness 0 mm Deep Photo Sensitive Region can only be Created in High Resistivity Silicon -10 V 3V Light absorbed in grey region cannot be detected 7

8 CMOS IC s on High Resistivity Silicon More Prone to Latch-Up PMOS NMOS R NWELL R Nsub - + R PWELL N -- substrate Latch up Tendency increases with Increasing R Nsub Decreasing C Increasing Q Parameters are worse in high rho Si compared to standard Si High resistivity Silicon Sensor IC Require Strong Substrate Connections to Minimize Latch-Up Probability 8

9 Parasitic Bipolar Transistors on High Resistivity Silicon 0V PD NMOS Deep Pwell PMOS PD N -- substrate Horizontal NPN Vertical PNP µm Horizontal NPN Risk of high current path between neighboring photodiodes Vertical PNP -V back Risk of high current path between front side Deep P-Well and backside electrode Firing of horizontal or vertical can significantly decrease sensor performance and must be avoided 9

10 Bipolar Transistors can be Completely Suppressed by Introducing an Extra Deep Nwell Implant vss DPWvssDNW GND Deep Pwell can be biased below GND Parasitic transistor is turned off November 19,

11 High Rho CIS Process Flow (Front Side) Preparation of 8 wafers for CMOS fabrication Implantation of deep P wells Standard CMOS IC fabrication Wafer thinning and polishing Deposition of Backside electrode Deposition of AR coating Simulated implantation profile Singulation of fully processed thinned CMOS wafers into individual chips Packaging DD CIS Fabrication Requires some Modifications to Baseline CMOS Process Plus Backside Post Process Thin film simulation of AR coating 11

12 Shallow Implantation + Laser Anneal on Back Side Measured implantation profiles for different laser light fluences Simulations are based on beam line implantation + furnace anneal All curves have the same implant energy and dosage: 1keV (minimum possible with simulator) 1E15at/cm 2 Anneal None (As implanted) 900C/1sec 900C/10sec For very shallow implants the profile is defined by annealing, not the implantation energy Profiles not well simulated with conventional beam line simulation approach followed by furnace anneal January 28,

13 3D Simulation of High Rho CMOS Pixel 15mm pixel pitch Cut plane Potential [V] 3.5 Cut line Potential [V] mm mm thick Si Backside Contact Backside illumination 3D Device Simulations are necessary especially for small pixels September16,

14 Absorption of Light in Silicon Photo-generated charge cannot be collected when generated in first ~0.1um of silicon Maximum depth for CMOS process boron and phosphorus implants Near InfraRed (NIR) Ultra Violet (UV) Most commercial CMOS sensors operate in visible domain High Resistivity Silicon Sensors Provide Benefits in Detection of Light Outside the Visible Domain 14

15 Comparison of Quantum Efficiency for Various Silicon Sensors Deep depletion sensor with broadband AR coating Backside illuminated deep depletion sensor Thick Backside Illuminated Sensor Front Illuminated Photodiode sensor (curves are generic not measured on DD-CMOS sensor) DD-CMOS Can Achieve QE of Best Scientific Silicon Sensors 15

16 Snapshot Shutter in Backside Illuminated Image Sensors Standard Silicon High Rho Silicon Photodiode Shutter transistor Storage Node (SN) Electronic shield around SN Photons can reach SN Without charge amplification extinction ratio limited to <70dB Photons are absorbed in thick active silicon region before reaching SN Backside Illuminated Image Sensor on 50 µm thick High Rho Silicon Achieves Extinction Ratio >120dB for 640nm without amplification 16

17 Nano Second Imaging N Front side N implant collection node V I High rho substrate (Intrinsic silicon) P Back side P implant electrode Sensor in high rho imager is a PIN photodiode Transit time of photo generated charge carriers in 100um FD CMOS imager with 100V backside bias < 1nsec, corresponding to a 3dB bandwidth > 1GHz Fully Depleted Imager on Intrinsic Silicon is Suited to Support Nanosecond Integration Time Windows 17

18 Dark Current on 50um Thick Silicon measured value Diode current is not zero at 0.0V Transition bias point shifted due to charge injection from backside electrode Measured on 1mm 2 large test pixel arrays, on wafer level, at room temperature 1V back bias was applied Measured Dark Current is Close to Predicted Depletion Current of <1nA/cm 2 at RT 18

19 Increased Tolerance to Radiation Induced Displacement Damage Published by Tomasz Hemperek CPIX 2014 Irradiation by heavy particles (proton, neutron) removes Si atoms from crystal lattice Also referred to as Non Ionizing Energy Loss Causes highly localized centers of leakage currents in imagers Different from Ionizing Energy Loss through X- and -rays Charge deposition in SiO 2 No good design counter measures available against Displacement Damage (DD) CMOS IC s can be hardened against X- and -rays by design Effect of displacement damage can be kept isolated in high rho silicon Efficient charge collection can be maintained if detector bias can increased through accumulation of damage Requires independent substrate bias control Thick High Rho Silicon Sensors Suited for Operation up to Very High Flux Levels <10 16 n eq /cm 2 19

20 Summary High rho CMOS pixels offer unique performance not achievable by any other sensor technology Front side processing compatible with capabilities of standard CMOS fabrication facilities Some modifications of standard recipes required New Process Design Kit (PDK) must be developed Backside processing mandatory to utilize all advantages CMOS circuits on front side limit temperature of backside process Very few high rho sensor products currently available Most high rho sensor chips are custom developments 20

21 Thank You for your attention!

22 About Sensor Creations, Inc. (SCI) Founded by Stefan Lauxtermann in 2010 Located in Southern California Affordable, ROIC and image sensor design Design (in house) Fabrication (through CMOS fab partner) Test (in house) Prototype and low volume packaging (in house) Extensive suite of silicon proven IP blocks available today Low noise snapshot shutter pixels with multi frame storage Low noise readout chain programmable Serial interface (SPI) 14bit high speed, low power column parallel ADC (measured) High speed I/O port with 1Gbit/sec (measured) Fully depleted backside illuminated CMOS imagers Custom designs Products Prototype Cameras 22

23 Absorption of Minimum Ionizing Particles (MIP) in Si Electron hole pair generation per micron of absorbing Si according to Bethe-Bloch calculation of mean energy loss of charged particles in Si Generated Electron-Hole pairs can only be detected if they are separated by an electric field Such as the electric field in the depletion region of a high resistivity sensor MIP Detector on High Resistivity Silicon Provides Maximum Detection Efficiency with the least Amount of Material in Beam Path 23

24 Absorption of Soft X-Rays in Si Absorption length of soft X-Rays in Silicon For direct X-ray detection active Si region must be thicker than possible in low rho Si Front to backside PIN (P-type Insulator N-type Si) diode used in high rho CMOS sensor Upper energy limit for direct X-ray imaging determined by scattering not limited absorption Monolithic CMOS Detectors on High Resistivity Silicon are Suited for Direct Image Detection of Soft X-Rays up to ~30keV 24