TAOS II: Three 88-Megapixel astronomy arrays of large area, backthinned, and low-noise CMOS sensors

Transcription

1 TAOS II: Three 88-Megapixel astronomy arrays of large area, backthinned, and low-noise CMOS sensors CMOS Image Sensors for High Performance Applications TOULOUSE WORKSHOP - 26th & 27th NOVEMBER 2013 Jérôme Pratlong, Bruno Gilli, Steve Bowring, Paul Jerram, Paul Jorden, Paul Trinder and Andrew Payne (e2v) Shiang-Yu Wang and Matt Lehner (ASIAA) John Geary (Harvard Smithsonian Center for Astrophysics)

2 NAS

3 TNOs smaller than 20Km diameter can t be directly detected by any telescope Occultation is the only way to detect them

4 Diffraction of Occultation The period for the occultation is about 0.2s. Better resolution in time can provide more information for the size and distance of the objects. TAOS2 sampling is 20Hz

5 Plausible Options Readout at 20MHz but with low noise Typical rate ~ few Ke 2e read noise can be achieved by amplifying the signal before readout Electron multiplication CCD (EM or L3 CCD) Readout the area with stars only 1000 stars in each chip 6x6 pixels per <100KHz CMOS sensor EM CCD generates more noise for bright objects and requires good gain control.

6 CMOS sensor needs Format : 4608 x 1920 (16µm pixel pitch) Pixel size : 10~16 microns QE : > 80% from 500~750nm Read noise : < 5e Full well : > 10000e Window switching time : < 0.5ms Total pixel rate : > 16Mpixel/s Dark rate : < 1e /s

7 Challenges CMOS detector design: Flexible access for windowing Large buttable device using stitching technology Low noise Astronomy detector therefore needs: Flatness of the packaging Backthinned High red QE Cryogenic cooling Slide 7

8 TAOSII detector: Architecture overview Focal plane using 10 image sensors of 1920 x 4608 size butted 16 µm square pixel pitch Array composed of 8 segments for parallel read-out Pixel array access by half row (left and right) independently ROI mode to speed up frame rate Multi-ROI mode access (both directions column and row) to concentrate on different area of the pixel array. Noise floor below 5e - RMS and low dark current. Slide 8

9 TAOSII detector: Architecture details 6 dummy rows Stitched block decoder Row decoder Row buffer 6 dummcolumns ioutput 1920 X 4608 Useful pixel (12x11 Dummy pixels 1 test line) 6 dummcolumns Row buffer Row decoder Stitched block decoder 5 dummy rows + 1 test line Read out path Global analogue bias Column decoder Serial column interface Serial row interface Output buffer Test block Serial row interface Pad Ring Slide 9

10 TAOSII detector: Generic access Option to acquire the next row while reading out the previous one. Slide 10

11 TAOSII detector: Readoutpath allowing acquisition of a row while reading Slide 11

12 TAOSII detector: row and column access Serial data in col_ser<7:0> col_clk col_load Column decoder approach by loading the address in a register first before sending the information to the local column decoder via a second register. Same concept used for row access. row_ser_in_l/r row_clk_l/r 13 bits register Pixel array The row address is sent to a register and when ready released to the local row decoder. row_load_l/r Row register 13 bits Row decoder This implementation does not any additional pin than a scan approach. A segment B segment Slide 12

13 TAOSII technology: Overview Tower have overcome potential lag effect. Photodiode - PPD Transfer gate STI PDP PD STI Dedicated light N-implant PWELL PDN PWELL Ground potential V PINNED P-Sub VSWING Reset potential Technology: 5T pinned photodiode pixel for low noise and anti-blooming feature 1-D Stitching Backthinned imager for high QE at high wavelength Epi starting material 18µm thinned down to 9µm (will be adjusted for best MTF) High resistance material 1Kohm.cm-1 Two layers ARC for high QE over the range of 500nm to 750nm Operational temperature between -40oC and possibly -100oC Slide 13

14 TAOSII Pixel: 5T approach Vrefr max about 2.8V Dark level 2.6V after feedthrough. 5 th transistor is working in anti-blooming With 0V on the gate. The 5 th transistor is driven by a logic signal: If programmed to 0V then it is an anti-blooming If programmed to toggle from 0V to supply then it acts as a global reset. Item Description TRANSISTORS M SF Nmos Source Follower amplifier transistor: low noise process. M SEL Nmos select transistor: low noise process. M TRA Nmos transfer transistor. M RST Nmos reset transistor: low noise process Nmos global reset transistor or Nmos anti-blooming transistor. Parasitic conversion capacitance SIGNALS sn Internal to the pixel sense node name sel Select command that connects to the gate of the transistor M SEL. tra Transfer command that connects to the gate of the transistor M TRA. rst Reset command that connects to the gate of the transistor M RST. g_rst Global reset command that connects to the gate of the transistor M G_RST. col Column connection output of the pixel. It is a common signal to all pixel from that column. vrefr Reset voltage level that is applied to the sense node prior to charge transfer. This supply is global to the array. vpix Source follower supply. This supply is global to the array. asub Substrate connection to minimise substrate effect due to the high resistivity material (1kOhm.cm -1 ) used. M G_RST C CONV Slide 14

15 TAOSII Pixel: Layout implementation This pixel is laid out that it is easily sizeable to 12µm pitch. Slide 15

16 Sensor organization Sensor organization as a function of the Stitch plan Segment A contains: Readout Pad ring Column and row registers Column decoders Bottom dummy pixels Segment B is repeated 4 times and contains: Useful pixels 1152 rows per section Column dummy pixels Row decoder and buffer Segment C contains: Top dummy pixels Seal ring Slide 16

17 TAOSII package: 3 sides buttable package Package non-sensitive area Sensor non-sensitive area 50µm 450µm ZIF socket interface (8x10 or 9x9) IMAGE SENSOR Readout area (non-sensitive are IMAGE SENSOR Sensitive area Sensor non-sensitive area 30.7mm 31.6mm Sensor non-sensitive area Package non-sensitive area 450µm 50µm 73.7mm Package 50µm ~76.3±0.3mm 200µm 50µm Requirement for the package: 3 sides buttability Flatness: Peak-to-Valley better than 30µm Value Focal plane sensitive area only 22626mm 2 Focal plane total image area 23818mm 2 Ratio between non-sensitive area and sensitive area Equivalent Fill Factor at focal plane 94% level. Slide 17

18 TAOSII Backthinned design packaging with 89 pins CMOS Device Invar 36 Package Invar 36 Shims (3 off) Spare Shim Position, not used 2 off Invar 36 Precision Pins PGA Pins Glue Channel Bond pads & Bond wires connecting device to PGA Invar 36 Shim Studs (3 off) Provision for Temperature Sensor (Not Shown) Stainless Steel Screws & Invar 36 washers Ceramic PGA Slide 18

19 TAOSII: Performance Parameter Description Typical estimated performance Units Pixel pitch 16 x16 µm Wavelength application 800 nm FF_BI Back Illuminated Fill Factor in Pixel > 87 % QE Quantum > 60 % Q LIN Linear charge capacity. 15 ke - Q SAT Saturation charge capacity: dominated by 22 ke - the conversion node and not the Pinned Photodiode. CVF Conversion Gain Factor at the output of 75 µv/e - the sensor Lag Residual charge after transfer from the 1 % pinned photodiode to the conversion node. RON Read Out Noise 3 e - RMS DC Dark o C e-/pixel/s MOVS Maximum Output Voltage Swing: 1.8 V Reset level Saturation level. FSR Full Scale Range: output Voltage Swing 1.2 V within linearity level. DR Dynamic range over FSR 74 db Detector will be cooled low enough (about -40oC or below) to meet the 1e-/pixel/s requirement. Non Linearity Error Non Linearity from 5% to 90% of FSR. +/-1 to +/-2 % MTF Modulation transfer 48 % Slide 19

20 TAOSII detector: Flexibility in format BASELINE OPTIONS 4608 X X X X µm pixel pitch: 16µm pixel pitch: 16µm pixel pitch: 16µm pixel pitch: ~ 76.5mm X 31.6mm ~ 58mm X 31.6mm ~ 39.6mm X 31.6mm ~ 21mm X 31.6mm 12µm pixel pitch: 12µm pixel pitch: 12µm pixel pitch: 12µm pixel pitch: ~ 57.5mm X 23.5mm ~ 43.6mm X 23.5mm ~ 30.0mm X 23.5mm ~ 16.0mm X 23.5mm Slide 20

21 TAOSII: Planning 27 th November 2013 Mid-December 2013 Tape-out End March 2014 Wafers at e2v End July 2014 end characterisation Slide 21

22 TAOSII: e2v back face QE measurements on CIS107-4T - 7µm pixel pitch QE Plot at 20 C ) 100% 90% 80% 70% 60% 50% 40% 30% 20% QE Astrium % 0% Wavelength (nm) NB this data is for a two layer AR coating. The model and the measured results are in good agreement indicating that all or nearly all of the generated electrons are gathered by the photodiode. QE is >80% from 450 to 750nm Slide 22

23 TAOSII: Etalon effect front face and back face comparison measured on CIS107 CIS107 4T pixel 7µm pixel pitch FrontFace QE CIS107 4T pixel 7µm pixel pitch BackFace QE Slide 23

24 TAOSII: e2v MTF measurement on high resistivity material CIS107 Thinned to 11µm with a depletion of about 7µm to 8µm. Thinned to 7µm with a depletion of about 1µm to 2µm.. On TAOSII the target will be to thinned between 9µm to 11µm. Experiment might be done to optimise this parameter versus QE Slide 24

25 Conclusion In order to meet the TAOSII image sensor requirements a CMOS detector has been chosen specified with an high level of flexibility leading to the following features: Pixel: 5T technology with a pixel pitch of 16µm. Noise floor aimed at 3e - RMS and 74dB dynamic range (in rolling shutter only) Cryogenic dark current < 1e-/pixel/s (on-going activity at e2v to test similar pixel down to -80oC) 8 each or 16MHz in total with possibility to extend each output to 7MHz. Region of interest and Multi-ROI available in both directions. Possibility to jump in both directions. Row access by half of the row: left half and right half independent access. Read while acquiring pixel of the next row. High frame rate, combining pixel acquisition while reading and ROI/JUMP, down to 6µs. Rolling shutter and electronic global shutter modes available. Anti-blooming built-in. Solution stitch-able 1D. The first results are expected by end summer Slide 25

26 Acknowledgements Special Thanks Shiang-Yu Wang from ASIAA Matt Lehner from ASIAA John Geary from Harvard Smithsonian Center for Astrophysics e2v co-writers and reviewers Slide 26