CMOS Today & Tomorrow

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1 CMOS Today & Tomorrow Uwe Pulsfort TDALSA Product & Application Support

2 Overview Image Sensor Technology Today Typical Architectures Pixel, ADCs & Data Path Image Quality Image Sensor Technology Tomorrow Architecture Outlook Image Quality Outlook BSI

3 CMOS Image Sensor Technology Today

4 Image Sensor Architecture - Line O/F O/F O/F O/F Temp PLL ADC ADC Sensor ADC ADC CDS CDS Timing Core CDS CDS Horizontal Read Rails Shift Registers Column Support Circuits (BIAS, S&H, etc.) Pixel Array Dual Line 7.04um square pixels Column Support Circuits (BIAS, S&H, etc.) Horizontal Read Rails Shift Registers CDS CDS Timing Core CDS CDS ADC ADC Temp ADC ADC PLL Sensor O/F O/F O/F O/F Example Models: P4 Series (2k - 16k Resolution) Multi-Line Colour sensors Pixel Design partially Pinned Photo Diode Rolling Shutter with CDS High Resolution possible with large pixels Capable of a few rows only Analog Path Correlated Double Sampling Stand-Alone ADCs 12bit, ~50MSps High power consumption Digital Path Serial Data LVDS up to 480Mbps per lane ~ 40 Mpix/s per lane (2 Pins) All Controls on-chip

5 Image Sensor Architecture - Area Isolation & Dark Rows Digital Timing Generation EXSYNC Pixel Design Isolation Columns Image Region Isolation Columns Row Decoder and Row Drivers SPI Clock Generation User Optimize Data Read-Back MCLK Pinned Photo Diode Global Shutter No or limited CDS High Resolution small pixel Isolation Rows Image Array Voltage buffers Analog Processing ROW [0] Bias Generation Analog Path Gain, Double Sampling Column-wise ADC ADC DATA PATH test pattern ROI address row address Ramp Generation 8-11bit, 5-10ms per row Digital Path 10bit COL [0] LVDS I/O STROBE FVAL LVAL Example Models: Parallel LVDS up to 480Mpix per tap All Controls on-chip FALCON 4M60 / 1.4M100, FALCON 2 12M58 GENIE HM, GENIE TS

6 Some Details - Pixel

7 CMOS Pixel Structures PRST RRST VDDI 3T 4T COL 5T PPD FD RSEL TG Multi-T I

8 CMOS Pixel Selection Pixel determines Basic Function & Capability of System Pixel 3-Transistor 4-Transistor 5-Transistor Multi-T Features Best Fill Factor, high Saturation, simple Architecture Elektronic Global Shutter not possible Limited possibilities for Adaptation (FW, CCE, NEE, ) Rolling Shutter with CDS (low noise) Global Shutter without CDS and without Exposure Control Better Fill Factor, good saturation level stop action function comparable to CCD ILT Global Shutter with Exposure Control possible Good Fill Factor, good saturation level Many Ideas, few products with 6, 7, 8 or more transistors Lowest Fill Factor, lowest saturation level Main Goal: Global Shutter with CDS (low noise) 8

9 Some Details - ADC

10 CMOS Image Sensor - ADC Selection ADC Single Slope Successive Approximation / Algorithmic Multi-Slope Sigma Delta Status Commonly used (various Models), 10-14bit No Linearity issues, low power consumption (up to ~Gbps) Low complexity, allows narrow column pitch Conversion rate limited by linear Ramp and counter Best candidate for 2 nd place in Image Sensors Potential to reach lowest power consumption Requires complex circuitry within a column Very tight connection between: column pitch, power, bit depth and bit rate - specifications need to be traded-off against each other Rarely outside of research projects Often shows linearity issues between coarse and fine steps Rare in the past, gaining with increasing bit depth and bit rate Very fast, with oversampling; enables high bit depth and rate Requires complex analog an digital circuitry High power consumption and complicated column construction 11

11 Some Details - Outputs

12 CMOS Outputs Digital data rate influences Line Rate and power consumption Output Analog CMOS I/O LVDS / Sub-LVDS SerDes Status Standard in CCD and older CMOS, today in special cases Mpix/s/pin, ADC components in camera Typical for communication with Sensor Slow (and today rare) to output data, 5-10 Mpix/s/pin Typical Data Format, sometimes also for communication Hardware Layer of the CameraLink Standard ~30mW/lane (10mW/lane), Mpix/s/lane, fully digital, robust Computer Standard today: CPU, memory, SATA, PCIx, Hardware Layer of the CLHS Standards (FALCON2, P4) ~10mW/lane, Mpix/s/lane, fully digital, robust No application in CMOS Image sensors as yet 13

13 Enables higher Integration CMOS in Imaging... ADC, biasing, controls integrated in chip Programmable, self or single-trigger Operation Delivers higher Speed Fast ADCs and/or highly parallel Processes High digital Data rates with low power consumption Offer extended Functionality Integration Control: Global Shutter, Exposure Control Frame-to-Frame Functions: Windowing, Gain, Resolution,... Application Adaptation: Bit depth, Snap Shot Mode,... Special functions: Wide Dynamic Range, shutter modes,...

14 Image Quality

15 Between Saturation and Noise Future Technologie needs to: Reduce Noise Global Shutter ~10 e- desirable Today ~ 1 / 1000 FW (DNR 60dB) Full Well - maintain or increase 30-40ke- desirable ~40ke- SAT Despite 4x Gain SNR in dark regions is too low - noise needs to be reduced Good image content, but Display-DNR hinders readability ~10ke- SAT Good readability with 4x Gain ~10ke- SAT Signal: ~ 5.25ke- Background: ~ 4.25ke- Contrast: 21% SNR: ~10 Signal: ~ 7.00ke- Background: ~ 4.00ke- Contrast: 54% SNR: ~70 Bright spots saturated - Higher FW required

16 Sensitivity number of photons is limited by system Sensor should capture all photons Fill Factor (FF) measures photons available per pixel Also influences acceptance angle, colour reproduction and MTF Sensor needs to convert all photons into electrons Quantum Efficiency (QE) measures photons converted per pixel Silicon property, can be influenced through process technology Wavelength dependent Typical Spec is eff. QE, measured as FF*QE Goal: More Electrons per Pixel with same Lighting

17 Optisches Pixel Design Acceptance Fill Factor Angle microlens optical layers optical layers electrical layers electrical layers Wafer and Photodiode Wafer and Photodiode

18 QE [%] Outside the visual Spectrum Typical QE (e.g. TD Falcon2) Monochrome vs. Colour e.g. IR Enhanced Infrared Capture Silicon up to ~1100nm Thick-EPI Wafer Material NIR and VIS filter layers UV Capture < 400nm UV-transparent Coverglass Special process steps 25.0% UV Erfassung 20.0% 15.0% 10.0% 5.0% SPEZ STD 0.0% Wavelength (nm)

19 CMOS Image Sensor Technology Tomorrow

20 The Future Architecture - I Line Scan Cost Efficient 1-Line Fast Multi-Line (> 4n) Higher Sensitivity TDI-Capability High Colour Quality Line Rates above 100 khz Area Scan Smaller Pixel (1-4 mm) Highest Resolution, lowest $/Mpix Trade-Offs in FW, NEE Larger Pixel (4-8 mm) Increasing Resolution (>12M) FW remains, reduced noise Frame Rates with 2+ GPix/s Shorter Pixel-to-Digital Path Merging Development Reduced Noise with same functionality (e.g. Gain) 12bit Column ADC with ~1 MSps, ~12bit DNR Serial High-Speed Outputs Up to 3 Gbps Mpix/s per Pin, 8b/10b encoding

21 The Future of Image Quality Area & Linescan Sensors: Reduced Noise Direct Pixel-to-ADC and Column-wise ADC Technology CDS Technology Also: High Full Well, Higher Resolution, High Fill Factor Multi-Line Sensors: Higher Sensitivity More Rows per Pixel TDI Principle Special Applications: Colour Linescan with n rows per colour or m colours Wide Dynamic Range High Full Well, reduced noise higher Dynamic Range Higher Fill Factor (e.g. Back-Side Illumination (BSI))

22 BSI Back-Side Illumination Back-Side Illumination Wafer thinned to mm Readout at front-side Advantages Std. Wafer e Optisch & Elektrisch Aktive Pixel reduzieren Füll Faktor Ausgedünnter Wafer e Elektrisch Aktive Pixel ohne Einfluß auf Lichtpfad High Fill Factor (no circuitry in light path) High QE (Stack optimized for optics, not electronics) More space in pixel for circuitry Technology increasingly available Wafer Thinning & Treatment for CCD and CMOS Optimization of specialized processes Still expensive, but increasing availability will reduce cost

23 Thank You for your Reducing the cost of products we use everyday Attention! Questions? Inspecting electronic components

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