A Review of Phase Locked Loop Design Using VLSI Technology for Wireless Communication.
|
|
- Ambrose Crawford
- 6 years ago
- Views:
Transcription
1 A Review of Phase Locked Loop Design Using VLSI Technology for Wireless Communication. PG student, M.E. (VLSI and Embedded system) G.H.Raisoni College of Engineering and Management, A nagar Abstract: The wireless communication systems are very useful in day to day life application. A phase locked loop is used as a main part of the system. It is used at the receiver of the wireless communication. The PLL is used to generate a proper output frequency as per the antenna reception. In the designing of this system, various individual systems are combined. In the designing of system, we have to consider a multiple working parameter. These are power requirement of system, output frequency, required input signals and designing technology etc. w. r. to Phase Locked Loop. For the designing of high end phase locked loop, we have to achieve low power consumption with higher frequency generation rate. The newly invented technology is working at the CMOS level designing of any system. The researchers are now developing a various software to achieve these features. As per the literature survey of Phase Locked Loop, the researchers are working on various parameters of working and designing. Researchers are designing a same system by various methods. There are two types of PLL designing. These are analog and digital. This paper is describing the survey of various already designed systems. Also this paper is helpful in getting the market requirements. Key words: Phase Locked Loop (PLL), Voltage Controlled Oscillator (VCO), VLSI technology, Microwind 3.1, low power, 45nm technology. 1. INTRODUCTION The electronics industry is now developing due to various newly invented technology. The electronics industry has reach a fast growth from last two decades, because the advancement in integration technology that is very large scale system design- in short advancement in the VLSI. In the high performance computing telecommunication and consumer electronics, the multiple applications has been rising steadily, and at fast pace. Typically, the required total power of these applications is the working force for the far development of this field. The power is one of the most important specification in designing of system for multi 1 gigahertz communication systems such as wireless devices, microprocessors and controllers, system on chip and ASICs [1]. Power consumption is an important parameter in the microprocessor design. The core of microprocessor requires largest power density on the microprocessor. The supply voltage can be reduced leading to reduction of static and dynamic power consumption of the circuit. But the reduced power supply can effect on the performance of the system, which is unacceptable. 2. NECESSITY The power is a very important parameter in designing of any on chip system. Also the portability of devices is a requirement of users. The high speed performance and low processing power is also a market requirement. The device should be very smart and intelligent to give an answer to individual demands with respect to broadcasting. 3. PROPOSED SYSTEM To lock the phase of input reference signal and feedback signal produced by VCO, the digital phase locked loop is used. Then this signal passes to the divider circuitry. The basic parts of a PLL is includes three main blocks Phase detector (PD). Loop filter and charge pump Voltage controlled oscillator (VCO) The phase detector basically used to compare the phase of two signals. Here, the phase detector compares phase of input signal and phase of VCO signal. The phase detector compares a phase difference between two signals and produces a difference voltage. The difference voltage is depends on the phase difference of the two inputs of phase detector. The difference voltage will passes through the filter circuit. The filter circuit is used to reduce the unwanted part of the signal [2]. Then output of the filter is applied to the input of VCO as a Vcontrol. The VCO produces the
2 frequency that reduces the phase difference of input signal and local oscillator. The signals are in phase, when the loop is locked. The pull in time is the period of frequencyacquisition. It should be very long or very short, which depends on the bandwidth of phase locked loop. F in Phase detector (XOR Gate) Loop Filter (RC Filter) Voltage controlled oscillator Figure 1. Block diagram of PLL. F out 3.1 Phase Detector Two broad categories of phase detector are: Multiplier circuits Sequential circuits. Multiplier means average product generation. The product of input signal waveform and local oscillator waveform is generated and the DC error signal is obtained. Properly designed multiplier system can operate on an input signal with multiple noise signals. The working of sequential phase detector depends on the zero crossing of the signals. Sequential phase detector generates a output voltage which is function of time interval between the zero crossing of two signals. We can find the phase and frequency difference of signal by using a sequential detectors There are two main phase detectors Multiplier as detector. XOR phase detector Multiplier as detector The multiplier phase detector has superior noise performance to all other detectors. This detector operates on the whole input and VCO signal rather than quantizing them to one bit. The PLL is mostly used in a microwave frequency applications and low noise synthesizers so balanced mixers are best suited for PLL. This will results in loop, whose gain is dependent upon the signal amplitude [3]. If non-idealities are implemented in circuit, mixer output is also nonlinear. Figure 2. Mixing phase detector It is advantageous to move to a detector that has immunity to these effects, when noise is not an issue. For multiple reasons, that detector may be desirable to have loop which produces a square wave instead of sinusoidal clock. If anyone over runs the mixer circuit, which is if one uses signals with large amplitudes that the amplifiers saturate, the output signals stop looking sinusoids and start looking like rectangular signals. That a phase detector is shown in Figure. The output of such a phase detector depends on a combination of averaging analysis and heuristics. The one most important feature of the phase detector is that it can be implemented ordesigned using an XOR gate that is Exclusive OR which is shown in figure. In XOR phase detector, the loop gain is independent of input signal amplitude. An XOR phase detector soutput have a larger linear range than a sinusoidal detector (mixer) XOR phase detector The phase detector compares two signals with respect to their phase. There are two basic types of the phase detectors these are analog and digital. In development of the analog filter, the multiplier circuit is applicable. It will take a product of two signals and shows a resulting signals. For development of digital phase detector, we are using a XOR logic gate. The XOR gate is designed by using various logic gates i. e. AND and OR gate[4][9]. Figure 3. CMOS design of XOR gate 2
3 3 Table 1. Truth table of XOR gate Input Output Loop filter The loop filter is used to improve the performance of the PLL. o Attenuates high frequency noise of the detector o Increases the hold and capture ranges o Increases the switching speed of the loop in lock. o Easy way to change the dynamics specifications of the PLL Figure 4. Concept of filter A loop filter means a Low pass filter, which passes only a low frequency signals and attenuates the frequencies which are above the cut off frequency of the filter. By observation of transfer function, we can say the gain of filter is more at low frequencies than at higher frequencies. Figure 5. Transfer function of low pass filter Figure 6. RC low pass filter Filter parameters o Accuracy: To achieve an accuracy using a passive and active filter techniques requires the use of very accurate resistors, capacitors, and sometimes inductor. Accurate components reduces errors. o Cost: The passive RC network is a ideal solution to the requirement of single pole filter. When good accuracy is requirement, the passive components, basically the capacitors, used in the discrete system is very costly; this is very important in very compact designs that require surface-mount components. o Noise: Passive filters generate very less noise, and conventional active filters have lower noise than switched-capacitor ICs. o Offset Voltage: Passive filters does not have inherent offset voltage. When a filter is designed from op amps, resistors and capacitors, then offset voltage will be a function of the offset voltages of the op amps and dc gains of the various stages of filter. o Frequency Range: A passive circuit or an op amp/resistor/ capacitor circuit are developed to operate at very low frequencies, but it will require some very large, and probably expensive, reactive components. o Tunability: It is the ability of filter to attenuate and pass a proper signal. A conventional active and passive filters are designed to have for any center frequency. The center frequency can be changed by changing the values of designing components like resistors and capacitors used. o Aliasing: It means mixing of high frequency signal with low frequency signal. This problem can be solved by simply adding a RC low pass filter at the output that removes some unwanted signals of high frequency. o Design Effort: this advantage is depends on the requirement of the designed application. The easiest way is to use devices, require nothing more than clock. 3.3 Charge pump If output frequency or phase is too slow, then charge pump sources current. Charge pump sinks current if output frequency or phase is too high. It is useful in copying currents. The VCO is basically used to generate a clock at output of PLL. The clock varies by 50 percent at positive or negative of the central frequency for which current mirror or current started circuits will be used. Charge pump
4 circuits will used to transfer a digital error signal to analog error current [5]. Advantages of charge pumps o Less power consumption than active filters o Less noise at output than active filters o Not have offset voltage of op amps o Provide a pole at the origin or zero. o More compatible with putting the filter on chip 3.4 Voltage Controlled Oscillator It is the most important functional unit in the Phase Locked Loop. Its output frequency shows the effectiveness of PLL. For operating at highest frequency VCO unit consumes the most of the power in the system. The Voltage Controlled Oscillator is developed by using ring oscillator of 7 stages. Ring oscillator is easy and simple to construct and operate using CMOS, as inverter is its basic element. VCO is particularly focussed to reduce the power consumption of the system. The objective of the project is to design a gigahertz frequency range and less power consumption that is in microwatts. Also less phase noise at CMOS VCO. The voltage controlled oscillator gives the output frequency which is controllable by its input voltage. The VCO is commonly used for clock generation in phase lock loop circuits. The current starved inverter chain uses a voltage control to change the current that flows in the N1, P1 branch. The current flowing through N1 and other three NMOS is same, means is mirrored by N2, N3 and N4. The same current flows through P1. The current through P1 is mirrored by P2, P2 and P4. At same time, the change in Vcontrol will shows a global change in the inverter currents, and works directly on the delay. Figure 7. VCO CMOS design 5. SYSTEM SOFTWARE S The system development means describing the various stages of system implementation. It is very necessary to plan How to complete our project. The system development is divided in two important parts i.e. software development and hardware development. This project is totally software dependent project. Here, I am designing a CMOS level design of Phase Locked Loop (PLL). For designing purpose, we are using a MICROWIND 3.1 designing tool. 5.1 Software MICROWIND The designing of physical mask layout of any circuit is made by using a particular process. That uses a set of geometric constraints or rules, which are called layout design rules. The layout design rules are describes a minimum allowable line widths for on chip systems like poly silicon interconnects or diffusion areas, metals, minimum feature dimensions and allowable separations between two designs. If a metal line width is made too small, for example, any line may be breaks during generation process which makes open circuit. When two lines are placed very near to each other in the layout, they may form an unwanted short circuit during or after the fabrication process. The main objective of design rules is to obtain a high overall yield and reliability while using as small as possible silicon area, for any circuit that is manufactured with a particular process [6]-[8]. Table 2. Available CMOS technology Technology file available Minimum gate length Value of lambda Cmos12.rul 1.2µm 0.6µm Cmos08.rul 0.7µm 0.35µm Cmos06.rul 0.5µm 0.25µm Cmos035.rul 0.4µm 0.2µm Cmos025.rul 0.25µm 0.125µm Cmos018.rul 0.2µm 0.1µm Cmos012.rul 0.12µm 0.06µm Soi01.rul 0.12µm 0.06µm Cmos90n.rul 0.1µm 0.05µm Cmos65n.rul 0.07µm 0.035µm Cmos45n.rul 0.05µm 0.025µm 4
5 5.2 Key features of Microwind : Microwind 3.1 is a layout & simulation tool that can be useful in whole micro-electronics engineering, flexible engineering and science. Microwind 3.1 is a program to provide designers with a hands-on learning experience on nanometer technology. Microwind 3.1 is easy to learn and use so you can focus more of your time on design issues, and less on programming. Microwind 3.1 unifies schematic entry, pattern based simulator, SPICE extraction of schematic, Verilog extractor, cross sectional & 3D viewer,layout compilation, on layout mix-signal circuit simulation,, net list extraction, MOS devices and sign-off correlation is used to unmatched design performance and designer productivity. 6. CONCLUSION Here, author surveyed a various papers. From that anyone can conclude that a PLL system is a combination of various small systems that is phase detector, loop filter, pre-charge circuit and voltage controlled oscillator. Also it describes a specifications of small system and their actual use in the system. The VLSI technology is basically describes a CMOS level designing of the system means a back end design. For designing of that, multiple software are available. The Microwind is a very useful software also handing of that is easy. We can develop a system using that software. REFERENCES [1] Chih-Ming Hung and Kenneth K. O, A Fully Integrated 1.5-V 5.5-GHz CMOS Phase-Locked Loop, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 4, APRIL 2002 [2] Fernando Rangel de Sousa, Student Member, IEEE, and Bernard Huyart, Member, IEEE, A Reconfigurable High-Frequency Phase-Locked Loop, IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 53, NO. 4, AUGUST 2004 [3] Jung-Chien Li and Guan-Chyun Hsieh, Member, IEEE, A Phase/Frequency-Locked Controller for Stepping Servo Control Systems, IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 39, NO. 2, APRIL 1992 [4] Jri Lee, Mingchung Liu, And Huaide Wang, A 75- Ghz Phase-Locked Loop In 90-Nm CMOS Technology in IEEE JOURNAL OF SOLID- STATE CIRCUITS, VOL. 43, NO. 6, JUNE 2008 [5] ChaitaliP.Charjan, Asso.Prof.AtulS.Joshi, Phase Locked Loop Using VLSI Technology For Wireless Communication In International Journal Of Innovative Research In Electrical, Electronics, Instrumentation And Control Engineering Vol. 2, Issue 4, April 2014 [6] Ms.Ujwala A. Belorkar and Dr.S.A.Ladhake Design of low power phase locked loop (PLL) using 45nm VLSI technology, in International journal of VLSI design & Communication Systems (VLSICS), Vol.1, No.2, June 2010 [7] ChaitaliP.Charjan, Asso.Prof.AtulS.Joshi Implementation of 2.4 GHz Phase Locke Loop using Sigma Delta Modulator, in International Journal of Application or Innovation in Engineering& Management (IJAIEM) Volume 3, Issue 3, March 2014 [8] VaishaliBhimte, VaishaliPande, Design Of Pd And High Performance Vco For Pll With 45 Nm Cmos Technology In International Journal Of Pure And Applied Research In Engineering And Technology A Path For Horizing Your Innovative Work (Ijpret), 2013; Volume 1(8): [9] DelvadiyaHarikrushna, Prof.Mukesh Tiwari, Dr.AnubhutiKhare, Prof. Jay Karan Singh, Design, Implementation And Characterization Of Xor Phase DetectorforDpll In 45 Nm Cmos Technology, in Advanced Computing: An International Journal ( ACIJ ), Vol.2, No.6, November
Phase Locked Loop using VLSI Technology for Wireless Communication
Phase Locked Loop using VLSI Technology for Wireless Communication Tarde Chaitali Chandrakant 1, Prof. V.P.Bhope 2 1 PG Student, Department of Electronics and telecommunication Engineering, G.H.Raisoni
More informationINTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY
INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY A PATH FOR HORIZING YOUR INNOVATIVE WORK DESIGN OF PD AND HIGH PERFORMANCE VCO FOR PLL WITH 45 nm CMOS TECHNOLOGY VAISHALI
More informationInternational Journal of Scientific & Engineering Research, Volume 4, Issue 6, June ISSN
International Journal of Scientific & Engineering Research, Volume 4, Issue 6, June-2013 1 Design of Low Phase Noise Ring VCO in 45NM Technology Pankaj A. Manekar, Prof. Rajesh H. Talwekar Abstract: -
More informationHIGH PERFORMANCE VOLTAGE CONTROLLED OSCILLATOR (VCO) USING 65NM VLSI TECHNOLOGY
HIGH PERFORMANCE VOLTAGE CONTROLLED OSCILLATOR (VCO) USING 65NM VLSI TECHNOLOGY Ms. Ujwala A. Belorkar 1 and Dr. S.A.Ladhake 2 1 Department of electronics & telecommunication,hanuman Vyayam Prasarak Mandal
More informationDesign of Phase Locked Loop as a Frequency Synthesizer Muttappa 1 Akalpita L Kulkarni 2
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 03, 2015 ISSN (online): 2321-0613 Design of Phase Locked Loop as a Frequency Synthesizer Muttappa 1 Akalpita L Kulkarni
More informationDesign of an Efficient Phase Frequency Detector for a Digital Phase Locked Loop
Design of an Efficient Phase Frequency Detector for a Digital Phase Locked Loop Shaik. Yezazul Nishath School Of Electronics Engineering (SENSE) VIT University Chennai, India Abstract This paper outlines
More informationCHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC
138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit
More informationDesign of 2.4 GHz Oscillators In CMOS Technology
Design of 2.4 GHz Oscillators In CMOS Technology Mr. Pravin Bodade Department of electronics engineering Priyadarshini College of engineering Nagpur, India prbodade@gmail.com Ms. Divya Meshram Department
More informationAn Efficient Design of CMOS based Differential LC and VCO for ISM and WI-FI Band of Applications
IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 10 April 2016 ISSN (online): 2349-784X An Efficient Design of CMOS based Differential LC and VCO for ISM and WI-FI Band
More informationLow Cost Transmitter For A Repeater
Low Cost Transmitter For A Repeater 1 Desh Raj Yumnam, 2 R.Bhakkiyalakshmi, 1 PG Student, Dept of Electronics &Communication (VLSI), SRM Chennai, 2 Asst. Prof, SRM Chennai, Abstract - There has been dramatically
More informationComparison And Performance Analysis Of Phase Frequency Detector With Charge Pump And Voltage Controlled Oscillator For PLL In 180nm Technology
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 4, Ver. I (Jul - Aug. 2015), PP 22-30 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Comparison And Performance Analysis
More informationA 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS
A 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS Diary R. Sulaiman e-mail: diariy@gmail.com Salahaddin University, Engineering College, Electrical Engineering Department Erbil, Iraq Key
More informationFFT Analysis, Simulation of Computational Model and Netlist Model of Digital Phase Locked Loop
IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 10 April 2016 ISSN (online): 2349-784X FFT Analysis, Simulation of Computational Model and Netlist Model of Digital Phase
More informationDesign of CMOS Phase Locked Loop
2018 IJSRST Volume 4 Issue 2 Print ISSN: 2395-6011 Online ISSN: 2395-602X Themed Section: Science and Technology Design of CMOS Phase Locked Loop Kaviyadharshini Sivaraman PG Scholar, Department of Electrical
More informationDesign and Implementation of Phase Locked Loop using Current Starved Voltage Controlled Oscillator in GPDK 90nM
International Journal of Advanced Research Foundation Website: www.ijarf.com, Volume 2, Issue 7, July 2015) Design and Implementation of Phase Locked Loop using Starved Voltage Controlled Oscillator in
More informationAn Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS Technology
IJIRST International Journal for Innovative Research in Science & Technology Volume 2 Issue 10 March 2016 ISSN (online): 2349-6010 An Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS
More informationAnalysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition
Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition P. K. Rout, B. P. Panda, D. P. Acharya and G. Panda 1 Department of Electronics and Communication Engineering, School of Electrical
More informationPhase Locked Loop Design for Fast Phase and Frequency Acquisition
Phase Locked Loop Design for Fast Phase and Frequency Acquisition S.Anjaneyulu 1,J.Sreepavani 2,K.Pramidapadma 3,N.Varalakshmi 4,S.Triven 5 Lecturer,Dept.of ECE,SKU College of Engg. & Tech.,Ananthapuramu
More informationOptimization of Digitally Controlled Oscillator with Low Power
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 6, Ver. I (Nov -Dec. 2015), PP 52-57 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Optimization of Digitally Controlled
More informationImplementation of 2.4 GHz Phase Locked Loop using Sigma Delta Modulator
Implementation of 2.4 GHz Phase Locked Loop using Sigma Delta Modulator Chaitali P.Charjan 1, Asso.Prof.Atul S.Joshi 2 1 PG student, Department of Electronics & Telecommunication, Sipna s college of Engineering
More informationA New Approach for Op-amp based VCO Design Using 0.18um CMOS Technology
International Journal of Industrial Electronics and Control. ISSN 0974-2220 Volume 6, Number 1 (2014), pp. 1-5 International Research Publication House http://www.irphouse.com A New Approach for Op-amp
More informationAn Analog Phase-Locked Loop
1 An Analog Phase-Locked Loop Greg Flewelling ABSTRACT This report discusses the design, simulation, and layout of an Analog Phase-Locked Loop (APLL). The circuit consists of five major parts: A differential
More information/$ IEEE
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006 1205 A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for
More informationISSN: International Journal of Engineering and Innovative Technology (IJEIT) Volume 1, Issue 2, February 2012
A Performance Comparison of Current Starved VCO and Source Coupled VCO for PLL in 0.18µm CMOS Process Rashmi K Patil, Vrushali G Nasre rashmikpatil@gmail.com, vrushnasre@gmail.com Abstract This paper describes
More informationLecture 7: Components of Phase Locked Loop (PLL)
Lecture 7: Components of Phase Locked Loop (PLL) CSCE 6933/5933 Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages,
More informationECE1352. Term Paper Low Voltage Phase-Locked Loop Design Technique
ECE1352 Term Paper Low Voltage Phase-Locked Loop Design Technique Name: Eric Hu Student Number: 982123400 Date: Nov. 14, 2002 Table of Contents Abstract pg. 04 Chapter 1 Introduction.. pg. 04 Chapter 2
More informationA VCO-based analog-to-digital converter with secondorder sigma-delta noise shaping
A VCO-based analog-to-digital converter with secondorder sigma-delta noise shaping The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters.
More informationIntegrated Circuit Design for High-Speed Frequency Synthesis
Integrated Circuit Design for High-Speed Frequency Synthesis John Rogers Calvin Plett Foster Dai ARTECH H O US E BOSTON LONDON artechhouse.com Preface XI CHAPTER 1 Introduction 1 1.1 Introduction to Frequency
More informationEnergy Efficient and High Speed Charge-Pump Phase Locked Loop
Energy Efficient and High Speed Charge-Pump Phase Locked Loop Sherin Mary Enosh M.Tech Student, Dept of Electronics and Communication, St. Joseph's College of Engineering and Technology, Palai, India.
More informationISSN:
507 CMOS Digital-Phase-Locked-Loop for 1 Gbit/s Clock Recovery Circuit KULDEEP THINGBAIJAM 1, CHIRAG SHARMA 2 1 Department of E&CE, Nitte Meenaskhi Institute of Technology, Yelahanka, Bangalore-560064,
More informationCHAPTER 6 DESIGN OF VOLTAGE CONTROLLED OSCILLATOR (VCO) USING 45 NM VLSI TECHNOLOGY
CHAPTER 6 DESIGN OF VOLTAGE CONTROLLED OSCILLATOR (VCO) USING 45 NM VLSI TECHNOLOGY Oscillators are required to generate the carrying signals for radio frequency transmission, but also for the main clocks
More informationA Low Noise, Voltage Control Ring Oscillator Based on Pass Transistor Delay Cell
A Low Noise, Voltage Control Ring Oscillator Based on Pass Transistor Delay Cell Devi Singh Baghel 1, R.C. Gurjar 2 M.Tech Student, Department of Electronics and Instrumentation, Shri G.S. Institute of
More informationDesign of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits Behzad Razavi Professor of Electrical Engineering University of California, Los Angeles H Boston Burr Ridge, IL Dubuque, IA Madison, WI New York San Francisco
More informationVLSI IMPLEMENTATION OF BACK PROPAGATED NEURAL NETWORK FOR SIGNAL PROCESSING
VLSI IMPLEMENTATION OF BACK PROPAGATED NEURAL NETWORK FOR SIGNAL PROCESSING DR. UJWALA A. KSHIRSAGAR (BELORKAR), MR. ASHISH E. BHANDE H.V.P.M. s College of Engineering & Technology, Amravati- 444 605 E-mail:ujwalabelorkar@rediffmail.com,
More informationEE2254 LINEAR INTEGRATED CIRCUITS UNIT-I IC FABRICATION
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING Question bank EE2254 LINEAR INTEGRATED CIRCUITS UNIT-I IC FABRICATION 1. Mention the advantages of integrated circuits. 2. Write down the various processes
More informationDESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERS
DESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERS Nilesh D. Patel 1, Gunjankumar R. Modi 2, Priyesh P. Gandhi 3, Amisha P. Naik 4 1 Research Scholar, Institute of Technology, Nirma University,
More informationDESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS
DESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS Aman Chaudhary, Md. Imtiyaz Chowdhary, Rajib Kar Department of Electronics and Communication Engg. National Institute of Technology,
More informationTHE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL
THE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL IN CMOS TECHNOLOGY L. Majer, M. Tomáška,V. Stopjaková, V. Nagy, and P. Malošek Department of Microelectronics, Slovak Technical University, Ilkovičova 3, Bratislava,
More informationDESIGN FOR LOW-POWER USING MULTI-PHASE AND MULTI- FREQUENCY CLOCKING
3 rd Int. Conf. CiiT, Molika, Dec.12-15, 2002 31 DESIGN FOR LOW-POWER USING MULTI-PHASE AND MULTI- FREQUENCY CLOCKING M. Stojčev, G. Jovanović Faculty of Electronic Engineering, University of Niš Beogradska
More informationFractional- N PLL with 90 Phase Shift Lock and Active Switched- Capacitor Loop Filter
J. Park, F. Maloberti: "Fractional-N PLL with 90 Phase Shift Lock and Active Switched-Capacitor Loop Filter"; Proc. of the IEEE Custom Integrated Circuits Conference, CICC 2005, San Josè, 21 September
More informationA CMOS Phase Locked Loop based PWM Generator using 90nm Technology Rajeev Pankaj Nelapati 1 B.K.Arun Teja 2 K.Sai Ravi Teja 3
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 06, 2015 ISSN (online): 2321-0613 A CMOS Phase Locked Loop based PWM Generator using 90nm Technology Rajeev Pankaj Nelapati
More informationDESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT
DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT PRADEEP G CHAGASHETTI Mr. H.V. RAVISH ARADHYA Department of E&C Department of E&C R.V.COLLEGE of ENGINEERING R.V.COLLEGE of ENGINEERING Bangalore
More informationVLSI Implementationn of Back Propagated Neural Network Signal Processing
IETE 46th Mid Term Symposium Impact of Technology on Skill Development MTS- 2015 VLSI Implementationn of Back Propagated Neural Network for Signal Processing Abstract - Mainly due to the rapid advances
More informationA CMOS UWB Transmitter for Intra/Inter-chip Wireless Communication
A CMOS UWB Transmitter for Intra/Inter-chip Wireless Communication Pran Kanai Saha, Nobuo Sasaki and Takamaro Kikkawa Research Center For Nanodevices and Systems, Hiroshima University 1-4-2 Kagamiyama,
More informationSAF ANALYSES OF ANALOG AND MIXED SIGNAL VLSI CIRCUIT: DIGITAL TO ANALOG CONVERTER
SAF ANALYSES OF ANALOG AND MIXED SIGNAL VLSI CIRCUIT: DIGITAL TO ANALOG CONVERTER ABSTRACT Vaishali Dhare 1 and Usha Mehta 2 1 Assistant Professor, Institute of Technology, Nirma University, Ahmedabad
More informationLINEAR IC APPLICATIONS
1 B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14 1 (a) Why is R e in an emitter-coupled differential amplifier replaced by a constant current source? (b)
More informationDesign of High Gain Two stage Op-Amp using 90nm Technology
Design of High Gain Two stage Op-Amp using 90nm Technology Shaik Aqeel 1, P. Krishna Deva 2, C. Mahesh Babu 3 and R.Ganesh 4 1 CVR College of Engineering/UG Student, Hyderabad, India 2 CVR College of Engineering/UG
More informationComparison between Analog and Digital Current To PWM Converter for Optical Readout Systems
Comparison between Analog and Digital Current To PWM Converter for Optical Readout Systems 1 Eun-Jung Yoon, 2 Kangyeob Park, 3* Won-Seok Oh 1, 2, 3 SoC Platform Research Center, Korea Electronics Technology
More informationYet, many signal processing systems require both digital and analog circuits. To enable
Introduction Field-Programmable Gate Arrays (FPGAs) have been a superb solution for rapid and reliable prototyping of digital logic systems at low cost for more than twenty years. Yet, many signal processing
More informationA CMOS CURRENT CONTROLLED RING OSCILLATOR WITH WIDE AND LINEAR TUNING RANGE
A CMOS CURRENT CONTROLLED RING OSCILLATOR WI WIDE AND LINEAR TUNING RANGE Abstract Ekachai Leelarasmee 1 1 Electrical Engineering Department, Chulalongkorn University, Bangkok 10330, Thailand Tel./Fax.
More informationAnalysis of Phase Noise Profile of a 1.1 GHz Phase-locked Loop
Analysis of Phase Noise Profile of a 1.1 GHz Phase-locked Loop J. Handique, Member, IAENG and T. Bezboruah, Member, IAENG 1 Abstract We analyzed the phase noise of a 1.1 GHz phaselocked loop system for
More informationDesign and Analysis of Current-to-Voltage and Voltage - to-current Converters using 0.35µm technology
Design and Analysis of Current-to-Voltage and Voltage - to-current Converters using 0.35µm technology Kopal Gupta 1, Prof. B. P Singh 2, Rockey Choudhary 3 1 M.Tech (VLSI Design ) at Mody Institute of
More informationLecture 1, Introduction and Background
EE 338L CMOS Analog Integrated Circuit Design Lecture 1, Introduction and Background With the advances of VLSI (very large scale integration) technology, digital signal processing is proliferating and
More informationECEN620: Network Theory Broadband Circuit Design Fall 2014
ECEN620: Network Theory Broadband Circuit Design Fall 2014 Lecture 16: CDRs Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Project descriptions are posted on the website Preliminary
More informationStudy and Implementation of Phase Frequency Detector and Frequency Divider 45nm using CMOS Technology
Study and Implementation of Phase Frequency Detector and Frequency Divider 45nm using CMOS Technology Dhaval Modi Electronics and Communication, L. D. College of Engineering, Ahmedabad, India Abstract--This
More informationHigh Temperature Mixed Signal Capabilities
High Temperature Mixed Signal Capabilities June 29, 2017 Product Overview Features o Up to 300 o C Operation o Will support most analog functions. o Easily combined with up to 30K digital gates. o 1.0u
More informationVLSI Chip Design Project TSEK06
VLSI Chip Design Project TSEK06 Project Description and Requirement Specification Version 1.1 Project: 100 MHz, 10 dbm direct VCO modulating FM transmitter Project number: 4 Project Group: Name Project
More informationDesign and Analysis of a Second Order Phase Locked Loops (PLLs)
Design and Analysis of a Second Order Phase Locked Loops (PLLs) DIARY R. SULAIMAN Engineering College - Electrical Engineering Department Salahaddin University-Hawler Zanco Street IRAQ Abstract: - This
More informationLow Power Wide Frequency Range Current Starved CMOS VCO in 180nm, 130nm and 90nm CMOS Technology
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 7, Issue 4 (May 2013), PP. 80-84 Low Power Wide Frequency Range Current Starved
More informationVCO Based Injection-Locked Clock Multiplier with a Continuous Frequency Tracking Loop
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 13, Issue 4, Ver. I (Jul.-Aug. 2018), PP 26-30 www.iosrjournals.org VCO Based Injection-Locked
More informationA 5.99 GHZ INDUCTOR-LESS CURRENT CONTROLLED OSCILLATOR FOR HIGH SPEED COMMUNICATIONS
A 5.99 GHZ INDUCTOR-LESS CURRENT CONTROLLED OSCILLATOR FOR HIGH SPEED COMMUNICATIONS Chakaravarty D Rajagopal 1, Prof Dr.Othman Sidek 2 1,2 University Of Science Malaysia, 14300 NibongTebal, Penang. Malaysia
More informationAvailable online at ScienceDirect. Procedia Computer Science 57 (2015 )
Available online at www.sciencedirect.com Scienceirect Procedia Computer Science 57 (2015 ) 1081 1087 3rd International Conference on ecent Trends in Computing 2015 (ICTC-2015) Analysis of Low Power and
More informationA Multiobjective Optimization based Fast and Robust Design Methodology for Low Power and Low Phase Noise Current Starved VCO Gaurav Sharma 1
IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 01, 2014 ISSN (online): 2321-0613 A Multiobjective Optimization based Fast and Robust Design Methodology for Low Power
More informationUltrahigh Speed Phase/Frequency Discriminator AD9901
a FEATURES Phase and Frequency Detection ECL/TTL/CMOS Compatible Linear Transfer Function No Dead Zone MIL-STD-883 Compliant Versions Available Ultrahigh Speed Phase/Frequency Discriminator AD9901 PHASE-LOCKED
More informationDesign of Low Power CMOS Startup Charge Pump Based on Body Biasing Technique
Design of Low Power CMOS Startup Charge Pump Based on Body Biasing Technique Juliet Abraham 1, Dr. B. Paulchamy 2 1 PG Scholar, Hindusthan institute of Technology, coimbtore-32, India 2 Professor and HOD,
More informationLSI and Circuit Technologies for the SX-8 Supercomputer
LSI and Circuit Technologies for the SX-8 Supercomputer By Jun INASAKA,* Toshio TANAHASHI,* Hideaki KOBAYASHI,* Toshihiro KATOH,* Mikihiro KAJITA* and Naoya NAKAYAMA This paper describes the LSI and circuit
More informationSudatta Mohanty, Madhusmita Panda, Dr Ashis kumar Mal
International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May-2014 45 Design and Performance Analysis of a Phase Locked Loop using Differential Voltage Controlled Oscillator Sudatta
More informationMixed Signal Virtual Components COLINE, a case study
Mixed Signal Virtual Components COLINE, a case study J.F. POLLET - DOLPHIN INTEGRATION Meylan - FRANCE http://www.dolphin.fr Overview of the presentation Introduction COLINE, an example of Mixed Signal
More informationDesign of a Frequency Synthesizer for WiMAX Applications
Design of a Frequency Synthesizer for WiMAX Applications Samarth S. Pai Department of Telecommunication R. V. College of Engineering Bangalore, India Abstract Implementation of frequency synthesizers based
More informationCMOS Instrumentation Amplifier with Offset Cancellation Circuitry for Biomedical Application
CMOS Instrumentation Amplifier with Offset Cancellation Circuitry for Biomedical Application Author Mohd-Yasin, Faisal, Yap, M., I Reaz, M. Published 2006 Conference Title 5th WSEAS Int. Conference on
More informationDESIGN OF A CURRENT STARVED RING OSCILLATOR FOR PHASE LOCKED LOOP (PLL)
DESIGN OF A CURRENT STARVED RING OSCILLATOR FOR PHASE LOCKED LOOP (PLL) 1 ZAINAB KAZEMI, 2 SAJJAD SHALIKAR, 3 A. M. BUHARI, 4 SEYED ABBAS MOUSAVI MALEKI 1 Department of Electrical, Electronic and System
More informationOn Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital VLSI
ELEN 689 606 Techniques for Layout Synthesis and Simulation in EDA Project Report On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital
More informationNEW WIRELESS applications are emerging where
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 4, APRIL 2004 709 A Multiply-by-3 Coupled-Ring Oscillator for Low-Power Frequency Synthesis Shwetabh Verma, Member, IEEE, Junfeng Xu, and Thomas H. Lee,
More informationBiCMOS Circuit Design
BiCMOS Circuit Design 1. Introduction to BiCMOS 2. Process, Device, and Modeling 3. BiCMOS Digital Circuit Design 4. BiCMOS Analog Circuit Design 5. BiCMOS Subsystems and Practical Considerations Tai-Haur
More informationUMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency
UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency Jamie E. Reinhold December 15, 2011 Abstract The design, simulation and layout of a UMAINE ECE Morse code Read Only Memory and transmitter
More informationA 45-nm SOI-CMOS Dual-PLL Processor Clock System for Multi-Protocol I/O
A 45-nm SOI-CMOS Dual-PLL Processor Clock System for Multi-Protocol I/O Dennis Fischette, Alvin Loke, Michael Oshima, Bruce Doyle, Roland Bakalski*, Richard DeSantis, Anand Thiruvengadam, Charles Wang,
More informationLow Power CMOS Digitally Controlled Oscillator Manoj Kumar #1, Sandeep K. Arya #2, Sujata Pandey* 3 and Timsi #4
Low CMOS Digitally Controlled Oscillator Manoj Kumar #1, Sandeep K. Arya #2, Sujata Pandey* 3 and Timsi #4 # Department of Electronics & Communication Engineering Guru Jambheshwar University of Science
More informationFig 1: The symbol for a comparator
INTRODUCTION A comparator is a device that compares two voltages or currents and switches its output to indicate which is larger. They are commonly used in devices such as They are commonly used in devices
More informationLow Jitter, Low Emission Timing Solutions For High Speed Digital Systems. A Design Methodology
Low Jitter, Low Emission Timing Solutions For High Speed Digital Systems A Design Methodology The Challenges of High Speed Digital Clock Design In high speed applications, the faster the signal moves through
More informationDESIGN OF CMOS BASED FM QUADRATURE DEMODULATOR USING 45NM TECHNOLOGY
DESIGN OF CMOS BASED FM QUADRATURE DEMODULATOR USING 45NM TECHNOLOGY 1 Pardeep Kumar, 2 Rekha Yadav, 1, 2 Electronics and Communication Engineering Department D.C.R.U.S.T. Murthal, 1, 2 Sonepat, 1, 2 Haryana,
More informationLecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1
Lecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1 LECTURE 160 CDR EXAMPLES INTRODUCTION Objective The objective of this presentation is: 1.) Show two examples of clock and data recovery
More informationDesigning of a 8-bits DAC in 0.35µm CMOS Technology For High Speed Communication Systems Application
Designing of a 8-bits DAC in 035µm CMOS Technology For High Speed Communication Systems Application Veronica Ernita Kristianti, Hamzah Afandi, Eri Prasetyo ibowo, Brahmantyo Heruseto and shinta Kisriani
More informationCMOS 120 GHz Phase-Locked Loops Based on Two Different VCO Topologies
JOURNAL OF ELECTROMAGNETIC ENGINEERING AND SCIENCE, VOL. 17, NO. 2, 98~104, APR. 2017 http://dx.doi.org/10.5515/jkiees.2017.17.2.98 ISSN 2234-8395 (Online) ISSN 2234-8409 (Print) CMOS 120 GHz Phase-Locked
More informationDelay-Locked Loop Using 4 Cell Delay Line with Extended Inverters
International Journal of Electronics and Electrical Engineering Vol. 2, No. 4, December, 2014 Delay-Locked Loop Using 4 Cell Delay Line with Extended Inverters Jefferson A. Hora, Vincent Alan Heramiz,
More informationA PROCESS AND TEMPERATURE COMPENSATED RING OSCILLATOR
A PROCESS AND TEMPERATURE COMPENSATED RING OSCILLATOR Yang-Shyung Shyu * and Jiin-Chuan Wu Dept. of Electronics Engineering, National Chiao-Tung University 1001 Ta-Hsueh Road, Hsin-Chu, 300, Taiwan * E-mail:
More informationExtreme Temperature Invariant Circuitry Through Adaptive DC Body Biasing
Extreme Temperature Invariant Circuitry Through Adaptive DC Body Biasing W. S. Pitts, V. S. Devasthali, J. Damiano, and P. D. Franzon North Carolina State University Raleigh, NC USA 7615 Email: wspitts@ncsu.edu,
More informationDesign of Single to Differential Amplifier using 180 nm CMOS Process
Design of Single to Differential Amplifier using 180 nm CMOS Process Bhoomi Patel 1, Amee Mankad 2 P.G. Student, Department of Electronics and Communication Engineering, Shantilal Shah Engineering College,
More informationDESIGNING A NEW RING OSCILLATOR FOR HIGH PERFORMANCE APPLICATIONS IN 65nm CMOS TECHNOLOGY
DESIGNING A NEW RING OSCILLATOR FOR HIGH PERFORMANCE APPLICATIONS IN 65nm CMOS TECHNOLOGY *Yusuf Jameh Bozorg and Mohammad Jafar Taghizadeh Marvast Department of Electrical Engineering, Mehriz Branch,
More informationCHAPTER 3. Instrumentation Amplifier (IA) Background. 3.1 Introduction. 3.2 Instrumentation Amplifier Architecture and Configurations
CHAPTER 3 Instrumentation Amplifier (IA) Background 3.1 Introduction The IAs are key circuits in many sensor readout systems where, there is a need to amplify small differential signals in the presence
More informationDesign and Performance Analysis of High Speed Low Power 1 bit Full Adder
Design and Performance Analysis of High Speed Low Power 1 bit Full Adder Gauri Chopra 1, Sweta Snehi 2 PG student [RNA], Dept. of MAE, IGDTUW, New Delhi, India 1 PG Student [VLSI], Dept. of ECE, IGDTUW,
More informationArea and Power Efficient Pass Transistor Based (PTL) Full Adder Design
This work by IJARBEST is licensed under Creative Commons Attribution 4.0 International License. Available at https://www.ijarbest.com Area and Power Efficient Pass Transistor Based (PTL) Full Adder Design
More informationQuestion Paper Code: 21398
Reg. No. : Question Paper Code: 21398 B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2013 Fourth Semester Electrical and Electronics Engineering EE2254 LINEAR INTEGRATED CIRCUITS AND APPLICATIONS (Regulation
More informationA CMOS Analog Front-End Circuit for MEMS Based Temperature Sensor
Technology Volume 1, Issue 2, October-December, 2013, pp. 01-06, IASTER 2013 www.iaster.com, Online: 2347-6109, Print: 2348-0017 A CMOS Analog Front-End Circuit for MEMS Based Temperature Sensor Bollam
More informationAbout the Tutorial. Audience. Prerequisites. Copyright & Disclaimer. Linear Integrated Circuits Applications
About the Tutorial Linear Integrated Circuits are solid state analog devices that can operate over a continuous range of input signals. Theoretically, they are characterized by an infinite number of operating
More informationA 6.0 GHZ ICCO (INDUCTOR-LESS CURRENT CONTROLLED OSCILLATOR) WITH LOW PHASE NOISE
International Journal of Electrical Engineering & Technology (IJEET) Volume 7, Issue 5, September October, 2016, pp.01 07, Article ID: IJEET_07_05_001 Available online at http://www.iaeme.com/ijeet/issues.asp?jtype=ijeet&vtype=7&itype=5
More informationDesign of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders
Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders B. Madhuri Dr.R. Prabhakar, M.Tech, Ph.D. bmadhusingh16@gmail.com rpr612@gmail.com M.Tech (VLSI&Embedded System Design) Vice
More informationRadio-Frequency Conversion and Synthesis (for a 115mW GPS Receiver)
Radio-Frequency Conversion and Synthesis (for a 115mW GPS Receiver) Arvin Shahani Stanford University Overview GPS Overview Frequency Conversion Frequency Synthesis Conclusion GPS Overview: Signal Structure
More informationECEN474/704: (Analog) VLSI Circuit Design Fall 2016
ECEN474/704: (Analog) VLSI Circuit Design Fall 2016 Lecture 1: Introduction Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Turn in your 0.18um NDA form by Thursday Sep 1 No
More informationA fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI
LETTER IEICE Electronics Express, Vol.1, No.15, 1 11 A fully synthesizable injection-locked PLL with feedback current output DAC in 8 nm FDSOI Dongsheng Yang a), Wei Deng, Aravind Tharayil Narayanan, Rui
More informationDESIGN OF CMOS BASED FM MODULATOR USING 90NM TECHNOLOGY ON CADENCE VIRTUOSO TOOL
DESIGN OF CMOS BASED FM MODULATOR USING 90NM TECHNOLOGY ON CADENCE VIRTUOSO TOOL 1 Parmjeet Singh, 2 Rekha Yadav, 1, 2 Electronics and Communication Engineering Department D.C.R.U.S.T. Murthal, 1, 2 Sonepat,
More information