Designing of a 8-bits DAC in 0.35µm CMOS Technology For High Speed Communication Systems Application

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1 Designing of a 8-bits DAC in 035µm CMOS Technology For High Speed Communication Systems Application Veronica Ernita Kristianti, Hamzah Afandi, Eri Prasetyo ibowo, Brahmantyo Heruseto and shinta Kisriani Electrical Engineering, Gunadarma University Abstract The design of an 8-bit DAC used in this research is used for high speed communication systems The main components used are the op-amp (operational amplifier), R-R Ladder, and the MOS switch The results of the design of op-amp characteristics meet of offset voltage, V offset = 0 V Research carried out by using the tools of Mentor Graphics software with AMS technology 035 µm CMOS process The design of the DAC in this research produces speeds up to 1000 Msps, these results suggest that the design meets the speed of high speed DAC categories ranging from Msps Measurements of integral and differential nonlinearities of the DAC design shows INL ± 1 LSB and DNL ± 1 LSB Later in this research, the design of an 8-bit DAC is applied in the form SOC (System on Chip) Keywords CMOS, DAC (Digital-to-Analog Converter), Operational Amplifier (Op-Amp), and MOS Switch I INTRODUCTION COmplementary metal-oxide-semiconductor (CMOS) is a technology for constructing integrated circuits CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits CMOS technology is also used for several analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication Frank anlass patented CMOS in 1967 (US patent 3,356,858)[1] In this research the CMOS technology is used for applications in the DAC (Digital-to-Analog Converter) CMOS design of the DAC in this research is used for high speed communication systems DAC on-chip high-speed high-resolution based on the same CMOS process as the digital circuits that are important for system applications such as Very high-data rate Digital Subscriber Line (VDSL), Direct Digital Synthesis (DDS), ireless Local Area Network (LAN), Quadrature Modulation (QAM), Direct Intermediate Frequency (IF), and Global mobile for mobile telecommunication (GSM), to achieve low power, small chip area, and high-speed performance [] Fig 1: High Speed DACs [3] Based on the above data, the design of the DAC (Digital to Analog Converter) can be said to be high speed if it have an update rate (Msps) between Msps DAC (Digital-to-Analog Converter) is a device to convert the input signal in digital form into an output signal in the analog form (voltage) The resulting DAC output voltage proportional with the digital value into the DAC Modifiers or conversion tool is needed as the interfacing between analog components with digital components Usually, the ADC (Analog-to-Digital Converter) there is a DAC block, where the ADC is a device to convert analog signals into digital signals Block DAC serves as feedback to correct errors and also to make the reference voltage during the conversion One of the circuits used is a switch capacitor circuit that has high speed and is able to filter out unwanted frequencies Fig : Diagram Block DAC This research has the following objectives are design and implement a circuit of components into an 8 bit DAC for high speed communication systems using CAD Mentor Graphics AMS (Austria Micro Systems) technology 035 µm CMOS process, and set up a 8-bit DAC design results in the form of

2 SOC (System on Chip) II RELATED ORK In electronics, a digital-to-analog converter (DAC or D-to- A) is a device that converts a digital (usually binary) code to an analog signal (current, voltage, or electric charge) An analogto-digital converter (ADC) performs the reverse operation Signals are easily stored and transmitted in digital form, but a DAC is needed for the signal to be recognized by human senses or other non-digital systems [4] The most common types of electronic DACs are: pulsewidth modulator, delta-sigma DAC, binary-weighted DAC, R- R ladder DAC, thermometer-coded DAC, and Hybrid DACs [4] A R-R Topologies for DACs The Current-Mode R-R DAC The R-R DAC can be classified into two categories: voltage-mode and current-mode A current-mode R-R DAC is shown in Fig 3 The branch currents flowing through the R resistors are of a binary-weighted relationship caused by the voltage division of the R-R ladder network and are diverted either to the inverting input of the op-amp (actually the feedback resistor) or the noninverting input of the op-amp (actually V REF )[5] Fig 4: Traditional voltage-mode R-R DAC [5] A ide-swing Current-Mode R-R DAC e ve shown that it is desirable to have a wide output swing, as is provided by the voltage-mode R-R DAC, while at the same time having a fixed input common mode voltage, as is provided by the current-mode R- R DAC Fig 5 shows a wide-swing current-mode R-R DAC configuration that has a rail-to-rail output swing while keeping the input common-mode voltage of the op-amp fixed at the common mode voltage, V CM, or (V REF + + V REF )/ [5] Fig 5: ide-swing current-mode R-R DAC [5] Fig 3: Traditional current-mode R-R DAC [5] The Voltage-Mode R-R DAC Fig 4 shows a schematic of a voltage-mode DAC The output of the N-bit voltage-mode DAC can be written as [5] Like traditional current-mode R-R DACs, the DAC scheme shown in Fig 5 operates on currents Using superposition and assuming V REF is the reference for calculations, the current flowing in the feedback resistor, R F, is given by (1) If the input code is all zeroes, with V REF = 0, V REF + = V DD, and the op-amp in the follower configuration, then V OUT = V REF If the input code is all ones, then the output of the DAC is V REF + 1 LSB () noting the inversion used in the control logic seen in Fig 5 The output voltage of the DAC is then given, assuming R = R F, by V OUT = V REF + V REF + V REF + I F R (3)

3 The matching between the resistors of the R-R ladder is one of the most important and limiting factors that determine the linearity (eg, DNL and INL) of the entire DAC It is helpful, when designing any type of resistor string DAC, if we can estimate the resistor matching requirements based on a desired resolution [5] B Operational Amplifier (Op-Amp) Operational Amplifier is the IC that generates the output voltage V o, which is the result of the strengthening of the difference in voltage at both inputs (V1 and V) [6] Figure 6 showing standard op-amp notation An op amp is a differential to single-ended amplifier It amplifies the voltage difference, V d = V p V n, on the input port and produces a voltage, V o, on the output port that is referenced to ground [7] Fig 7: A transistor modeled as a switch [8] Fig 8: Inverter Series of CMOS[9] III RESEARCH METHODS Fig 6: Standard Op Amp Notation [7] A DAC Design for High Speed Communication Systems Methods The basic form of an op-amp is a high gain dc-amplifier with a differential input port and a single output port A differential input has two terminals, which are both independent of ground or common The signal between these two terminals is the input signal, which will be amplified The terminals are called non-inverting input and inverting input [7] C The MOSFET as a Digital Switch A simple description treats the MOSFET transistor as a switch The gate terminal is analogous to the light switch on the wall hen the gate has a high voltage, the transistor closes like a wall switch, and the drain and source terminals are electrically connected Just as a light switch requires a certain force to activate, the transistor gate terminal needs a certain voltage level to switch and connect the drain and source terminals This voltage is called the transistor threshold voltage Vt and is a fixed voltage for nmos and for pmos devices in a given fabrication process [8] Each transistor works like switch, which its work system will be in closed condition or open condition On the figure 10, if input series is signed 0, so transistor type N is open condition and transistor type P is closed condition so VDD voltage will pass through that transistor type P and output is 1 On the other way, if input is signed 1, so transistor type P is open condition and transistor type N is closed condition So the voltage from ground will pass through transistor type N and the output series is 0 [9] Fig 9: Stages in DAC Research Design In the research of this DAC design for high speed communication systems, three phases of the design as shown in Fig 11 is being conducted The first stage is expected to resulted schematic design of the simulation with a prototype digital signal given in Once the schematic design is complete, the next phase of activity is the manufacture of layout The results of this stage of the design layout is a clear form which is a settlement in the previous stage, which can then be processed according to CMOS technology in this case 035 µm CMOS technology using a form of floor plan or SOC (System on Chip) which will then be applied in the fabrication process Fabrication stage is the stage of completion with carrying out orders to the manufacturer s chip CMOS chips based on the

4 results of the design layout and floor plan that has been made in the previous stage B Supporting Component DAC Design In designing DAC there are supporting components where the value of each component (in this case the value of each transistor) must be determined Those determination through manual calculation process, then adjusted at the time of simulation In the calculation process there are some parameters should be considered, and the accordance parameter with the AMS technology 035 µm CMOS process are as follows: Constants of MOS is variables (K n = 155 µa/v s/d 195 µa/v dan K p = 50 µa/v s/d 70 µa/v) Threshold voltage of MOS is also variables (V T Hn = 0,40V s/d 0,64V dan V T Hp = -0,53V s/d 0,77V) 1) Operational Amplifier Design (Op-Amp): Operational amplifiers (op-amp) in the DAC design consist of four parts; there are a constant current source, current mirror, differential amplifier, and output amplifier I D6 = 49846µA Differential Amplifier Previously, from the current mirror circuit I D7 that have been obtained in the calculation of 1847 µa, performed calculations to gained the value of V SG This step need to be done in order to obtain the value (/L) 1 4 The solutions are as follows: I D7 = K p w L = 548 L (V SG + V T Hp ) L 1, = 07µm ; 1, = 38µm L 3,4 = 035µm ; 3,4 = 8µm Output Amplifier Previously, the current mirror circuit i D6 that have been obtained in the calculation of µa, performed calculations to obtain the value of V SG This step need to be done in order to obtain the value (/L) 5 As follows is the solution: 49846µA = Kn w L (V SG + V T Hn ) L = 437 L 5 = 035µm; 5 = 15µm TABLE I: Results Changes Value of the /L at the Op-Amp Fig 10: Op-Amp circuit Constant Current Source ith the V DD value is 33 V and V SS value is -33 V From equation ı D on saturation state can be derived to calculate the V GS, there is: LID V GS = K n + V T Hn (4) V SG = V DD = V SG8 + V GS9 + V GS10 + V SS I D8 = 8448µA LI D K p + V T Hp (5) Current Mirror V GS voltage on the PMOS M 6 and M 7 are the same as the V GS voltage on the PMOS M 8 So the equations obtained are as follows: I D7 = 1847µA I D8 L 1 1 = I D7 L = I D6 L 3 3 (6) Description First Simulation Second Simulation M 1 38/07 40/07 M 38/07 40/07 M 3 8/035 0/035 M 4 8/035 0/035 M 5 15/035 85/035 M 6 9/035 95/035 M 7 109/ /035 M 8 5/035 5/035 M 9 11/035 11/035 M 10 11/035 11/035 ) MOS Switch Design: As follows are the calculations to determine the value of and L in each transistor: PMOS I D = K p L (V M + V T Hp ) L p = 035µm ; p = 13µm NMOS I D = K n L (V M + V T Hn ) L p = 035µm ; p = 05µm 3) R-R Ladder DAC Design: Another supporting component after the op-amp is a component of the R-R Ladder DAC In this research, word of bits used is 8 bits, so it is the required resistor 16 as much as units consist of 7 unit of resistor R and 9 unit of resistor R

5 Each resistor then converted into a transistor, by using the equation as follows: R n = V DD K n L (V DD V T Hn ) (7) If R = 10 KΩ, then L = 035 µm, = 17 µm If R = 0 KΩ, then L = 035 µm, = 08 µm The resistors on R-R Ladder then modified by using transistors Fig 1: Simulation Results of Offset Voltage Simulations were also performed for AC voltage by using a 10 MHz input frequency to find a large open loop gain (AOL), phase margin (PM), and frequency of unity (GB) Fig 11: R-R Ladder DAC Circuit (Transistor) Fig 13: Simulation Results of Amplification AoL, GB, and PM Op-Amp IV TESTING AND RESULTS As seen in Fig 14, which indicates that the line V P OS (Positive Voltage) as the input voltage and a line indicating the output voltage V OUT meet at one point on the voltage of 0 volts This shows that the simulated op-amp to reach the offset voltage as one of the characteristics of the op-amp (V offset = 0 volts) is obtain Evidenced by doing magnification of up to two to three times, the second voltage V OUT and V P OS still pass voltage 0 volts TABLE II: Simulation Result of Amplification AoL, GB, dan PM Op-Amp AoL GB PM 639 db 1677 MHz In this simulation stage, the circuit has been in combination with an op-amp and MOS circuit switches By providing varying values (0 and 1) at the input digital data, and reference voltage (V REF = 15 Volt)

6 TABLE IV: Results of 8-bit DAC Design Parameter 8-bit DAC [Results of Design] Resolution 8 bit Rate 1000 Msps CMOS Process 035 µm 33 V INL ± 1 DNL ± 1 Fig 14: Simulation Results of 8-bit DAC The layout results of the DAC schematic circuit as shown in figure 18 Fig 15: Simulation Results of 8-bit DAC (continue) Fig 16: Layout 8 bit DAC TABLE III: The Value of Analog Voltage with V REF 15 V Based on The Simulation D7 D6 D5 D4 D3 D D1 D0 V OUT In this research the total component of the CMOS transistors used is 4 pieces and one capacitor to the op-amp, using a layout area width of 1 µm x 96 µm = 116 µm From design layout and specifications that have been generated, then the fabrication process can be done This layout can be made into a single chip or grown in an apparatus (Embedded System) as required In this research the layout is includes a chip (System on Chip) that is connected to the pins according to the function of each pin as shown in Fig 19 Fig 17: System on Chip The design of 8-bit DAC in this research produces speeds up to 1000 Msps, which is based on the category of high speed DAC, the design of 8-bit DAC is included into the category high speed, so it can be used for the communication system V CONCLUSION This research discusses the design of the Digital to Analog Converter (DAC) which was applied to the SOC (System on Chip) for high speed communication systems DAC circuit consist of MOS switches, the R-R Ladder, and the Op- Amp Then the design is simulated using Mentor Graphics

7 software technology AMS 035 µm CMOS Process From the simulation results obtained can be summarized as follows: 1) Op-Amp design at DAC circuit in this research produces a precision offset voltage Generate an open loop gain (AOL) of 639 db, phase margin (PM) 677 degrees, and GB at 1677 MHz The data obtained have met the objectives of this research ) Circuit design switches are used in order to DAC circuit be able to produce a residual voltage of the linear feedback from the conversion of digital data 3) R-R Ladder circuit design main components being used is resistor In designing a layout the size of the resistor layout is very large and less efficient Because of that we need a replacement component that is more efficient but still have the same quality In this research, a resistor circuit at the DAC can be replaced with NMOS transistors And then after being simulated, the results obtained do not have any different with the output at the time of the DAC circuit using a resistor This is very advantageous especially from the standpoint of industry because it can save production costs 4) The design of DAC in this research included into the category of high speed because the speed gained from the research is 1000 Msps These results meet the specifications of high speed DAC as described in figure 1 5) The results of the circuit layout design 8-bit DAC and the floor plan in the form of SOC (System on Chip) is ready for fabrication REFERENCES [1] ikipedia, Cmos, access on November 010 [] J-S Y S-H L M-Jung Kim, H-Hee Bae, A 3 v 1b 100 ms/s cmos d/a converter for high-speed communication systems, Semiconductor Technology and Science, vol 3, pp 11 16, December 003 [3] Maxim, High-Speed ADCs, DACs, and AFEs Maxim Integrated Products, Inc, September 008 [4] ikipedia, Digital-to-analog converter, access on October 011 [5] R J Baker, CMOS Circuit Design, Layout, and Simulation, Third Edition iley, 010 [6] Anonim, Introduksi operational amplifier, BAGIAN+1_Opamppdf, access on October 011 [7] J Karki, Digital video broadcasting, hite Paper: SLOA011, April 1998 [8] C Hawkins and J Segura, Introduction to Digital Electronics Semi, 005 [9] E P ibowo and N Huda, Desain Skematik, Layout, dan Simulasi dengan Menggunakan Perangkat Lunak Mentor Graphics Depok: Gunadarma University, March 007

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