INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY

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1 INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY A PATH FOR HORIZING YOUR INNOVATIVE WORK DESIGN OF PD AND HIGH PERFORMANCE VCO FOR PLL WITH 45 nm CMOS TECHNOLOGY VAISHALI V.BHIMTE 1,VAISHALI PANDE 1 Faculty in Department of Electronics Engineering, Kavi Kulguru Institute of Technology and Science, Ramtek, Dist: Nagpur. Accepted Date: 27/02/2013 Publish Date: 01/04/2013 Keywords PD, Loop Filter, VCO, 45nm CMOS Technology Corresponding Author Ms. Vaishali V.Bhimte Abstract This paper describes design aspects for low power and high performance phase locked loop using 45nm process technology. The paper contains cmos design of PFD, charge pump and loop filter, VCO. The design is simulated with 45nm CMOS technology. The Software microwind 3.1 used allows us to design and simulate an integrated circuit at physical description level. The main novelty related to the 45nm technology such as the high-k gate oxide, metal-gate and very low-k interconnect dielectric described.

2 I. INTRODUCTION The electronics industry has achieved a phenomenal growth over the last two decades, mainly due to the rapid advances in integration technologies, large-scale systems design - in short, due to the advent of VLSI. The number of applications of integrated circuits in high-performance computing telecommunications, and consumer electronics has been rising steadily, and at a very fast pace. Typically, the required computational power of these applications is the driving force for the fast development of this field. Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core of a microprocessor, which includes the largest power density on the microprocessor. In an effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. Lowering the supply voltage, however, also reduces the performance of the circuit, which is usually unacceptable. 1. Low Power For low power, low leakage transistors will be used and a little variation in frequency will be compromise on. Also there will be a shutdown input in proposed circuit which will be the PLL to hold or there can be a pin, which if enabled then will make the PLL frequency to half. 2. Advanced VCO The VCO is the most important functional unit in the PLL. Its output frequency determines the effectiveness of PLL. In addition to operating at highest frequency this unit consumes the most of the power in the system. Obviously this unit is a particular focus to reduce power consumption. Its objective of this work to demonstrate that gigahertz frequency range and mill watt power consumption of a monolithic CMOS VCO with good phase

3 noise performance can be achieved. consumption is also a limiting factor in VLSI integration for portable applications. II. SIMULATION SETUP This paper describes the improvement related to the CMOS 45nm technology and the implementation of this technology in Microwind 3.1. For technology mode 45nm, Fig.1 Basic block diagram of PLL PLLs are widely used in communication application such as frequency synthesis for missile tracking; noise stability is an important factor which can be analyzed. Fig.2 PLL used to accelerate clock signals Integrated phase-locked loops (PLL's) play the versatile roles in the applications of clock generator, time synchronization and clock multiplication. A typical Phase Lock Loop architecture consists of a phase frequency detector (PFD), a charge pump, a loop filter, a voltage-controlled oscillator (VCO) and a frequency divider. Power effective gate length is 25nm with metal gate and SiON gate dielectric. There may exist several variants of the 45-nm process technology. One corresponds to the highest possible speed, at the price of a very high leakage current. This technology is called High speed as it is dedicated to applications for which the highest speed is required. III. XOR PHASE DETECTOR The XOR phase detector is the simplest phase detector. The XOR is useful as a phase detector since the time when the two inputs are different (or same) represents the relative phase. The output of the XOR is low pass filtered and acts as a control voltage to the VCO. The output (low pass filtered) as a function of the phase error is also shown

4 Charge pump sources current if output frequency/phase is too slow. Charge pump sinks current if output frequency/phase is too high. It is primarily used to copy currents. The VCO is commonly used for Fig.3 xor as a phase detector For this detector any deviation in a positive or negative direction from the the perfect in-phase condition (i.e., phase error of zero) produces the same change in duty factor resulting in the same average voltage. Thus the linear phase range is only 180 degrees. Using such a phase detector, a PLL will lock to a quadrature phase relationship (i.e., ¼ cycle offset) between the two inputs. A drawback of the XOR phase detector is that it may lock to a multiple of the clock frequency. If the local clock is a multiple of the reference clock frequency, the output of the phase detector will still be a square wave of 50% duty cycle, albeit at a different frequency. The filtered version of this signal will be identical to that of the truly locked state and thus the VCO will operate at the nominal frequency. clock generation in phase lock loop circuits. The clock may vary typically by +/- 50 percent of its central frequency for which current mirror/current started circuits will be used. Besides this charge pump circuits will also be used to convert digital error pulse to analog error current. Fig.4 design of PD with RC filter IV.CHARGE PUMP AND LOOP FILTER:-

5 number of inverters. Fig.6 A ring oscillator based on an odd Fig.5 Simulation of PD with RC filter V. VCO 1. Ring Oscillator The role of oscillators is to create a periodic logic or analog signal with a stable and predictable frequency. Oscillators are required to generate the carrying signals for radio frequency transmission, but also the main clocks of processors. The ring oscillator is a very simple oscillator circuit, based on the switching delay existing between the input and output of an inverter. The usual implementation consists in a series of five up to one hundred chained inverters. Usually, one inverter in the chain is replaced by a NAND gate to enable the oscillation. Fallowing fig.6 shows a ring oscillator based on an odd number of inverters The main problem of this type of oscillators is the very strong dependence of the output frequency on virtually all process parameters and operating conditions. As an example, the power supply voltage VDD has a very significant importance on the oscillating frequency. 2. Advanced VCO The VCO is the most important functional unit in the PLL Its output frequency determines the effectiveness of PLL. In addition to operating at highest frequency this unit consumes most of the power in the system. The voltage controlled oscillator (VCO) generates a clock with a controllable frequency. The VCO is commonly used for clock generation in phase lock loop circuits. The clock may vary typically by +/-50% of its central frequency. The current starved

6 inverter chain uses a voltage control to modify the current that flows in the N1, P1 branch. The current through N1 is mirrored by N2, N3 and N4. The same current flows in P1. The current through P1 is mirrored by P2, P2 and P4. Consequently, the change in Vcontrol induces a global change in the inverter currents, and acts directly on the delay. VI. RESULT Figure 8. Shows the VCO using 45nm technology. This VCO is designed with microwind 3.1 software using 45 nm design rule. This VCO is designed for high GHz frequency. Fig.8 design of VCO ig.7 Schematic diagram of a voltage controlled oscillator F The simulation of a high performance VCO is shown in following figure 9. A higher odd number of stages are commonly implemented, depending on the target oscillating frequency and consumption constraints. Then, if the phase from the oscillator falls behind that of the reference, the phase detector causes the charge pump to change the control voltage, so that the oscillator speeds up. Fig.9 simulation of VCO (voltage verses time)

7 VII.CONCLUSION Phase detector, charge pump, loop filter and VCO is designed. The layout which is developed by us is for a modified design of high performance VCO. The design is simulated with 45 nm CMOS technology and implemented in microwind 3.1. Future work will concern the 32 nm technology node, under preparation for an industrial production, which could include double gate MOS devices. REFERENCES 1. Ms. Ujwala A. Belorkar, Dr. S.A.Ladhake, Design of low power phase locked loop ( PLL) using 45nm VLSI Technology, International journal of VLSI design & Communication Systems ( VLSICS ), Vol.1, No.2, June K.Rajasekhar, S.Adilakshmi, T.B.K. Manoj kumar, Design of High Performance Phase Locked loop for Multiple outputs with Ultra Low Power Sub Threshold Logic, International Journal of Engineering Research and Applications (IJERA) ISSN: Vol. 2, Issue 2,Mar-Apr 2012, pp Haripriya janardhan, MSEE Mahmud Fawzy Wagdy, Design of a 1GHz Digital PLL Using0.18μm CMOS Technology, IEEE International conference H.O. Johansson, A Simple precharged CMOS Phase Frequency Detector, IEEE Journal of Solid State Circuits, Volume 33, no 2, pp , Feb Recardo Gonzalex, Supply and threshold voltage scaling for low power CMOS IEEE journal Of solid state circuits Vol. 32,No. 8 April Digest of Technical Fernando Rangel De Sousa, A reconfigurable high frequency phase-locked loop IEEE trans actions on instrumentation & measurement Vol. 53 No. 4 Aug Papers, Symposium on VLSI Technology, June 2004 pp Navid Azizi, Student Member, IEEE, Muhammad M. Khellah, Member, IEEE, Vivek K. De,Senior Member, IEEE, and Farid N. Najm, Fellow, IEEE, Variations-Aware Low-Power Design And Block Clustering With Voltage Scaling, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Vol. 15 No.7, July 2007

8 8. S. Borkar, T. Karnik, S. Narendra, T. Tschanz, A. Keshavarzi, and V. De, Parameter variaoons and impact on circuits and microarchitecture, in Proc. Design Autom. Conf., 2003, pp Vincent R. von Kaenel, Member, IEEE: A High-Speed, Low-Power Clock Generator for a Microprocessor Application IEEE Journal of solid-state circuits, VOL. 33, NO. 11, NOVEMBER 1998