Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash Adc

Transcription

1 IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: ,p- ISSN: Volume 12, Issue 2, Ver. II (Mar.-Apr. 2017), PP Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash Adc M.Kiranmai 1,V.Y.S.S.Sudir patnaikuni 2, K.Mouli 3, B.Manikanta sai 4, V.Nancharaiah 5. 1 student, Dept of ECE, Lendi institute of engineering and technology, jntuk, India. 2 Assistant Professor, Dept of ECE, Lendi institute of engineering and technology, jntuk, India. 3 student, Dept of ECE, Lendi institute of engineering and technology, jntuk, India. 4 student, Dept of ECE, Lendi institute of engineering and technology, jntuk, India. 5 Associate professor, Dept of ECE, Lendi institute of engineering and technology, jntuk, India. Abstract: The present investigation proposed a low power encoding scheme of thermometer code to binary code converter for flash analog to digital conversion by the design of different circuits. In this paper, we have proposed three encoding techniques for the conversion of analog to digital signal using Multiplexer based encoder, heterogeneous encoder and encoding technique using dynamic logic circuits providing low power of operation and we compare the results obtained from each technique based on power consumption. The multiplexer based encoder was designed with the help of multiplexers which consumes less amount of power comparing with other designs. Keywords: Analog to digital converter, Multiplexer based encoder, TIQ comparator, Heterogeneous encoder, Dynamic logic. I. Introduction The flash ADC is a fastest speed compared to other ADC architectures. Therefore, it is mainly used for high speed and large bandwidth applications such as radar processing, digital oscilloscopes and so on. The flash ADC is also known as parallel ADC because of its parallel architecture. Analog to Digital Converter (ADC) plays an important role in digital signal processing systems. The main challenges of designing ADC for system on chip applications are high speed, low voltage, and low power consumption. Reducing the power consumption is a major concern in a portable device. Low power techniques are applied to prolong the battery life of a system. Similarly ADCs also require a low power technique in the design to reduce the total power consumption of ADC.Speed, power dissipation and resolution are the three crucial parameters the design of any ADC which cannot be changed once the design is complete. In wireless and mobile communication applications require a high speed ADC with low resolution. In these applications, flash ADC is the most suitable ADC because of its parallel operation. The complete conversion is done in a single cycle with the help of a large number of comparators. The below figure illustrates the structural design of a typical flash ADC. This architecture requires 2 n -1 comparators for the operation. For example if the circuit requires five bit as output then the number of comparators to be used was 31 as per calculation. The exponential increase of the number of comparators in flash ADC leads to a large die size as well as large power consumption in a chip. The reference voltage of each comparator is provided by an external reference source. The reference voltages are equally spaced between largest reference voltage and the smallest reference voltage. A common analog input is given to each and every individual comparator which are used in flash ADC. Since all the comparators are functioning in parallel way, the output is produced in a single cycle. The digital outputs which are obtained in a specific manner from the comparators are called thermocode and further there will be a encoder for converting the resulting thermocode to binary code. Here, in this paper the encoders designed for the conversion are multiplexer based encoder, heterogeneous encoder and dynamic logic using full adders. DOI: / Page

2 The proposed encoder dynamic logic utilizes the properties of logic style implementation and Wallace tree implementation. In order to reduce the power dissipation the logic implementation is done with the use of dynamic logic. To make the code as more resilient i.e., lack of errors last stage was implemented using Wallace tree encoder. The present investigation was described as follows. The designing of three encoders explains in section 2. The method of implementation is described in the section3. Succeeding results, comparison and conclusion are provided. II. Design Analysis Of The Propoed Encoders The conversion from output of a comparator thermometer code to binary code is one of the bottlenecks in flash ADC. The bubble error usually results from timing differences between clock and signal lines and it is a situation where 1 is found above zero in thermometer code. The binary output totally depends on the output of a comparator based on number of 1 s.if the number of 1 s at the output was n then the binary output code was n. While designing thermometer code to binary code conversion two parameters are taken into consideration is error handling capability and power dissipation. Offset voltage in the comparator creates a bubble error in the thermometer code. Generally two methods are introduced to reduce the bubble errors. The first method is to convert thermometer code to gray code and then convert to binary code. But the accuracy of gray code steadily decreases as more number of comparators are used and more number of bubble errors is present in the thermometer code. The second method is the usage of Wallace tree encoder for the implementation using full adders for dynamic logic. This technique offers high robustness to bubble error and stuck at fault error because of its inherent global error correction or suppression capability. The disadvantage of this method is to provide a large delay of the encoder. In the first stage, conversion of thermometer code into two different four bit binary codes is done. With the help of four full adders and two different four bit binary codes, the final binary code was designed. The design equations which relates the thermometer code and binary code is presented and truth table is also shown below. MUX and heterogeneous encoders was designed with the help of full adders and multiplexers where the binary output depends on the ONEs obtained from the comparators as described below. DESIGN EQUATIONS: DOI: / Page

3 Table- Thermometer to binary code converter. 2.1 TIQ COMPARATOR In N bit Flash ADC 2 N -1 comparator is employed to compare the reference voltage with the input voltage to induce the thermometer code. Generally, resistor ladder is employed to generate reference voltage. This design is complex and additionally consumes more power and area. So in this paper we have proposed a comparator based on Threshold Inverter Quantization(TIQ) technique which is alternative approach to reduce the power consumption and chip area, it is basic CMOS inverter consists of one PMOS and one NMOS transistor with the switching threshold voltage.tiq comparator made up of two cascade CMOS inverter where the first inverter is used to set the reference voltage of comparator by varying the parameters like width and length of PMOS and NMOS transistors where as the second inverter increases the voltage gain and manage linearity balance for the voltage rising and falling intervals of high frequencies input signals. Fig:TIQ comparator MULTIPLEXER ENCODING TECHNIQUE MUX based encoders operates at high speed and covers the small chip area compared to the dynamic logic encoding technique. This encoder is implemented by grouping the results of smaller length MUX based encoder to develop a high bit resolution encoder to convert thermometer code into binary output. It gives better result than previous encoders in terms of power consumption, speed and space. DOI: / Page

4 2.1.2 HETEROGENEOUS ENCODER Heterogeneous encoder can be implemented by using any one of the existing encoders like Wallace tree encoder and multiplexer based encoder. This encoder was designed using full adders and multiplexers as shown below. In this selection signal is used from MUX which is critical. This can tolerant the bubble error and remaining signal can be used as inputs. Wallace encoder is also free from bubble error but the circuit is complex in nature. Hence, this encoder is designed which is easy to implement and also consumes less power. III. Implementation Of Proposed Encoders In order to convert the thermometer code to binary code different methods are implemented based on design equations. Pseudo NMOS, static CMOS and dynamic logic are the methods implemented for the conversion. One of the proposed encoding technique was dynamic logic as it overcome the disadvantages of other two methods. Since the power dissipation, consumption and number of transistors used was high for those two methods. Based on this intention, we proposed an encoding technique by dynamic logic providing low power consumption and medium speed of operation. The operation of dynamic logic evaluates in two phases namely precharge and evaluation. During precharging phase, when CLK=0, the output mode is fully charged to supply voltage vdd irrespective of pull down network through pull up transistor. At this time, the pull down path is disconnected as CLK is connected directly to NMOS transistor. The next phase is evaluation is done when CLK=1. In this case the pull up transistor is disconnected from the circuit and pull down path is discharged conditionally based on different inputs given to the circuit. The main thing to be concerned was during evaluation phase, the input to the gate has to make atmost one transition. The schematic implementation of dynamic logic, MUX based encoders and heterogeneous encoder are shown below. DOI: / Page

5 3.1 PROPOSED ENCODING TECHNIQUE USING DYNAMIC LOGIC IMPLEMENTATION OF b IMPLEMENTATION OF b2 DOI: / Page

6 3.1.3 IMPLEMENTATION OF b1 Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash Adc IMPLEMENTATION OF b0 3.2 MULTIPLEXER BASED ENCODER The operation of multiplexer based encoder is as follows. The input signal is given to the TIQ comparator as a sinusoidal and it compares it with the threshold voltage generated by the first cmos invereter of comparator and generates the output signal as binary generating a thermometer code from all comparators. The output of each comparator is given to multiplexers in which each cell counts number of logical ONEs at each entries performing operation and generates a final binary output. DOI: / Page

7 3.2.1 IMPLEMENTATION OF CMOS FULL ADDER We have designed a CMOS full adder which consists of 28 transistors which consumes less amount of power and the design equation is as follows 3.3 HETEROGENEOUS BASED ENCODER IV. Simulation Results The proposed encoders which are designed had been tested for every inputs given in the truth table and results were verified. Three types of encoders used in this paper were compared based on the results obtained from power analysis. The MUX based encoder consumes less power for operation comparing with dynamic logic and heterogeneous encoders as shown in the table. The reconfigurable capability of the proposed encoders makes the design adaptable to reconfigurable flash ADC architecture. DOI: / Page

8 4.1 SIMULATED OUTPUT Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash Adc 4.2 COMPARISON TABLE: Results Dynamic logic Heterogenous encoder MUX based encoder Architecture Flash Flash Flash Resolution 5 bits 4 bits 4 bits Vdd 5 V 5 V 5 V Power mw 1.08mW mW consumption V. Conclusion Now a days the growth of portable device and battery operated like cell phone, laptops has increased. Hence the device should be designed which consumes less power and have minimal area and device can be operated for long time. TIQ removes the array of resistors that makes the ADC devices to operate faster and takes less area. Hence we have designed three encoding techniques in which a MUX based encoder for the binary conversion which consumes less amount of power compared to the other techniques based on above results References [1]. D.Lee, J.Yoo, K.Choi and J. Ghaznavi, Fat-tree encoder design for ultrahigh speed flash analog to digital converters I proc. IEEE Mid-west Symp. Circuits Syst, pp , Aug [2]. S. Sheikhaei, S. Mirabbasi, A. Ivanov, An Encoder for a 5GS/s 4bit flash A/D converter in 0.18um CMOS,Canadian Conference on Electrical and Computer Engineering, pp , May [3]. [Jan M Rabaey, Anantha Chandra kasan, Borivoje Nikolic, Digital Integrated Circuits, a design perspective, second edition, Prentice Hall [4]. Vudadha, Chetan, et al. Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. 25 th IEEE International conference on VLSI Design, pp , Jan [5]. Sail, E.; Vesterbacka, M, A multiplexer based decoder for flash analog to- digital converters, IEEE region 10 conference, TENCON 2004, pp , Nov [6]. Sall, Erik, Mark Vesterbacka, and K.Ola Andersson. A study of digital decoders in flash analog-to-digital converters, Proc. of International symposium on Circuits and systems, pp , May [7]. Gupta, Yogendra, et al. Design of low power and high speed multiplexer based Thermometer to Gray Encoder,IEEE International Symposium on Intelligent Signal Processing and Communications Systems, pp , Nov DOI: / Page