Static and dynamic parameter estimation of Threshold Inverter Quantizer based flash ADC

Transcription

1 Volume 118 No , ISSN: (printed version); ISSN: (on-line version) url: ijpam.eu Static and dynamic parameter estimation of Threshold Inverter Quantizer based flash ADC Vishal Moyal 1 and Dr Neeta Tripathi 2 1 Department of Electronics & Telecommunication, Shri Shankaracharya Technical Campus, Bhilai, India vishalmoyal@gmail.com 2 Principal, Shri Shankaracharya Engineering College, Bhilai, India neeta31dec@rediffmail.com January 15, 2018 Abstract The put forward work in this paper anticipates to estimate the static and dynamic parameters of a 3-bit Flash Analog to Digital Converter (FADC) realized using Threshold Inverter Quantizer (TIQ) technique with Diode Free Adiabatic Logic (DFAL) based Inverter. The TIQ based FADC also requires 2n-1 comparators like conventional ADCs. Though, respective comparator in the TIQ flash ADC has different sizes to deliver internal reference voltages, which is achieved by methodically varying widths of PMOS and NMOS transistors of TIQ inverter. The design consumes 553 nw, which is 65.86% less than that of the power consumed by FADC based on CMOS TIQ. The static and dynamic parameter are evaluated for the implemented design and obtained result as follows DNL = LSB /-0.61 LSB, INL = LSB / LSB, SNR= db, SNDR 1 695

2 = db, SFDR = db and ENOB = 2.7 bits. Key Words : FADC, TIQ, DFAL, FFT, INL, DNL. 1 INTRODUCTION In the real world, most data are available as analog signals, in order to handle the data by modern handheld digitized devices like mobile phones, cameras, and devices used in bio medical etc. prerequisite to convert the analog signals to the digital signals. In these type of devices Analog to Digital Converters (ADCs) are castoff as a fundamental part of the system, instead of a detached circuit which is required to curtail the power dissipation in the organization [1-3]. ADCs are broadly subdivided as Flash type, Pipelined, Sigma- Delta, Dual Slope, and Successive Approximation ADC; amongst these categories Flash ADC is utilized for the high-speed application in low resolution, but its accuracy is principally restricted by the offsets of preamplifiers and comparators which contribute to the un-deterministic random offsets making it difficult to resolve. [4-6]. For power reduction and speed enhancement of ADCs various techniques of designing of comparator are suggested such as auto zeroed sequentially sampled type, dynamic comparator, differential amplifier latch, and threshold inverter quantizer based comparator [3-10]. In this work it is anticipated to estimate static and dynamic parameters of a Flash type ADC simulated using DFAL CMOS Inverter based Threshold Inverter Quantizer (TIQ) comparator as an alternative for conventional CMOS inverter TIQ to reduce the power dissipation [9-10]. TSMC 65nm technology is used on Cadence Virtuoso 6.16 for parameter estimation. 2 ARCHITECTURE FOR FLASH ADC Comprehensive architectural view of Flash ADC architecture is as presented in Fig. 1 which mainly involves of two sections, first is Comparator section and second is Code Converter section; if 2 696

3 Sample and Hold (S/H) is excluded. This architecture is simple and most suited for System on Chip (SoC) implementation. Figure 1: Generalised architecture of Flash ADC In the work presented in this paper the comparator section of ADC comprises of DFAL based TIQ which consumes less power over conventional CMOS TIQ comparator [10]. Output of comparator section is obtainable at the input of thermometric code format and is essential to be converted in binary code, to meet this requirement a Code Converter Section is employed; at the output of which digital code is available after conversion [11-13]. 3 DESIGN OF ADC The proposed ADC argued in this work is designed for a 3-bit resolution to achieve this following mathematical relationship is used for calculation purpose. Number of Comparator required = 2n 1 (1) Where n = Number of bits in the ADC design. Comparators are cautiously sized to have a step size of V, which is calculated from the full-scale range of analog voltage. This calculated step size is referred as 1 LSB for further calculation. The analog input signal is made functional to array of comparators implemented using DFAL inverter based TIQ technique tailed by the alike gain booster section to bid full voltage swing [5]. A. TIQ Comparator Define abbreviations and acronyms the first time they are used in the most critical segment in the Flash ADC architecture is a comparator. Its role is to convert analog input voltage into logic

4 or logic 0 by comparing it with the reference voltage. Architecture of flash type converter can be deployed using different comparators such as auto zeroed sequentially sampled type, dynamic comparator, differential amplifier latch, and threshold inverter quantizer based comparator [3-10]. The quantization of analog input is done by using comparator with selection of desired threshold voltage (Vth) of the inverter as and is coarsely given by the following mathematical relations [6]. V th = Vtp +Vtn (Kn/K p) 1+ K n/k p (2) K n = (W/L) n µ n Cox (3) K p = (W/L) p µ p Cox (4) Where V tp and V tn represent threshold voltages of PMOS and NMOS and µ p and µ n is the mobility of PMOS and NMOS correspondingly. Using these mathematical relations given in Eq 2 and step size of the full swing voltage (LSB), the reference voltages for each stage of comparator are determined for calculating the width (W) of PMOS and NMOS transistors of TIQ comparator, which is represented in TABLE I. TABLE I. WIDTH CALCULATION OF PMOS AND NMOS To obtain diverse levels in the quantizer the (W/L)n ratio of PMOS is kept at minimum value as per the design library, and the channel widths of the PMOS transistors are speckled to minimize the flow of current during metastable region i.e. Voltage Transfer 4 698

5 Curve (VTC), steps are repetitive carried out in the NMOS channel width calculation as well [5]. DC sweep simulation is done over a full-scale range of input voltage and obtained variation of reference voltage as a function of variation in the W/L ratio of MOS transistors, as depicted in Fig 2. Figure 2: Voltage transfer characteristics of DFAL TIQ comparator Considering the parameters calculated in Table I, the TIQ comparator was implemented using conventional CMOS inverter as well as DFAL CMOS inverter. Both TIQ comparators were simulated for the input frequencies ranging from 1 Hz to 1 MHz and the average dissipated power observed as 1.62 µw for conventional CMOS design and 553 nw for proposed design, which is about 65.86% lesser. B. Code converter Output of this comparator section is connected to the thermometric code format as tabulated in Table II. Here thermometric code is represented by bits Y6 Y0 and Binary Code is by B2 B0. From Table II, it is detected that B2=Y3. When Y3=0 then B1=Y1 and when Y3=1 then B1=Y5; by perceiving such relations, which are equivalent to the basic design equation of 2:1 multiplexer (MUX) the code converter stage is realized by using interconnected multiplexers as publicized in Fig. 3 [14-17]

6 Figure 3: Schematic of thermometric to binary code converter 4 SIMULATION RESULTS The Flash ADC is implemented by interconnecting different stages designed. The proposed ADC is simulated on Cadence Virtuoso 6.16 to estimate the parameters using TSMC 65nm technology. Transient analysis is carried out at 1 ff capacitive load, obtained simulation waveforms are as shown in Fig. 4, and it is traceable that input Vin is diverse from 0 to 1.2V in gradual increasing junctures, and output bits of FADC are observed; which are the equivalent binary output of the input voltage Vin depending upon the threshold voltage calculated through methodical deviation of transistor parameter sizes and observed the binary output as 000,001,010,011,100,101,110,111 with time interval of 1 LSB

7 Figure 4: Transient response of ADC using DFAL TIQ comparator DNL and INL plots for ADC with proposed TIQ comparator are shown in Fig. 5 and the corresponding maximum DNL = LSB /-0.61 LSB and INL = LSB / LSB, respectively. Figure 5: DNL / INL response plot Fast Fourier Transform (FFT) test is a typically carried out to measure the dynamic parameters of the ADCs and results are tabulated in Table II [16-19]. TABLE II. OBSERVED VALUES ADC PARAMETERS 7 701

8 In this paper, DFAL CMOS inverter based TIQ technique has been proposed for reduction of power in comparator stage of ADC. The proposed scheme effectively reduced the static power consumption up to 65.86% of the conventional CMOS inverter TIQ. The proposed method showed the static and dynamic parameter of Flash ADC as follows follows DNL = LSB /-0.61 LSB, INL = LSB / LSB, SNR= db, SNDR = db, SFDR = db and ENOB = 2.7 bits with load capacitance of 1 ff. References [1] S. Naraghi and D. Johns, A 4-analog-to-digital converter for high speed serial link Micronet annual Workshop, pp.33-34, April 26-27, [2] Ying-Zu-Lin, Cheng-Wu-Lin and Soon Jyh Chang, A 5bit 3.2GS/s Flash ADC with digital offset Calibration in IEEE Trans. VLSI Syst., Vol. 18, No. 3, pp , Mar [3] T. Cho and P.R. Gray, A 10b, 20Msample/s 35 mw pipeline A/D converter. IEEE J. Solid-State Circuits, vol. 30, pp , March [4] M. Choi and A. Abidi, A 6-b 1.3GSamples/s A/D Converter in 0.35 m CMOS, in Proceedings of the International Solid-State Circuits Conference, pages , [5] Ali Tangel and Kyusun Choi, The CMOS Inverter as a Comparator in ADC Design, Analog Integrated Circuits and Signal Processing, 39, , [6] Jincheol Yoo, A TIQ based flash A / D Converter for System on- Chip Applications, Ph. D. Thesis, The Pennsylvania State University, The Graduate School, Department of Computer Science and Engineering, May [7] Jincheol Yoo, Kyusun Choi, and Jahan Ghaznavi, Quantum Voltage Comparator for 0.07m CMOS Flash A/D Converters, Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI03)

9 [8] Vishal Moyal and Neeta Tripathi, Adiabatic Threshold Inverter Quantizer for a 3-bit Flash ADC presented at IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) on March 2016, Chennai, India, Part Number: CFP16D52-USB ISBN: , p.p [9] F. Kaess, R. Kanan, B. Hochet, M. Declercq, New Encoding Scheme for High-speed Flash ADCs, in Proc. Of ISCAS97, vol. 1, pp. 5-8, [10] Channakka Lakkannavar, Shrikanth K. Shirakol, and Kalmeshwar N. Hosur, Design, Implementation and Analysis of Flash Adc architecture with Differential Amplifier as Comparator using Custom Design Approach International Journal of Electronics Signals and Systems (IJESS) ISSN: , Vol-1 Iss-3, [11] D. Lee, J. Yoo, K. Choi and J. Ghaznavi, Fat Tree Encoder Design for Ultra-High Speed Flash A/D Converters, in Proc. Of MWSCAS-2002, vol. 2, pp. II-87 - II-90, [12] E. Sail and M. Vesterbacka, A Multiplexer Based Decoder for Flash Analog-to-digital Converters, in Proc. Of TENCON 2004, vol. 4, pp , [13] E. Sail and M. Vesterbacka, Thermometer-to-binary Decoders for Flash Analog-to-digital Converters, in Proc. of ECCTD 2007, pp , [14] Bui Van Hieu, Seunghyun Beak, Seunghwan Choi, Jongkook Seon and Taikyeong Ted. Jeong, Thermometer-to-binary Encoder with Bubble Error Correction (BEC) Circuit for Flash Analog-to-Digital Converter (FADC) 2010 Third International Conference on Communications and Electronics (ICCE), Aug. 2010, p.p , doi /ICCE [15] P. Palsodkar, P. K. Dakhole and P. Palsodkar, Improved power supply rejection (PSR) digital comparator based Flash analog to digital converter (FADC), Electronics and Communication 9 703

10 Systems (ICECS), 2014 International Conference on, Coimbatore, 2014, pp doi: /ecs [16] D. Malathi, Sanjay R, Greeshma R and B. Venkataramani, A 4-bit low power process tolerant flash ADC in 0.18m CMOS, Signal Processing, Communication and Networking (ICSCN), rd International Conference on, Chennai, 2015, pp doi: /icscn [17] P. Palsodkar, S. More and P. K. Dakhole, Improved linearity standard cell based flash ADC with DBNS encoding scheme, Devices, Circuits and Systems (ICDCS), nd International Conference on, Combiatore,2014, pp.1-5.doi: /icdcsyst [18] E. Sall, M. Vesterbacka, and K. O. Andersson, A study of digital decoders in flash analog-to-digital converters, in Proceedings of IEEE International Symposium on Circuits and Systems, vol. 1, pp , May [19] Maxim Integrated Products, INL/DNL Measurements for High-Speed Analog to-digital Converters (ADCs)

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