Sandeep Kakde Dept. of Electronics Engineering Y. C. College of Engineering Nagpur, India

Transcription

1 Design and Implementation of Flash ADC using TIQ and Transmission Gate for High Speed Application Abhishek Madankar Dept. of E&TC Engineering Y. C. College of Engineering Nagpur, India Sandeep Kakde Dept. of Electronics Engineering Y. C. College of Engineering Nagpur, India Abhijit Asati EEE Group Birla Institute of Technology Pilani, India ABSTRACT The main design blocks of Flash ADC includes the design of comparator, decoder and digital to analog convertor. The design of comparator is the most critical task in this paper because the performance of ADC depends on the choice of comparator. This paper describess the design of high speed FLASH ADC using clocked digital comparator with 4-bit resolution. Analog signal is characterized by the signal whose amplitude is continuously changing with respect to time. The clock digital comparator is designed in TSMC 0.18 μm CMOS technology with supply voltage of 1.8 V. The length of transistor is fixed and depending upon the width of transistor, internal references voltages are generated in the range of to 1.02 V. The proposed 4-bit flash ADC using CDC is designed using multiplexer based Decoder and simulated with the help of TANNER-EDA tool in TSMC 0.18 μm CMOS technology. High speed clocked digital comparator with inverter configuration is used for dynamic offset suppression. The comparison of result are shown in the result part. Keywords:- Flash ADC, CMOS-Clocked Digital Comparator, Multiplexer Analog to digital convertor, Transistor Inverter Quantizer (TIQ). middle bit. The second MSB and LSB s of output binary bits are obtained depending on the value of middle bit, if the value of middle bit is 0 then multiplexer based decoder circuit select the upper bits (Right side bits of middle bit) and if value of middle bit is 1 then it selects lower bits (Left side bits of middle bit). CLOCKED DIGITAL COMPARATOR For conversion of analog signal into digital signal requires the quantizer, sampler and encoder. In clocked digital comparator as shown in fig. 1, the first stage consist of two inverter, the first inverter is acting as the quantizer by settling the comparator voltages for comparison and the second inverter is acting as the logic level inversion. The need of second inverter arises due to the output of first inverter. In ADC and DAC structure, the output should be same as the input signal but the first inverter inverts the input and later on, we will get the output out of phase, so for nullifying the phase shift, we have to add the second inverter. INTRODUCTION Analog to digital convertor circuit converts continuously changing analog signal into digital signal. Analog signal is characterized by the signal whose amplitude is continuously changing with respect to time while the amplitude and time is discrete in case of digital signal. The ADC is characterized by three-factors namely speed, area, and power consumption, the cost of ADC is varying from application to application. According to moor s law as the technology shrinks the speed of device increase and the supply voltage decrease this is the quite challenging in CMOS technology. Flash ADC with Clocked Digital Convertor (CDC) configuration eliminates the resistive network required for generation of internal reference voltage. Flash Analog to Digital Convertor (FADC) consists of two stages. In first stage Clocked Digital Comparator (CDC) have back -to-back inverter configuration followed by transmission gate. Transmission gate is used for sampling. Second stage of ADC consists of multiplexer based decoder, which requires less hardware and has short critical path. In multiplexer based decoder, middle bit is used as select line of 2:1 MUX because it consists of two stages (0 and 1) rest of the bits follows the thermometer code hence the MSB of output binary code is exactly same as the Fig.1 Clocked Digital Comparator TRANSISTOR INVERTER QUANTIZER Comparator structure is most pivotal part in FADC architecture. The role of comparator is to compare the input signal with reference voltage and gives the respective logic levels (1 and 0) the comparator converts the input signal into only two logics (logic1 and logic 0) depending on the values of input, if the values of input is greaterr than threshold value then it ll give logic 1 else it ll give logic 0. The TIQ shown in fig 2 is the first stage of Clocked Digital Comparator, it is use for generating the internal reference voltage, which is required for comparison, and the internal reference voltage is generated using number of methods namely resistive ladder network, systematically varying the size of transistor. 82 P a g e

2 Fig.2 Transistor Inverter Quantizer (TIQ) In Transistor Inverter Quantizer (TIQ), systematic varying the width of NMOS and PMOS transistors generates the internal reference voltage. We are keeping the length of transistor is same because the length of transistor depends on the technology. CMOS INVERTER AS PHASE SHIFTER The inverter provides phase shift, amplification, quantization stages. Let us consider the signal given to the clocked digital comparator is sine wave then inverter gives the output negative of sine wave, X () t A*() SIN wt as input inverter gives X () t A*() SIN wt we further solved this equation by 1 applying some mathematical relationship SIN ()( A B *)( SINA *) COSB COSA SINB X ()( t *()*())( A SIN *()*()) wt COS A COS wt SIN 1 X () t A*() SIN wt 1 [() COS 1 SIN() 0] CMOS INVERTER AS QUANTIZER The Clocked Digital Comparator compares the input voltage with reference voltage generated internally by varying the width of each comparator. Depending on the value of reference voltage, each comparator gives its logic level. The four-bit comparator requires fifteen comparators since they ll generate their respective fifteen levels and act as quantizer. TRANSMISSION GATE The second stage consist of transmission gate, the use of transmission gate is for sampling the signal as we know the transmission gate work on clock signal if the transmission gate is positive edge enabled clocked then it works only for positive edges that means it only pass the logic for positive edge and blocked the logic for negative edge that s why we generally called transmission gate as the switch. The frequency on which clocked operates called as sampling frequency and the sampling frequency should be more than twice of input frequency, so the clocked digital comparator is acting as the quantizer and sampler. Fig.3 Tanner Implementation of Transmission Gate MULTIPLEXER BASED DECODER The multiplexer based decoder consists of 2:1 multiplexer, which requires 11 multiplexer for implementation of 15 inputs. The 2:1 multiplexer requires two input signals with one select line, depending on the select line input will selected, the M.S.B. bit of binary input equal to middle bit of thermometer code because it uses the twin logic. Table.I Conversion of 3-bit thermometer to binary code Thermometer code Binary Code T3 T2 T1 B2(MSB) B Fig.4 Tanner Implementation of MUX Based Decoder P a g e 83

3 DIGITAL TO ANALOG IMPLEMENTATION The DAC configuration shown in figure 5 consist of a network of resistor alternating in value of R and 2R. Starting from bottom of network the 2R resistor is connected to the Vref- the digital input decides which resistor is switched to Vref- and Vref+. Fig.6 Tanner Implementation of Analog to Digital Convertor Fig.5 Digital to Analog Convertor WORKING WITH ADC-CDC The comparators are working on their internal reference voltages. As the input signal, amplitude crosses the threshold value of reference voltage. Comparator works, and generates thermometer code. As the input signal crosses maximum value of amplitude then all comparator moves to the saturation region they produces the output equal to logic 1. After interfacing ADC and DAC together, they must produce the output same as the input signal which is shown below. The threshold voltages are laying in the range from to 1.02 volt for this range ADC produces the respective binary bits. Below this range, the output equals to zero and above this range, the output equals to one. During positive interval of clock, it produces output; otherwise zero. The above logic is valid only when the amplitude of input signal starts from zero and reaches toward the maximum value as the amplitude falls from the maximum value toward zero value the effect of mobility arises. As we know, the mobility of electron is equal to the three times the mobility of hole, the output is not same as the input. When the input is at logic zero, the pmos produces the output equal to logic one but if you observe, as the pmos conducts, it will connect to the VDD (positive supply) supply. It requires some delay but in case of NMOS transistor, when it conducts it will connect it to ground (negative supply). It will connect to the ground fast as compare to PMOS that is why the output is not exactly same as the input. Fig.7 Tanner implementationn of ADC-DAC SIMULATION RESULT Fig.8 Tanner implementation of TIQ The Intersection between input signals with the output signal gives the internal reference voltage required for comparison. The range of reference voltage is volt. The flash ADC produces the binary output according to the Amplitude of Input signal. As the input signal crosses first (0.653) and last (1.02) referance voltage it genrate 0000 and P a g e

4 Simulation Results of ADC-DAC for 180 nm technology The output generated by ADC-DAC look like Input signal. The ADC-DAC produce the output signal based on the binary bit generated by ADC, The ADC generate output bit ranging from 0000 to 1111 only for the range of Internal reference voltage of comparator. Fig.9 DC Sweep Transfer Characteristic of CDC Fig.12 Transient Result of ADC and DAC for 4-bit Resolution Fig.10 Output Waveform for 4-bit Flash ADC Simulation Results of DAC for 180 nm technology The Input binary bits generate the output analog signal. The DAC is based on the binary weighted sum of the input. It generates amplitude of outputt signal for 0000 Input and 1.02 for 1111 Input. TABLE.II Comparison with standard design / Standard Result/ Expected Result Parameter Specification Ideal value Architecture Flash Flash Resolution 4 bit 4 bit Power Supply 1.8 v 1.8v Technology Sampling Frequency Input Frequency SNR ENOB DNL INL TSMC 0.18 um 1 GHz 10 MHz db 3.86 Bit / LSB /-1.5 LSB TSMC 0.18 um 1 GHz 10 MHz db 4 Bit +0.5 LSB/-0.5 LSB +0.5 LSB/-0.5 LSB Reference Voltage 1.02/ /0.653 Fig.11 Output Waveform for 4-bit Flash DAC Fast Fourier Transform (FFT) Result The fast Fourier Transform plot is required for finding out the Dynamic Parameters like Signal to Noise Ratio (SNR), Spurious Free Dynamic Range (SFDR), Dynamic Range (DR) and Effective Number of Bits (ENOB). P a g e 85

5 and Systems (APCCAS), IEEE Asia Pacific Conference, pp , [4] M. Wang, High Speed Low Power CMOS flash analog to digital convertor for wideband communication system-on-a-chip phd Dissertation, The Wright State University, [5] Erik Säll and Mark Vesterbacka A MULTIPLEXER BASED DECODER FOR FLASH ANALOG-TO-DIGITAL CONVERTERS Proceeding of IEEE, 2004 [6] Sail, E., Vesterbacka, M., A multiplexer based decoder for flash analog to digital convertor, TENCON 2004, Page (s): vol.4. [7] J. Yoo, A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications,, Ph.D. Dissertation, The Pennsylvania State University, May, Fig.13 Fast Fourier Transform (FFT) Result CONCLUSION The design of Flash ADC includes the design of comparator, decoder and digital to analog convertor. The design of comparator is the most critical task in this paper because the performance of ADC dependsds on the choice of comparator. In this paper, CDC is used which is suitable for increasing the speed of ADC. Decoder architecture used is Multiplexer Based decoder, which will reduce the complexity. The DAC architecture is implemented with the help of Resistive Ladder Network.The Static characteristics like Differential Non Linearity error (DNL) and Integral Non Linearity error (INL) are found in the range of / LSB and /-1.5 LSB and Dynamic characteristics like SNR, SFDR, DR and ENOB are found as db, db, db and 3.86 bit. The Flash ADC and DAC is implemented and characterized in the following ways: 1) No external Resistor array is needed for generating the internal reference voltages. 2) The Multiplexer based Decoder is used due to which the hardware requirement Reduces. 3) No need of sample and hold circuit which will cause the increment in speed.4) Less possibility for the meta-stable output due to high switching speed of CDCs. [8] Jincheol Yoo, Kyusum Choi and Tangel, A 1-GSPS CMOS flash A/D convertor for system on chip application, IEEE computer society workshop on April 2001 Page (s): [9] A. Tangel, VLSI Implementation of the Threshold Inverter Quantization (TIQ) Technique for CMOS Flash A/D Converter Applications PhD Dissertation, The Pennsylvania State University, Aug Chia- Chun Tsai Kai-Wei Hong Yuh-Shyan Hwang Wen-Ta Lee Trong-Yen Lee, New power saving design method for CMOS flash ADC, MWSCAS '04. The th Midwest Symposium on Circuits and Systems, 2004.VOl 3, pp [10] J. Ramesh, K. Gunavathi, A 8-BIT TIQ based 780 msps CMOS flash A/D converter, IEEE International Conference on Computational Intelligence and Multimedia Applications 2007, pp [11] P.Iyappan, P.Jamuna, and S.Vijayasamundiswary, Design of Analog to Digital Converter Using CMOS Logic, IEEE International Conference on Advances in Recent Technologies in Communication and Computing, 2009, pp REFERANCES [12] Baljit Singh and Praveen Kumar Charactrizaation analysis of a High speed, Low Resolution ADC based [1] M. Kulkarni, Sridhar, G.H. Kulkarni, The Quantized on simulation results for different resolutions 2009 Differential Comparator in Flash Analog to Digital international conference on information and Convertor Design IJCNC, July 2010 multimedia technology. [13] JincheolYoo, Daegyu Lee, Kyusun Choi and Ali [2] Mingzhen Wang, Hongxi Xue Design Optimization Tangel, Future ready ultra-fast 8-bit CMOS ADC for of CMOS CDC Comparators Proceeding of ICCP, system on-chip applications, IEEE International 2011 ASIC/SOC Conference, pages , [3] MeghanaKulkarni, V. Sridhar, G.H. Kulkarni 4-Bit [14] Amol Inamdar, Anubhav Sahu, Jie Ren, Aniruddha Flash Analog to Digital Converter Design using Dayalu, and Deepnarayan Gupta, "Flash ADC CMOS-LTE Comparator IEEE Conference Circuits 86 P a g e

6 Comparators and Techniques for their Evaluation", IEEE Transactions on Applied Superconductivity, Vol. 23, no. 3, ISSN No ,pp. 1-8, Jan [15] Xiangliang Jin, Zhibi Liu, and Jun Yang, "New Flash ADC Scheme With Maximal 13 Bit Variable Resolution and Reduced Clipped Noise for High- Performance Imaging Sensor", IEEE Sensors Journal, Vol. 13, no. 1, pp , Jan [16] Young-Kyun Cho, Jae-Ho Jung, and Kwang Chun Lee, "A 9-bit 100-MS/s Flash-SAR ADC without Track-and- Hold Circuits", International Symposium on Wireless Communication Systems (ISWCS),ISBN No , pp , Aug [24] Arulkumar, C. V., and P. Vivekanandan. "Multi-feature based automatic face identification on kernel eigen spaces (KES) under unstable lighting conditions." Advanced Computing and Communication Systems, 2015 International Conference on. IEEE, [25] Sundaramoorthy, S., M. Kowsigan, J. Rajesh Kumar, and C. V. Arulkumar. "Semantic Keyword Search on XML." In International Journal of Engineering Research and Technology, vol. 1, no. 3 (May-2012). ESRSA Publications, [17] Joyjit Mukhopadhyay and Soumya Pandit, " Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics", Hindawi Publishing Corporation VLSI Design, Vol. 2012, pp. 1-13,2012. [18] Chakir Mostafa,Hassan Qjidaa, "1 GS/s, Low Power FlashAnalog to Digital Converter in 90nm CMOSTechnology", IEEE conference on Multimedia Computing and Systems (ICMCS), 2012 International,pp ,May2012. [19] Yun-Shiang Shu, "A 6b 3GS/s 11mW Fully Dynamic Flash ADC in 40nm CMOS with Reduced Number of Comparators", IEEE Symposiumm on VLSI Circuits Digest of Technical Papers,pp , June2012. [20] Ch. Vassou, L. Mountrichas, S. Siskos, "A NMOS Bulk Voltage Trimming Offset Calibration Technique for a 6-bit 5GS/s Flash ADC", IEEE International Conference on Instrumentation and Measurement Technology (I2MTC),pp. 5-8,May [21] Soon-Kyun Shin, Jacques C. Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, and Matthew Z. Straayer, "A 12b 200MS/s Frequency Scalable Zero-Crossing Based Pipelined ADC in 55nm CMOS",IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4,2012. [22] Yuji Gendai, and Akira Matsuzawa, "A Speci?c Distortion Pattern of Flash ADCs Identi?ed by Discriminating Time-Domain Analysis", IEEE transactions on instrumentation and measurement, vol. 61, no. 2, pp , Feb [23] V Arulkumar, C., et al. "Secure Communication in Unstructured P2P Networks based on Reputation Management and Self Certification."International Journal of Computer Applications (2012): 1-3. P a g e 87