nd International Conference on VLSI Design

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1 29 22nd International Conference on VLI Design Design of a Low Power, Variable-Resolution Flash ADC reehari Veeramachanen, A. Mahesh Kumar, Venkat Tummala*,M.B. rinivas Centre for VLI and Embedded ystem Technologies(CVET), International Institute of Information Technology (IIIT), Gachibowli, Hyderabad, 532, India. * an Jose tate University srihari@research.iiit.ac.in, maheshkumar_a@research.iiit.ac.in, ven646@gmail.com srinivas@iiit.ac.in. Abstract: In this paper, a low power and variable resolution (adaptive) flash ADC is proposed. The ADC enables exponential power reduction while the reduction in resolution is linear. In the proposed design, unused parallel voltage comparators are switched to standby mode leading to consumption of only the leakage power. The ADC, capable of operating at 4-bit, 5-bit, and 6-bit precision, dissipates 6mW at 4-bit and 2mW at 6-bit, and operates at a sampling frequency of to 2 GP. The ADC has been designed and simulated in standard 65nm CMO technology using Cadence tools. conversion resolution is high. Because many comparators compare the reference voltage with input voltage at the same time, power consumption in the flash architecture is much larger than for the others. Controlling the power consumption in the comparator is the key to reducing the overall power consumption in a flash ADC. V in Vout Vin V ref C 63. INTRODUCTION V C 62 Analog-to-digital converter (ADC) is a fundamental block in mixed-signal VLI circuits. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an analog-todigital converter (ADC). These parameters cannot be changed once an ADC is designed. While one can use 6-bit precision from an 8-bit ADC, it is non-optimal resulting in slower speed and extra power consumption due to full 8-bit internal operation. In this paper, a new flash ADC design is proposed that is a true variable-power and variable-resolution ADC. It can operate at higher speed and will consume less power when operating at a lower resolution. uch features are highly desirable in many wireless and mobile applications. For example, the strength of a radio frequency (RF) signal varies greatly depending on geographic location. Optimally, the ADC resolution can be reduced upon the reception of strong signal and can be increased upon the reception of weak signal. ubstantial reduction in power consumption at lower resolution will prolong the battery life. 2. Background Low power ADC architectures are implemented with pipelined, successive approximation, and sigma-delta modulators. These are all useful for the medium speed conversion and high resolution applications. On the other hand, the flash architecture is suitable for high speed conversion and low resolution applications due to its parallel architecture. Figure represents the conventional flash ADC with dc characteristics, which requires many analog comparators and the complexity and power dissipation become very high. Moreover, the accuracy of dividing resistors requires high value for reference voltage if the C (a) (b) (c) Figure : Differential voltage comparator In this work, the authors propose a new, low-power and low-voltage flash ADC based on an existing approach [-3,8] of TIQ-based ADC in which the ratio of channel length and width are designed by which the transition threshold of the CMO inverters is varied to detect input analog signal. The values are then encoded into the digital code. The advantages are that the ADC circuit does not need any resistor and uses simple CMO inverters rather than analog comparators. 3 Proposed ADC Design The key feature of the comparator in the proposed design is the fact that the comparator can easily and quickly switch from active mode to standby mode. It consists of following four sub blocks followed by their integration. 3. Bias block 3.2 Peak detector 3.3 comparator 3.4 Decoder block 3. Bias block Bias block consists of band-gap reference and voltage regulator generating reference voltages as shown in the figures 2. The band-gap reference block generates.7v and /9 $ IEEE DOI.9/VLI.Design Authorized licensed use limited to: NATIONAL CHANGHUA UNIVERITY OF EDUCATION. Downloaded on February 2,2 at 23:54:36 ET from IEEE Xplore. Restrictions apply.

2 voltage regulator generates reference voltages V=., V2=.9 and V3=.7 in this application. V3 The proposed comparator uses two cascading CMO inverters as a comparator for high speed and low power consumption. This is a modification of Tangel [-3] who used TIQ comparator for implementing a high speed flash ADC. Band-Gap Reference Block Vref Voltage Regulator V2 V 3.3. CMO Inverter as a Comparator The inverter threshold (Vm) is defined as the Vin = Vout in the VTC of an inverter. Mathematically, 3.2 Peak detector Figure. 2. Bias block The function of the peak detector is to compute the peak value of the input. The circuit follows the voltage peaks of a signal and stores the highest value on a capacitor. If a higher peak value signal comes along, this new value is stored. The highest peak value is stored until the capacitor is discharged. Consider the circuit of figure 3. When input V in exceeds Vc, the voltage across capacitor, the diode D is forward biased and the circuit becomes a voltage follower. Consequently, the output voltage Vo follows V in as long as V in exceeds Vc. When V in drops Vc, the diode becomes reverse-biased and the capacitor holds the charge till input voltage again attains a value greater than Vc. Figure 4 shows the different voltage wave shapes for the peak detector. The advantage of peak detector is self-triggering, self-sparsifying and timing output. Vin + A _ D Figure. 3. Peak detector Figure. 4. Different Voltage wave shapes for the peak detector V V C C (a) Inverter schematics diagram (3.) (b) Inverter VTC Figure. 5. Inverter schematic and VTC Where VTp and VTn represent the threshold voltages of PMO and NMO devices, respectively. Figure 5 shows the schematic of an inverter and its VTC from the simulation. The first inverter consists of controllable inputs Vctrlp and Vctrln to operate inverter in stand-by mode or active mode as shown in figure 5(a). At the input the analog signal quantization level is set by Vm depending on the W/L ratios of PMO and NMO, the control voltages Vctrlp= and Vctrln= for active mode and Vctrlp= and Vctrln= for stand-by mode. The second inverter is used to increase voltage gain and to prevent an unbalanced propagation delay. In Figure 5(b), the slope of Vout is shown larger than the one of Vout. The inverter threshold depends on the transistor sizes. The inverter VTC Va and Vb show the difference from the VTC of Vout. With a fixed length of the PMO and NMO devices, we can get desired values of Va and Vb by increasing only the width of the PMO and NMO transistors, respectively. This result can be confirmed by the following equation of the inverter threshold 3.3 Comparator The comparator is the most important component in the ADC architecture. Its role is to convert an input voltage (Vin) into a logic `' or `' by comparing a reference voltage (Vref) with the Vin. If Vin is greater than Vref, the output of the comparator is `', otherwise `'. (3.2) where µp and µn are the electron and hole mobility, respectively. To derive above Equation, we assume that both 8 Authorized licensed use limited to: NATIONAL CHANGHUA UNIVERITY OF EDUCATION. Downloaded on February 2,2 at 23:54:36 ET from IEEE Xplore. Restrictions apply.

3 transistors are in the active region, the gate oxide thickness (Cox) for both transistors is the same, and the lengths of both transistors (Lp and Ln) are also the same. From Equation 3.2, we know that Vm is shifted depending the transistor width ratio (Wp/Wn). That is, increasing Wp makes Vm larger, and increasing Wn results in Vm being smaller on the VTC. This changing of the widths of the PMO and NMO devices with a fixed transistor length is the idea of the TIQ comparator[-3]. We can use the inverter threshold voltage as an internal reference voltage to compare the input voltage. However, to use the CMO inverter as a voltage comparator, we should check the sensitivity of Vm to other parameters, which are ignored in Equation 3.2, for correct operation of the proposed flash ADC. 3.4 Decoder block A decoder for flash analog-to-digital converter with short critical path, regular structure, and small area has been suggested earlier [4]. In this work, it has been modified to make its operation efficient. The decoder is based on 2: multiplexers connected as a tree. Each level of the tree divides the input thermometer scale in two and calculates one of the bits in the binary output. In comparison with the Wallace tree decoder and the folded decoder the length of the critical path is approximately reduced to one third and one half, respectively. The amount of hardware is also reduced, which will translate to a power saving, compared with the Wallace tree decoder and the folded decoder. The multiplexer-based encoder can be found by observing that the most significant bit (MB) of the encoder output is equal to the middle digit in the thermometer code. The second highest bit is found in the same way, but only considering a part of the whole thermometer code. The lower half if the middle digit is zero, otherwise the upper half. This is continued until all output bits are found. The algorithm is illustrated by the figure 6 below to the left and can be realized by the circuit below to the right, which entirely consists of 2-to- multiplexers. Hence, it has a regular structure, which is an advantage during layout [5]. A comparison between different types of encoders as shown in table, also indicate that this encoder has the lowest hardware cost among all and shortest critical path. Hence, it is probable that it also is the fastest encoder. In the following figure 6, block diagram is shown with an example. Type of encoder N.o. MUX's Critical path Wallace tree 7 MUX 8 t mux 4-level folded 8 MUX 2 t mux Multiplexer based 57 MUX 5 t mux Table Different types of encoders (a) b3 b2 b b b3 b2 (b) A A (c) B B b b Figure 6 Decoder block diagram with example Figure 6 (c) represents the CMO based 2-to- multiplexer. The advantage of this multiplexer are. Acts as gain booster in the ADC. 2. Low leakage operation 3. Two legs are symmetrical 4. Layout area of the MUX is less and symmetry 5. Power dissipation is less 3.5 Integration of Blocks The proposed flash-adc features modified threshold inverter quantization (TIQ) technique [-3] for low power and variable resolution using standard CMO 65nm technology. Figure 7(a) and 7(b) shows Peak Detector for Reconfigurability and block diagram of the proposed ADC. The proposed ADC consists of bias block generating reference voltage V, V2, V3 (V>V2>V3) which are used as reference levels to determine the voltage levels of the analog input signal, peak detector for determining the voltage levels, 63 inverters, decoder s (4-bit, 5-bit and 6-bit), digital block and output multiplexer. The analog input signal Vin is given to the peak detector and the inverters. Peak detector consists of an amplifier, three diodes D, D2, D3, comparators and multiplexers. When the input signal Vin applied to the peak detector the comparator output comp is high and mux is short circuited. when Vin exceeds V k then diode D is forward biased and the circuit becomes a voltage follower. Consequently, the output V k follows Vin as along as Vin exceeds V k. When Vin drops below Vc, the diode becomes reverse biased and the capacitor holds the charge till input voltage again attains a value greater than Vc. when diode D is reverse biased and the voltage V k =Vc is greater than V then comparator Comp triggers and output is. In this case mux open circuited and the peak voltage is stored on to the capacitor (Vc). The control signals C= and C2=C3= and hence peak detector acts as V voltage peak detector. The control voltages C, C2 and C3 are given to a digital block to generate control voltages (A, A2 and A3) for decoders as shown in table 2. 9 Authorized licensed use limited to: NATIONAL CHANGHUA UNIVERITY OF EDUCATION. Downloaded on February 2,2 at 23:54:36 ET from IEEE Xplore. Restrictions apply.

4 INPUT OUTPUT C C2 C3 A A2 A3 Table 2. Control ignals for inverters, Decoders and Multiplexer 6-bit inverters are designed with different threshold voltages i.e., for highest input peak voltage signal the control signal values are C=, C2=C3= which will turn on (active mode) LB inverters from to 5 and turn off (stand-by mode) from 6 to 63. In the decoder section we have 4-bit, 5-bit and 6-bit decoders separately. The control signal A=, A2=A3= which will select 4-bit decoder and output multiplexer such that proposed ADC operates as 4-bit ADC with highest input analog signal. For the second highest peak input analog signal, the signal is compared with reference voltage V2. During this comparison if V k2 =Vc is greater than V2 then comparators Comp, Comp2 triggers and outputs of comparators go to therefore C=C2=, C3= and digital block outputs are A=A3=, A2=. Hence peak detector acts as V2 voltage peak detector. The control signals C, C2, C3 will turn on (active mode) inverters from to 3 and turn off (stand-by mode) from 32 to 63. The control signals A, A2 and A3 will select 5-bit decoder and output multiplexer such that proposed ADC operates as 5-bit ADC. For the Lowest peak input analog signal, the signal is compared with reference voltage V3. During this comparison, if V k3 =Vc is greater than V3 then comparators Comp, Comp2, Comp3 triggers and outputs of comparators go to therefore C=C2=C3= and digital block outputs are A=A2=, A3=. Hence peak detector acts as V3 voltage peak detector. The control signals C, C2, C3 will turn on (active mode) inverters from to 63. The control signals A, A2 and A3 will select 6-bit decoder and output multiplexer such that proposed ADC operates as 6-bit ADC. Figure 7(b) Block diagram of Proposed ADC 4 imulation Results This section describes the functional simulation of the proposed ADC and characterization to verify that is suitable for high speed, low voltage application. 4. Functional simulation A transient and DC analysis of the ADC is done by giving a ramp input going from.264v to.888v (which is full scale range of the ADC) and with each LB voltage level (VLB) of mv. The digital codes were obtained correctly going from to 63 at the output with one VLB of mv, indicating that the ADC was functionally correct. The simulation results are shown in figure 8(a) and figure 8(b). The programmable resolution based upon analog input peak voltage and its corresponding power consumption values and performance parameters are given in table 3. Vin + _ D D2 D3 K K2 K3 MUX _ MUX2 _ MUX3 _ + V + V2 + V3 comp comp2 comp3 C 4 bit C2 5 bit C3 6 bit Vc Digital Logic A A2 A3 Figure 7(b) Peak Detector for Reconfigurability Figure 8(a) Transient analysis of the 6-bit ADC to prove functional correctness 2 Authorized licensed use limited to: NATIONAL CHANGHUA UNIVERITY OF EDUCATION. Downloaded on February 2,2 at 23:54:36 ET from IEEE Xplore. Restrictions apply.

5 DNL and INL testing is done by including verilog-a block which generates a slowly varying full scale range ramp is given as input to the proposed flash ADC, which completes the full scale range in 63 steps for transistor level implementation. The values of the each code are compared with ideal value and store the difference value. The results show that the ADC exhibits a maximum DNL of.4lb. and INL of.35lb as shown in the Fig 9 and Fig respectively Characterization Figure 8(b) Inverter threshold levels The proposed ADC (4-bit, 5-bit and 6-bit) is designed in 65nm technology, characterized for parameters like differential non-linearity (DNL), integral non-linearity (INL) (tatic performances), signal-to-noise ratio (NR), signal to noise and distortion ratio (NDR) and effective number of bits (ENOB) ( Dynamic performances) [6-8] as shown in table 3. DNL(LB) OUTPUT CODE.4.3 Figure 9: DNL plot of the 6-bit ADC.2 4-bit 5-bit 6-bit DNL (LB) INL (LB) Input frequency.2gs/sec Gs/sec 8Ms/sec NR 3dB 3dB 34.5dB NDR 29.5dB 29.5dB 34dB ENOB Avg.Power(mw) 6mw 9mw 2mw Layout Area (um2) 32x32 4x4 5x5 Power supply (v) Table 3 Proposed ADC features for 4-bit, 5-bit and 6-bit. The proposed ADC designed for 6-bit is compared with conventional 6-bit comparator based ADC for static performance, dynamic performance and power consumption as shown in table 4. INL (LB) OUTPUT CODE Figure INL plot of the flash ADC The NR and NDR of the designed ADC have been measured at an input frequency of 4MHz. The flash ADC is fed a sinusoidal input which covers the entire full scale range, and the output is fed to an ideal DAC is a reconstructed, digitized sine wave, at 4MHz. The FFT of this sine wave is plotted, from which NR and NDR values at different input frequency range is shown in the figure. The NR and NDR was found to be 34.5 db and 34. db. Comparator based ADC Design Proposed ADC Design DNL (LB).8.4 INL (LB).5.35 Input frequency 8Ms/sec 8Ms/sec NR 32.3dB 34.5dB NDR 3.86dB 34dB ENOB Avg.Power(mw) 7mw 2mw Layout Area(um2) 9x9 5x5 Power supply.2v.2 Table 4 Comparison of 6-bit comparator based and Proposed ADC design Figure NR and NDR plot The effective number of the bits (ENOB) shows an ADC s performance at a specific input frequency. The ENOB is really related to the input frequency. If the input frequency is increased, then the ENOB degrades. The ENOB can be calculated with NDR as shown in equation. ENOB = (NRD.76) / Authorized licensed use limited to: NATIONAL CHANGHUA UNIVERITY OF EDUCATION. Downloaded on February 2,2 at 23:54:36 ET from IEEE Xplore. Restrictions apply.

6 ENOB for five different frequencies is shown in the table 4. Table 4 Different ENOB values with respect to frequency. I/P Frequency No of bits ENOB MHz 6-bit 5.6 2MHz 6-bit 5.5 3MHz 6-bit 5.4 4MHz 6-bit MHz 6-bit Power simulation Figure 2 shows the comparison of power consumption for conventional 6-bit flash ADC and proposed 6-bit ADC design. We observe that peak powers are 7mW and 2mW for conventional ADC and proposed ADC respectively. Figure 4 Layout of Proposed ADC Figure 4 represents the layout view of the Proposed ADC. ADC footprint is made such that all input pins are brought on to the left side and output pins are on the right side of the layout. Conclusion The proposed low power and variable resolution flash ADC design operates at high speed with programmable resolution based upon analog input peak voltage. It operates at higher speed, lower resolution and consumes less power. The advantage of proposed ADC is built in peak detector which will detect the peak level of the analog input signal and provides programmable feature (i.e., at highest input voltage peak level ADC will operate as 4bit and for lowest input voltage peak level ADC will operate as 6-bit). Figure 2 Instantaneous power plot of the flash ADC The flash ADC is fed a sinusoidal input operating at a frequency of 8MP which covers the entire full scale range, and the output is fed to an ideal DAC is a reconstructed, digitized sine wave, at 8Ms/sec is shown in the figure 3. Figure 3 8Msamples/sec 6-bit ADC Input and output waveform. References [] A. Tangel, "VLI implementation of the threshold inverter quantization (TIQ) technique for CMO flash A/D converter applications." Ph.D. Dissertation, The Pennsylvania tate University, Aug [2] J. Yoo, "A TIQ Based CMO Flash A/D Converter for ystem-on-chip Applications", Ph.D Thesis, The Pennsylvania tate University, May 23. [3] Tangel, A.; Choi, K, 'The CMO Inverter as a Comparator in ADC Designs, spinger Analog Integrated Circuits and ignal Processing, Vol.39, pp.47-55,24. [4] E. äll, "Implementation of Flash Analog-to-Digital Converters in ilicon-on-insulator Technology," Linköping tudies in cience and Technology, Thesis No. 23, IBN , Linköping, weden, Dec. 2, 25. [5] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, 2nd Edition, 23. [6] Maxim Integrated Products, INL/DNL Measurements for High-peed Analog to-digital Converters (ADCs). [7] Maxim Integrated Products. Defining and Testing Dynamic Parameters in High-peed ADCs, 2 [8] Rudy J. van de Plassche, CMO Integrated Analog-to- Digital and Digital-to-Analog Converters, 2nd Edition, Authorized licensed use limited to: NATIONAL CHANGHUA UNIVERITY OF EDUCATION. Downloaded on February 2,2 at 23:54:36 ET from IEEE Xplore. Restrictions apply.