A new structure of substage in pipelined analog-to-digital converters

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1 February 2009, 16(1): The Journal of China Universities of Posts and Telecommunications new structure of substage in pipelined analog-to-digital converters JI Hua-yu ( ), CHEN Gui-can, ZHNG Hong Institute of Microelectronics, Xi an Jiaotong University, Xi an , China bstract The article presents a new (1+1)-bit/stage structure for pipelined analog-to-digital converters (DC). When the input analog signal of the structure exceeds the converting range of the whole DC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the DC. The structure is used in a 12-bit 40 M/s pipelined DC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators decision levels. The DC implemented in emiconductor Manufactory International Corporation (MIC) 0.18 μm CMO process consumes 210 mw and occupies a chip area of mm 2. Keywords digital correction, pipelined DC, residue voltage, operational amplifier 1 Introduction Many applications in digital communications and digitized imaging require high-speed and low-power DCs. mong various DC architectures, the pipelined converter is proved to be efficient for achieving a combination of high resolution and high speed. In the substage of pipelined DC, if the decision levels of the comparators have offsets, the converting error will occur in the next stage and the effective resolution of the converter is reduced. The error can be eliminated by the digital correction technique. The technique can correct the error by reducing the residue gain, using the 1.5-bit structure and overlapping the output codes of stages when they are added [1 3]. t the same time, many digital calibration techniques are developed to calibrate the errors of amplifier by multiplying digital-to-analog converter (DC) and other analog circuits of pipelined DC [4 5]. However, when these techniques are used to calibrate the errors, there is no redundancy in the substage of DC. For instance, when the nonlinearity of residue amplifier is calibrated by the signal statistics-based digital calibration technique, the output codes of sub-dc of the first substage are modulated by a random sequence Received date: Corresponding author: JI Hua-yu, jiahuayu@mail.xjtu.edu.cn DOI: / (08) number [6 9]. Therefore, redundancy will disappear in the stage and any error may cause its residue to exceed the ± V range ( ± V is full-scale input). If the second stage still uses the 1.5-bit, in the next stage, the converting errors will occur and the output residue will exceed ± V range. The article presents a new structure of substage for pipelined DC: (1+1)-bit/stage. When the input signal of the (1+1) bit/stage is in ± 1.5V range, the stage can still convert the input voltage correctly, and the output residue voltage will be in ± V range. The stage produces a 3 bit output code and can be used in combination with 1.5 bit in pipelined DC. The offsets of the comparators decision level are corrected at the same time. In the article, the (1+1) bit/stage structure is used in the second stage of a 12 bit 40 M/s pipelined DC to test the functions of the structure. 2 tructure design 2.1 tructure The residue transfer function of 2 bit substage is improved to get new characteristics. The residue curve of 2 bit substage whose residue gain is 2 is shown in Fig. 1(a). The vertical jumps occur at the comparator decision levels 0.5V, 0, and + 0.5V. When the input signal exceeds ± V range, the output residue also exceeds ± V range. The DC

2 Issue 1 JI Hua-yu, et al. / new structure of substage in pipelined analog-to-digital converters 87 output is shown above the curve for four regions of the input (00 in the first region, 01 in the second region, etc). Within each region, the residue crosses zero once. These zero crossings occur at ± 0.75V and ± 0.25V. positive offset is added to the 2-bit substage. s shown in Fig. 1(b), the decision levels of the comparators are increased by 0.25V, respectively. To reduce the range of the output residue and obtain a symmetric curve, a 0.75V decision level is added. The changed curve is shown in Fig.1(b). The new curve shows that when the input signal is in ± 1.5V range, the output residue remains within ± V range. Therefore, the residue does not exceed the input range of the next stage. The residue transfer function shows that the structure has 3 bit output and 5 codes 000, 001, 010, 011, and 100. The resolution of the stage is (log 2 5) 2.3. To distinguish with 1.5 bit and 2.5 bit, the structure is named (1+1) bit/stage. (a) Residue curve of 2 bit sub-dc 2.2 Output codes of DC with (1+1) bit/stage The (1+1) bit/stage is used after the stage whose output residue may exceed the DC converting range. ccording to Ref. [3], the total output code of the pipelined DC with (1+1) bit/stage can be calculated by the equation: m m 1 N m DOUT = DOUT() i Gk i= 1 N (2) i k= i where D OUT is the output code of the whole DC, D OUT (i) is the output code of the ith stage, N i and N m are the total codes number of the ith stage and the mth stage respectively, and G k is the residue gain of the kth stage. ssume that there is a three-stage converter with the stage resolutions 4, 3, and 3, and that the second stage is the (1+1) bit/stage structure. The residue gains of the first stage and the second stage are reduced by two times to introduce digital correction. This means N 1 = 16, G 1 = 8, N 2 = 4, G 2 = 2, N 3 = 8, and G 3 = 4. (ccording to Ref. [3], N 2 is the number of code before the comparator is added). By using Eq. (2), the output code can be calculated as DOUT = 8 DOUT(1) + 4 DOUT (2) + DOUT(3) (3) The total output code in this case can be produced by shifting D OUT (1) 3 steps and D OUT (2) 2 steps, without shifting D OUT (3) or adding all three together. The process of overlap-adding is illustrated in Fig. 3. Fig. 3 Calculation of the output code of the DC (b) Residue curve of (1+1) bit/stage Fig. 1 Residue curve The circuit of the structure can be designed according to the residue curve. The structure is shown in Fig. 2. The sub-dc with 4 comparators is used to quantize the analog input into 3 bit digital output. The multiplying DC (MDC) contains a DC, a subtractor, and a sample-and-hold (/H) amplifier. The output signal of the MDC is V = 2( V V) (1) IN 1 where 2 is the gain of the MDC, V IN is the analog input signal, and V 1 is the output signal of the DC. 3 Circuit design 3.1 ub-dc The structure of sub-dc is shown in Fig. 4. The sub-dc has 4 comparators. The positive inputs of the comparators are connected to the analog input signal V IN. The negative inputs of the comparators are connected to decision levels 0.75V, Fig. 2 tructure of (1+1) bit/stage Fig. 4 tructure of the ub-dc

3 88 The Journal of China Universities of Posts and Telecommunications V, 0.25V, and 0.75 V, respectively. The outputs of the comparators form the thermal codes a 0, a 1, a 2, and a 3. The thermal codes are encoded by logic block to produce the 3 bit binary output f 0, f 1, f 2. The relationship of input signal, thermal codes, and output of the logic block is shown in Table 1. Table 1 Output of the ub-dc Thermal codes Output of logic block Input signal (a 3, a 2, a 1, a 0 ) (f 2, f 1, f 0 ) V < 0.75V IN 0.75 V V < 0.25V IN 0.25V V < 0.25V IN 0.25V V < 0.75V IN V 0.75V IN 3.2 MDC The gain-of-two amplification and the analog subtracts of MDC are constructed by switched-capacitor circuits. Fig. 5 shows a simplified single-ended version of the circuits, although the final silicon uses a more precise, fully differential design. P 1 and P 2 are two-phased nonoverlapping clocks. During P 1, the bottom plates of capacitor C 1 is tied to V IN to implement the bottom-plate sampling scheme, and both of the plates of C 2 are tied to ground. During P 2, the bottom plate of C 2 is connected to the output of the operational amplifier, whereas the bottom plate of C 1 is connected to ±V or 0 or ±0.5V according to the control signal 1 5. during P 2 is as follows: When VIN < 0.75V, the bottom plate of C 1 is tied to V, VRE = ( VIN + V) (9) When 0.75V VIN < 0.25V, the bottom plate of C 1 is tied to 0.5V, VRE = ( VIN V) (10) When 0.25V VIN < 0.25V, the bottom plate of C 1 is tied to 0, VRE = VIN (11) When 0.25V VIN < 0.75V, the bottom plate of C 1 is tied to +0.5V, VRE = ( VIN 0.5 V ) (12) When VIN 0.75V, the bottom plate of C 1 is tied to +V, VRE = ( VIN V) (13) If and C 1 = 2C 2, the residue transfer function Eqs. (9) (13) can be written as VRE = 2VIN ± 2V or VRE = 2VIN ± V or VRE = 2VIN (14) 3.3 Operational amplifier Fig. 5 chematic of the MDC The signals 1 5 control the switch according to the following equations: (4) (5) (6) (7) = a3a2a1a0 (8) ssume that the operational amplifier of the MDC has a finite linear gain of, and the transfer function of the MDC To achieve precise transfer performance of the (1+1) bit/stage, the switching-capacitor circuits of MDC need to work precisely to follow Eq. (14). Therefore, it is important for operational amplifier to obtain as high gain as reasonably possible. In the article, a two-stage amplifier is presented to achieve high gain and reasonable output voltage swing. Fig. 6 shows the schematic of the fully differential amplifier that includes two stages. The first stage is folded-cascode amplifier with cascode PMO loads to get high gain. The second stage is common source circuit with PMO input device to get excellent output swing. The phase margin is improved by two capacitors C 1 and C 2 between the two stages. The common feedback circuit is not shown in the figure. The open-loop gain of the amplifier is 72 db and the unity-gain bandwidth is about 313 MHz with 1.5 pf load.

4 Issue 1 JI Hua-yu, et al. / new structure of substage in pipelined analog-to-digital converters 89 (b) DNL with (1+1) bit/stage Fig. 8 DNL performance Fig. 6 4 Experimental results Circuit of amplifier 12-bit 40 M/s pipelined DC is presented to test the function of the new structure. In the DC, the signal statistics-based technique is used to calibrate nonlinearity. Thus, the residue of the first stage may exceed the input range of next stage. The topology of our DC is shown in Fig. 7. The primary parts of analog circuit blocks include the sample-and-hold circuit, a 4-bit flash DC, a (1+1)-bit/stage, seven 1.5-bit/stage DCs and a 3-bit flash DC. lthough (1+1) bit/stage has more complicated circuits than 1.5 bit, the conversion speed is not reduced compared with that of 1.5 bit/stage. The simulational results show that the setting time of MDC s amplifier of (1+1) bit/stage is 6.03 ns, which entirely meets the requirements of resolution and conversion speed. The power dissipation and die size are 15.7 mw and mm 2, respectively. Both of them are approximately twice larger than those of 1.5 bit. Whereas, the (1+1) bit/stage has more binary outputs and codes than 1.5 bit. The DC is fabricated in MIC 0.18 μm CMO process. The die size is mm 2, as shown by the die photo in Fig. 9. The total power dissipation is 210 mw. The DNL and integral nonlinearity (INL) of the DC are LB and LB, respectively. nd the spurious free dynamic range (FDR) and signal to noise and distortion ratio (IND) are db and db, respectively. The testing results show that the (1+1) bit/stage has right function and can correct the offset of comparators decision level. Fig. 7 Topology of the DC In the simulated model, a 0.4% noise is added in the first stage of the DC. The differential nonlinearity (DNL) performance is shown in Fig. 8. ccording to Fig. 8(a), DNL is within LB range when the second stage is 1.5 bit/stage. s shown in Fig. 8(b), the DNL is improved within ±0.5 LB range when the second stage is (1+1) bit/stage. Fig. 9 Die photo (a) DNL with 1.5-bit/stage Table 2 shows a performance comparison between two similar products and the DC presented in this article. s can be seen from the table, the DNL and INL of this DC are much higher than those of D9235 and MX1421. The IND is higher than MX1421 but lower than D9235. Therefore, the static performance of this work has advantages and the dynamic performance should be improved in future work.

5 90 The Journal of China Universities of Posts and Telecommunications 2009 Table 2 Comparison with previous work This DC D9235 MX1421 Resolution/bit Conversion rate/mhz Power/mW IND/dB DNL(max)/LB INL(max)/LB 0.4 Not available 2 5 Conclusions The article presents a new sub-dc structure of pipelined DC: (1+1) bit/stage. The structure can correct the input signal when the signal exceeds the DC s converting range, and the output residue is within the converting range of the next stage. The testing results of the 12 bit 40M/s pipelined DC show that the (1+1) bit/stage can convert input signal in ±1.5V range correctly and produce the residue voltage in ±V range. cknowledgements This work was supported by the Project of pplied Materials (X-M ). References 1. tephen H L, Fetterman H, Gross G F, et al. 10-b 20-msample/s analog-to-digital converter. IEEE Journal of olid state Circuits, 1992, 27(3): Chuang Y, Terry L. digitally self-calibrating 14-bit 10MHz CMO pipelined /D converter IEEE Journal of olid state Circuits, 2002, 37(6): Gustavsson M, Wikner J J, Nianxiong N T. CMO data converters for communication. Boston, M, U: Kluwer cademic Pulishers, 2000: Wang X, Hurst P J, Lewis H. 12-bit 20-M/s pipelined DC with nested digital background calibration. Proceedings of IEEE Custom Integrated Circuits Conference, ep 21 24, an Jose, C, U. Piscataway, NJ, U: IEEE, 2003, Grace C R, Hurst P J, Lewis H. 12-b 80-M/s pipelined DC with bootstrapped digital calibration. IEEE Journal of olid-state Circuits, 2005, 40(5): Murmann B, Boser B E. 12b 75 M/s pipelined DC using open-loop residue amplification. IEEE Journal of olid-state Circuits, 2003, 38(12): Murmann B, Boser B E. Digitally ssisted Pipelined DCs. Boston, M, U: Kluwercademic Publishers, 2004: Li J P, Moon U K. Background calibration techniques for multistage pipelined DCs with digital redundancy. IEEE Transaction on Circuits and ystems, 2003, 50(9): Jun M, Lewis H. n 8-bit 80-M sample/s pipelined analog-to-digital converter with background calibration. IEEE Journal of olid-tate Circuits, 2001, 36(10): (Editor: ZHNG Ying)