A Digitally Enhanced 1.8-V 15-b 40- Msample/s CMOS Pipelined ADC

Transcription

1 A Digitally Enhanced.8-V 5-b 4- Msample/s CMOS d ADC Eric Siragusa and Ian Galton University of California San Diego Now with Analog Devices San Diego California Outline Conventional PADC Example Digitally Enhanced PADC Prototype System-Level Design Details Circuit-Level Design Details Measured Results Conclusion

2 A Conventional d ADC Example V in (t) Flash ADC x out Flash ADC 8 -b 4 Analog Digital Delays not shown Seven stages Each resolves slightly more than 3 bits -b of redundancy per stage Ideal and gains accuracy is just over 5b Conventional Switched Capacitor PADC Interstage gain error: Sources: capacitor mismatch finite open-loop amplifier gain incomplete amplifier settling Effect: leakage of quantization noise into PADC output DAC Noise: Source: capacitor mismatch Effect: introduction of signal-dependent errors Conventional solutions: Large capacitors high-gain op-amps Foreground calibration techniques Analog-intensive calibration techniques Trimming

3 Digitally Enhanced PADC Prototype Analog performance limitations are mitigated by background digital signal processing: Gain error correction (GEC) DAC noise cancellation (DNC) Segmented mismatch-scrambling 3 Demonstrated in a.8 μm CMOS prototype:.8 V 5 bit 4 Msamples/s 4 mw 9 db SFDR 7 db peak SNR 88 db THD. E. J. Siragusa I Galton IEE Electronics Letters March 3. I. Galton IEEE TCAS-II March 3. A. Fishov E. Siragusa J. Welz E. Fogleman I. Galton IEEE ISCAS May. IC Prototype High-Level Architecture V in Flash ADC Uncorrected ADC Output DNC/ GEC Logic DNC/ GEC Logic DNC/ GEC Logic Corrected ADC Output Flash ADC PRN Generator DEM 8 9 -b 4 Enhancements 3

4 Dynamic Element Matching Overview When DAC mismatches are present: -b DEM -b DEM alone improves SFDR but not SNDR! However DEM causes the noise to have structure : Noise was manipulated with known pseudo-random sequences and digital logic in the encoder DNC technique will exploit the structure to remove the noise Dynamic Element Matching DAC x {} DEM x x x 3 x 4 x 5 x 6 x 7 x 8 x 9 x -b DAC -b DAC -b DAC -b DAC -b DAC -b DAC -b DAC -b DAC -b DAC -b DAC / eh if x[ n] / el if x[ n] yn [ ] xn [ ] edac[ n] /4 eh if x[ n] /4 el if x[ n] DEM uses pseudo-randomization to convert -b DAC mismatches e hi and e li into a constant gain α a constant offset β and white DAC noise e DAC. 4

5 DEM DAC Example for x = x = DEM or or etc. -b DAC -b DAC -b DAC -b DAC -b DAC -b DAC -b DAC -b DAC -b DAC -b DAC Chosen pseudo-randomly once per sample period e DAC [ n] α and β are independent of x and pseudo-random choice e DAC depends on pseudo-random choice The DEM : A Closer Look DEM S 3 S seg 8 S S S S 3 S S 4 S 5 s n s n s n seg[ ] 3[ ] 5[ ] where: xkr [ n] xin[ n] x [ n] s [ n] kr kr S kr xkr [ n] skr [ n] if xkr [ n] even and skr [ n] else x [ n] 8 s [ n] in S seg sseg[ n] if xin[ n] even and sseg[ n] else seg s seg and s jk are independent pseudo-random ± sequences s seg and s jk are known by the digital logic 5

6 The DEM : Example One example set of choices for x = : DEM S seg 8 5 S 3 3 S S S S S 3 S 4 S 5 where: xkr [ n] x [ ] in n x [ n] s [ n] kr kr S kr xkr [ n] skr [ n] if xkr [ n] even and skr [ n] else x [ n] 8 s [ n] in S seg sseg[ n] if xin[ n] even and sseg[ n] else seg Structure of the DAC Noise -b DAC x DEM -b DAC -b DAC -b DAC yn [ ] xn [ ] edac[ n] Known independent pseudo-random ± Sequences Can Show: e e DAC is like a spread spectrum signal: n s n s n DAC k r kr sg e seg k r Unknown constants that depend only on the -b DAC mismatches Δ kr and Δ seg are the unknown (constant) message signals s kr and s seg are the known spreading codes 6

7 The DNC Technique The DAC noise directly corrupts the uncorrected ADC output: V in 6 9 s -7 Uncorrected ADC Output DNC/ GEC Logic Digitized Residue 6 The DNC logic is a spread spectrum receiver that: correlates the digitized residue against s kr and s seg to estimate Δ kr and Δ seg uses the DAC noise equation to cancel e DAC First Calibration Logic - DNC Digitized Residue Level Requantizer 3 PN Generator Dithered Requantizer s 3 Average 3 Correlator # s seg Average 3 Correlator #9 3 seg s 3 s seg DNC Logic 3 s 3 seg s seg GEC Logic 9 simple spread-spectrum receivers Requantization: reduces DNC logic size dithered to avoid corrupting correlations y GEC y DNC Error Estimate 7

8 Conventional PADC: Interstage Gain Error Flash ADC 8 -b Digitized Residue s -7 Signal Quantization Noise ε = interstage gain error Causes imperfect cancellation of ADC quantization noise Reduces SFDR and SNDR The GEC Technique () Flash ADC DEM -b Digitized Residue s -7 Signal Quantization Noise GEC Signal A pseudo-random ±Δ/4 sequence is introduced to the DAC path It occupies a portion of error headroom created by redundancy It follows the same path and sees the same gain as the quantization noise 8

9 The GEC Technique () Average of: Flash ADC Ideas behind GEC Technique: DEM -b (Digitized Residue) Digitized Residue s -7 Signal Quantization Noise GEC Signal Correction Factor (Digized Residue) / (Correction Factor) = First Calibration Logic -GEC Digitized Residue Level Requantizer 3 DNC Logic PN Generator y DNC Dithered Requantizer r gec pause Average 3 Correlator ( ) GEC Logic y GEC Error Estimate Instead of dividing the digitized residue by the gain estimate: a linear Taylor series approximation is used: ( ) the resulting correction signal is added directly to output Any linear contribution to gain error is corrected! 9

10 Circuit-Level Details V in+ V in Passive Sampling Network Passive Sampling Network Distributed Input Sampling Network Flash ADC 8 r gec Thermometer to Binary 4 DEM 8 s 8 b k c k PRN Generator To DNC/ GEC Logic -b 9 4 Residue Amplifier V out+ V out y out Distributed input sampling 4 Separate input and DAC sampling capacitors DNC&GEC => no special attention to cap matching 4. I. Mehr and L. Singer IEEE Journal of Solid State Circuits March Bootstrapped Switch Circuitry.8V C Track Switch Off Charge C Sample Thick-Oxide Devices V in Sampling Switch Modified version of circuitry presented in [5] Thick-oxide devices to avoid exceeding technology limits Uses a single.8v clock 5. M. Dessouky and A. Kaiser IEE Electronics Letters January 999 V out

11 Residue Amplifier ().8V.8V.8V.8V P V cmoo V bp V CMFB V bp3 P V inn V outp V bp P V cmoi P OTA P R c C c V outp V inn V inp V bn V inp V outn P P V cmoo V bn Closed loop gain of 4 Two-stages for high gain and wide output swing Residue Amplifier () Conventional PADC: Open-loop gain requirement >db Gain-boosting is typically required Simulated gain: >5dB with gain-boosting 85dB without Prototype IC: Gain-boosting with enable/disable circuitry is included As expected measured PADC performance with GEC enabled and gain-boosting disabled does not change! Scaled down once and used in the remaining stages without further scaling

12 DEM and GEC Adder Implementation Control logic block presets paths Critical path is T-gate delay & adder implemented together to minimize latency 8 y FADC r gec b k DEM 8 s 8 c k PRN Generator To DNC/ GEC Logic 9 8 y FADC MSB 9 s r gec T-gate delay Layer of 7 T-gates 7 Control Logic (Timing not critical) f z LSB Segment Switch NAND-gate delays b 7 b 6 b 5 b 4 b 3 b b b c c DAC Sampling Network of 8 b k 8 -b c k V o+ V o- V ref+ V ref- P P P P C d V cmoi C d P P Pb k Pb k Pb k Pb k V o+ To Residue Amplifier V o- of From DEM To Residue Amplifier V ref+ P P P P C d / V cmoi C d / P P Pc k Pc k Pc k Pc k V ref- -b : 8 step-size Δ step-size Δ/ References are double sampled Capacitor sizes halved Reduces kt/c noise

13 Process Layout and Packaging Overview Process.8μm CMOS MiM capacitors deep Nwells thick-oxide devices low- V T devices Layout Deep Nwells and multiple supply domains No special attention to capacitor matching ESD protection circuitry on all pads Packaging 56-pin QFN package with exposed die paddle Down-bonding of all grounds to exposed paddle Double-bonding of critical supply pins Measured SFDR and THD vs. Input Frequency SFDR db 9 88 THD MHz DNC and GEC enabled 3

14 Measured PSD with a 9 MHz Input db -6 db MHz MHz With DNC and GEC disabled With DNC and GEC enabled SFDR 64.8 db SFDR 9.9 db SNDR 54.7 db SNDR 7.6 db Measured DNL (f in = MHz ) DNL (LSB)) Code x 4 DNL (LSB)) Code x 4 With DNC and GEC disabled DNL =.3 LSB With DNC and GEC enabled DNL =.5 LSB 4

15 Measured INL (f in = MHz ) INL (LSB) INL (LSB) Code x Code x 4 With DNC and GEC disabled With DNC and GEC enabled INL = 5 LSB INL =.5 LSB Fabrication and Measurement Summary Resolution Sample Rate Input Voltage Range SFDR THD Peak SNR DNL INL SFDR Improvement with DNC and GEC enabled SNDR Improvement with DNC and GEC enabled Total Power 5 b 4 MHz.5 Vp-p differential 9 db 88 db 7 db.5 LSB.5 LSB > db > db 4 mw Analog Power 343 mw (.8 V) Digital Power 5 mw (. V) Output Drivers Power 6 mw (.8 V) Technology Die Size Package.8μm P6M CMOS 4mm x 5mm (including pads) 56-Pin QFN with ground downbonding 5

16 Die Photo Bias s -7 Clk Buff/Gen Digital Logic Serial Port Conclusion The silicon implementation of two digital signal processing background calibration techniques has been presented DNC to compensate for DAC mismatch noise GEC to compensate for interstage gain errors Together they drastically reduce analog circuit requirements required to achieve high performance They have been shown to be enabling components in a high-resolution pipelined ADC 6

17 Acknowledgements The authors are grateful to Erica Poole for digital schematic capture and verification Sudhakar Pamarti and Ashok Swaminathan for digital layout and technical advice Eric Fogleman for technical advice and Andrea Panigada for test board design and technical advice. 7