Materials in this course have been contributed by Fernando Medeiro, José M. de la Rosa, Rocío del Río, Belén Pérez-Verdú and

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1 CMOS Sigma-Delta Converters From Basics to State-of-the-Art Circuits and Errors Angel Rodríguez-Vázquez Barcelona, / Septiembre / 2010 Materials in this course have been contributed by Fernando Medeiro, José M. de la Rosa, Rocío del Río, Belén Pérez-Verdú and Angel Rodríguez-Vázquez 1

2 Overview of non-idealities - Ideal In-Band Error Power: 2 2L 1 π P Q B 2L (2 L+1) OSR - Actual In-Band Error Power: PT PQ PQ PTH PJ PHD... Finite Amplifier Gain Non-Linearities Thermal Noise Comparator Hysteresis Capacitor Mismatch Settling Errors Clock Jitter DAC Non-linearity among others 2

3 Overview of non-idealities Depending on the building-block: Fully-diff SC schematic of a 2nd-order M Clock: - Jitter Amplifiers: -Output swing -DC gain - Dynamic limitations (GB, SR) - Thermal and 1/f noise - Gain non-linearity Capacitors: -Mismatch - Non-linearity Switches: - Finite on-resistance - Thermal noise - Charge injection - Clock feedthrough - Non-linearity Comparators: -Hysteresis -Offset References: - Thermal and 1/f noise - Output impedance Multi-bit ADCs & DACs: -Gain error -Offset error - Non-linearity 3

4 Overview of non-idealities Depending on their effect: ERRORS DEGRADING NTF AMPLIFIER DC GAIN CAPACITOR MISMATCH INTEGRATOR SETTLING Amplifier GB Amplifier SR Switch R on Impact depends on topology Output PSD 4th order SINGLE-LOOP Ms Low sensitivity 3rd order CASCADE Ms Noise leakages Imperfect cancellation of low-order quantization errors 0.5/OSR 0.5 2nd order 1st order f/f s (log) 4

Overview of non-idealities Depending on their effect: ERRORS DEGRADING NTF MODELED AS ADDITIVE ERRORS AMPLIFIER DC GAIN CIRCUIT NOISE CAPACITOR MISMATCH Thermal noise (switches, opamps, refs) 1/f

5 Overview of non-idealities Depending on their effect: ERRORS DEGRADING NTF MODELED AS ADDITIVE ERRORS AMPLIFIER DC GAIN CIRCUIT NOISE CAPACITOR MISMATCH Thermal noise (switches, opamps, refs) 1/f noise (opamps, refs) INTEGRATOR SETTLING Amplifier GB CLOCK JITTER Amplifier SR DISTORTION Switch R on Non-linear amplifier gain Non-linear capacitors Impact depends on topology SINGLE-LOOP LOOP Ms Low sensitivity CASCADE Ms Noise leakages Imperfect cancellation of low-order quantization errors Non-linear settling Non-linear switches Front-end dominates Similar impact on different topologies 5

6 Integrator leakage Effect of amplifier gain on the integrator transfer function: Ideal SC integrator SC integrator considering amplifier finite gain g C C 1 2 Amplifier gain Shift of the pole from DC (z = 1) 6

7 Integrator leakage Effect on single-loop loop Ms: d ll -Ideally: -In practice: 2nd-order M Lth-order M: Quite insensitive to leakages ( 2, L-1 shaping) 7

8 Integrator leakage Effect on cascade Ms: M Mismatch between analog and digital filtering - Ideally: - In practice: low-order order leakages (L 1-1, L 2-1, ) 8

9 Integrator leakage Comparison of integrator leakage effect on 4th-order Ms (ideal) Sensitivity to int. leakages of cascades increases with OSR and L 1st-stage leakages dominate (L 1-1 shaping) 9

10 Capacitor mismatch Circuit primitive: Physical implementations: MOS cap Analog CMOS Digital CMOS Mixed CMOS 10

11 Capacitor mismatch Local and global errors in: Area Capacitance per Unit Area SC integrator t g C C 1 2 nc mc u u g g 1 1 n m C Cu u C ~ 0.05% 05% - 01% 0.1% using good quality caps and adequate layout strategies Centroid techniques 11

12 Capacitor mismatch Effect on single-loop loop Ms: - Ideally: 2nd-order M - In practice: Slight increase of error, but shaping is preserved 12

13 Capacitor mismatch Effect on cascade Ms: M - Ideally: - In practice: Mismatch between analog and digital it coeffs low-order leakages (L 1, L 2, ) 13

14 Capacitor mismatch Effect on cascade Ms: C = 0.5% C = 0.1% M M (OSR = 32) (OSR = 32) 14

15 Capacitor mismatch Effect on cascade Ms: Required C for 1-bit loss in DR Sensitivity to mismatch rapidly increases with: - Oversampling ratio (OSR) - Cascade order (L) 1st-stage leakages 1st stage leakages dominate (L 1 shaping) 15

16 Integrator incomplete settling The relationship between opamp input and output is nonlinear and dynamic Settling error A DC GB, SR Integrator temporal evolution Integrator temporal evolution error due to amplifier finite bandwidth slew-rate limitation Modulator output spectrum increase on the noise floor harmonic distortion due to slewing SNDR degradation 16

17 Integrator incomplete settling Integrator temporal evolution: [Rio00] Both integration and sampling dynamics considered 1 pole model + SR limitation in amplifiers All parasitic caps taken into account 17

18 Integrator incomplete settling Integrator temporal evolution: [Rio00] Linear Partial Full response slew GB i SR i 18

19 Integrator incomplete settling Integrator temporal evolution: [Rio00] GB i GB s SR i SR s 19

20 Integrator incomplete settling Integrator temporal evolution: [Rio00] 20

21 Integrator incomplete settling Effect of the amplifier GB: If only amplifier GB is considered (assuming no SR limitation) - Can be viewed as a systematic error in the integrator weight - Effect on Ms similar to a mismatch between analog and digital coeffs l - It causes low-order noise leakages in cascade Ms 21

22 Integrator incomplete settling Additional effect of the amplifier SR (+ GB): - Dominant linear dynamics are not mandatory in order to fulfill specs - SR can be traded for GB - It can be used to optimize the power consumption of amplifiers Non-linear dynamics cause distortion! SR at the front-end integ must be carefully tackled 22

23 Integrator incomplete settling Additional effect of the switches Ron (+ GB + SR): = 1 Input is sampled with an error Linear dynamics are slowed down Slew time shortens 23

24 Circuit noise Main noise sources in SC integrators: Switches Thermal noise Amplifiers Thermal and flicker noise References Thermal and flicker noise Sampling: Integration: Noise contribution ti of the switches (input-referred): Switches for sampling Aliased component [Fisc82] C S = 0.66pF f s = 70MHz 24

25 Circuit noise Main noise sources in SC integrators: Switches Thermal noise Amplifiers Thermal and flicker noise References Thermal and flicker noise Sampling: Integration: Noise contribution of the switches (input-referred): Switches for sampling Switches for integration 25

26 Circuit noise Noise contribution of the amplifier (input-referred): Thermal + Flicker Thermal component corner freq. Aliased component Flicker component Low-pass filtered version at the integ input: Folded tails are submerged into the aliased thermal noise Similar treatment for the references 26

27 Circuit noise Total noise PSD for the front-end integ: switches amplifier references Switches: - kt/c is the ultimate limitation on the converter resolution - It can only be decreased by increasing Cs and/or fs (it does not depend on Ron!) - x2 in fully-diff implementations (3-dB increase, but signal power is 6dB larger!) Amplifiers & References: - GBs should be as low as settling errors allow (reduces folding!) - 1/f contributions decrease with the corner frequency - Adequate techniques can be applied in low-freq apps: CDS, chopper, [Enz96] In-band error power due to circuit noise in the M 27

28 Circuit noise Effect of noise leakages and thermal noise on a 2-1 cascade 3rd-order shaping w/ Thermal noise 2nd-order shaping no shaping w/ Integ leakage Ideal 28

29 Circuit noise Effect of 1/f and thermal noise on the spectra of a 4th-order M (silicon results for several fs) Thermal components Be careful with Flicker models for transistors! Front-end amplifier needed redesign! Flicker component (1/f) 29

30 Clock jitter Sampling time uncertainty [Boser88]: Non-uniform sampling of the input If jitter is modeled as random: Ideal J = 0.1ns, f x = 125kHz J = 0.1ns, f x = 500kHz Error is larger, the larger input freq (wideband apps!) 30

31 Non-linearity of capacitors In an ideal capacitor: dq = Cdv In practice: dq = C(v)dv, with C being voltage-dependent v i Considering the effect of the sampling cap only [Bran97]: a 1 = 500ppm/V, a 2 = 500ppm/V 2 HD 3 = -94.0dB HD 3 = -89.9dB HD 3 = -89.8dB - Even-order distortion cancels w/ fully-diff - Non-linearity of sampling cap dominates - Valid for weak non-linearities (MOS caps are very non-linear!) 31

32 Non-linear Amplifier Gain Actual amplifier gain depends on output voltage: Amplifier gain, db A DC Output voltage, V A DC = 500, 1 = 10%/V (single-ended M) [Yin94] - Increasing A DC helps a lot! - A DC at the front-end larger than noise leakages require 32

33 Non-linear settling SR can trade for GB in the integrator settling, but non-linear dynamics cause distortion: SR at the front-end larger than settling requires 33

34 Non-linear switch resistance Switches exhibit a finite R ON which is also non-linear: R ON, p R 1 ON, n R ON, n R ON, p W k' n ( V L n 1 W k' p ( v L p DD I v V V I Tp ) Tn ) R ON,eq V DD 0 VTp VDD VTn v I R R // R ON,eq ON, n ON, p Non-linear sampling [Geer02]: Alternative switch sizings Numerically solved - Distortion is dynamic (increases with input freq!) - Front-end switch dominates - R ON at the front-end smaller than settling requires - Very important in low-voltage! Most suited sizing i depends d on parasitics, Vref/Vsupply, 34

1-bit DAC Inherently linear Offset Attenuated

similarly to quantization error [Boser88] P h

errors on a 2nd-order 3-bit M Multi-bit ADC

Non-linearity directly added to the input!

35 Comparators and multi-bit quantizers Single-bit Ms: Multi-bit Ms: Comparator: 1-bit DAC Inherently linear Offset Attenuated by the integrator DC gain Hysteresis Shaped similarly to quantization error [Boser88] P h 4h 2 2L π (2 L+1) OSR 2L 1 Effect of DAC errors on a 2nd-order 3-bit M Multi-bit ADC Errors attenuated/shaped Multi-bit DAC Non-linearity directly added to the input! [Mede99]: σ D INL B LSB DEM techniques Dual quantization 35

36 Case study A2.5-V Cascade SDM in CMOS 0.25um for ADSL/ADSL w/ dual quantization Two different amplifiers: 2-stage OA in the 1st stage, and 1-stage OA in 2nd and 3rd stages. Standard CMOS switches (no clock-boosting). Only 2-branch integrators and 2x16 unit capacitors (MiM). Comparators: regenerative latch + preamplification stage. 3-bit quantizer in the last stage: Resistive-ladder DAC (no calibration). Flash ADC: Static differential input stage + latched comparators. Power-down control. 36

37 Case study - Blocks Specs Blocks Specs EQUATION DATABASE Typical Worst Case Quantization noise -88.1dB -86.2dB MODULATOR Topology Oversampling ratio Reference voltage Clock Coc frequency Clock jitter Sampling capacitor 2-1-1(3b) 1(3b) V 70.4MHz 15ps (0.1%) 0.66pF Ideal Corner analysis: -90.3dB Cap. sigma (MiM, 1pF) 0.05% FRONT-END DC gain leakage Fast and slow devices models -99.8dB Cap. tolerance ±20% INTEGRATOR Cap. mismatch Temperature leakage range: [-40ºC, +110ºC] Bottom parasitic cap. 1% -95.4dB -89.4dB ( C = 0.05% ±5% 0.1%) variation in the 2.5-V supply Switch on-resistance 150 DAC error -96.4dB DC gain 3000 (70dB) GB (1.5pF) 265MHz Thermal noise -84.8dB -82.2dB AMPLIFIER Slew rate (1.5pF) 800V/ s kt/c noise -88.1dB -86.0dB Output swing ±1.8V Amplifier noise -87.5dB -84.5dB Input equivalent noise 6nV/sqrt(Hz) Clock jitter In-band error power Dynamic range -82.3dB 82.8dB (13.5bit) -90.1dB -80.3dB 80.8dB (13.1bit) COMPARATORS 3-bit QUANTIZER Hysteresis Offset Resolution time DAC INL 20mV ±10mV 3ns 0.5%FS 37

38 Case study MODULATOR Topology Oversampling ratio Reference voltage 2-1-1(3b) V Typical Worst Case Clock frequency Clock jitter 70.4MHz 15ps (0.1%) Quantization noise -88.1dB -86.2dB Sampling capacitor 0.66pF Ideal DC gain leakage Cap. mismatch leakage ( C = 0.05% 05% 0.1%) -90.3dB -99.8dB -95.4dB -89.4dB FRONT-END INTEGRATOR Cap. sigma (MiM, 1pF) Cap. tolerance Bottom parasitic cap. Switch on-resistance 0.05% ±20% 1% 150 DAC error -96.4dB Thermal noise -84.8dB -82.2dB kt/c noise -88.1dB -86.0dB AMPLIFIER DC gain GB (1.5pF) Slew rate (1.5pF) Output swing 3000 (70dB) 265MHz 800V/ s ±1.8V Amplifier noise -87.5dB -84.5dB Input equivalent noise 6nV/sqrt(Hz) Clock jitter -90.1dB Hysteresis 20mV In-band error power -82.3dB -80.3dB COMPARATORS Offset ±10mV Dynamic range 82.8dB (13.5bit) 80.8dB (13.1bit) 3-bit QUANTIZER Resolution time DAC INL 3ns 0.5%FS 38

Case study - Integrator Dynamics Integrator

5f s is ideally enough to limit settling

clock-boosting) (assuming that 85% of the

large enough to let the linear dynamic to

39 Case study - Integrator Dynamics Integrator Dynamics GB > 2.5f s is ideally enough to limit settling errors (this architecture w/ OSR = 16). Switch on-resistance slows down the effective amplifier response: R on ~ 150 requires just GB > 3.2f s Standard switches GB = 265MHz (no clock-boosting) (assuming that 85% of the clock cycle is useful) Slew rate must be large enough to let the linear dynamic to correctly settle. 6.5 SR = 800V/ s Partially slew-rate limited operation of the front-end integrator introduces distortion. 39

40 Case study - Amplifiers INTEG. 11 INTEG. 2 INTEG. 3 INTEG. 4 Unit capacitor 0.66pF 0.45pF 0.45pF SC CMFB nets DC gain (70dB) (70dB) 600 (56dB) pmos input scheme GB (1.5pF) 265MHz 265MHz 210MHz Slew rate (1.5pF) Output swing 800V/ s 800V/ s ±1.80V ±1.80V 350V/ s ±1.60V Cancelled body effect (substrate noise coupling) Smaller 1/f noise Input equivalent noise 6nV/sqrt(Hz) 50nV/sqrt(Hz) OPA OPB 40

41 Case study - Amplifiers INTEG. 1 INTEG. 2 INTEG. 3 INTEG. 4 Unit capacitor 0.66pF 0.45pF 0.45pF SC CMFB nets DC gain 3000 (70dB) 600 (56dB) pmos input scheme e GB (1.5pF) Slew rate (1.5pF) 265MHz 800V/ s 210MHz 350V/ s Cancelled body effect (substrate noise coupling) Output swing ±1.80V ±1.60V Smaller 1/f noise Input equivalent noise 6nV/sqrt(Hz) 50nV/sqrt(Hz) OPA 2-stage amplifier Telescopic 1st stage 2-path compensation DC gain GB (1.5pF) PM (1.5pF) SR (1.5pF) Output swing Input eq. noise Input capacitance Power consumption Typical 78.6dB 446.8MHz 64.0º 1059V/ s ±2.09V 5.1nV/sqrt(Hz) 126fF 17.2mW Worst Case 73.5dB 331.5MHz 57.9º 883V/ s ±1.86V 5.5nV/sqrt(Hz) 129fF 19.4mW 41

42 Case study - Amplifiers INTEG. 1 INTEG. 2 INTEG. 3 INTEG. 4 Unit capacitor 0.66pF 0.45pF 0.45pF SC CMFB nets DC gain 3000 (70dB) 600 (56dB) pmos input scheme GB (1.5pF) Slew rate (1.5pF) 265MHz 800V/ s 210MHz 350V/ s Cancelled body effect (substrate noise coupling) Output swing ±1.80V ±1.60V Smaller 1/f noise Input equivalent noise 6nV/sqrt(Hz) 50nV/sqrt(Hz) OPB folded-cascode amplifier DC gain GB (1.5pF) PM (1.5pF) SR (1.5pF) Output swing Input eq. noise Input capacitance Power consumption Typical 58.0dB 393.5MHz 70.3º 377V/ s ±1.97V 4.1nV/sqrt(Hz) 300fF 6.6mW Worst Case 56.8dB 331.7MHz 67.7º 373V/ s ±1.72V 5.1nV/sqrt(Hz) 343fF 6.9mW 42

43 Case study - Switch ON-Resistance Slow-down of the integrators dynamics Incomplete sampling (RC time constant) Dynamic distortion (front-end integrator) R on ~ 150 Standard CMOS switches nmos: 8.5/0.25 pmos: 36.5/0.25 No clock-boosting No low-vt transistors 43

44 Case study - Switch ON-Resistance Dynamic distortion evaluated through electrical simulation 366kHz Sinewave input DMT input 44

Case study - MiM Capacitors CMOS tech with mixed-signal

1% assumed for 6- design) Bottom plate parasitic 1% Helps to

spread ±20% Integrators weights: Front-end integ, 0.

45 Case study - MiM Capacitors CMOS tech with mixed-signal facilities M5 thin oxide Thin oxide between M4 metal 4 and metal 5 TOP BOTTOM M3 Cap. matching 0.05% (1pF) Very good matching (0.1% assumed for 6- design) Bottom plate parasitic 1% Helps to limit the capacitive load to integrators Cap. spread ±20% Integrators weights: Front-end integ, 0.66pF: 27 m x 27 m Remaining integs, 0.45pF: 22 m x 22 m Also MiM caps in OPA, in the SC CMFB nets, and in the anti-aliasing aliasing filter 45

46 Case study - Quantizers Comparator Pre-amp + Regenerative latch + SR latch (Different supplies) Hysteresis Resolution time, LH Input capacitance V 3.9ns 100fF Offset Resolution time, HL Power consumption 6.3mV 2.8ns 0.3mW 3-bit Quantizer Resistive-ladder DAC 700- ladder between references +2V/+0.5V (14x50, 3.21mW) Unsalicided n+ poly used in resistors References obtained from the on-chip analog supply Flash ADC Static input scheme (no caps) Reduces capacitive load to 4th integrator Saves silicon area Extra differential pair in comparators 46

Case study - Layout & Prototyping CMOS 0.25 m 2.

Dedicated analog, mixed, and digital supplies Guard

among analog and digital blocks Layout symmetry and

distributing the clock signals Extensive on-chip

47 Case study - Layout & Prototyping CMOS 0.25 m 2.78mm 2 w/o pads 44-pin plastic QFP 4-layer PCB Dedicated analog, mixed, and digital supplies Guard rings with dedicated pad/pin Increased distance among analog and digital blocks Layout symmetry and common-centroid techniques Shielded bus for distributing the clock signals Extensive on-chip decoupling Pad ring divided blocking cells Multiple bonding techniques 47

48 Case study - Experimental results 160kHz THD = -87dB SFDR = 90dB Part of a commercial modem In mass production (STMicroelectronics) 48

49 References [Boser88] B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation Analog-to-Digital Converters. IEEE Journal of Solid-State Circuits, vol. 23. pp , December [Bran97] [Enz96] B. Brandt, P.F. Ferguson, and M. Rebeschini, Analog Circuit Design of Σ ADCs, Chapter 11 in Delta-Sigma Data Converters: Theory, Design and Simulation (S.R. Norsworthy, R. Schreier, and G.C. Temes, Editors). IEEE Press, C.C. Enz and G.C. Temes, Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization. Proceedings of the IEEE, vol. 84, no. 11, pp , November [Fisc82] J.H. Fischer, Noise Sources and Calculation Techniques for Switched Capacitor Filters. IEEE Journal of Solid-State Circuits, vol. 17, no. 4, pp , August [Geer02] Y. Geerts, M. Steyaert, and W. Sansen, Design of Multi-Bit Delta-Sigma A/D Converters. Kluwer Academic Publishers, [Mede99] F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez, Top-Down Design of High-Performance Modulators. Kluwer Academic Publishers, [Rio00] [Yin94] R. del Río, F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez, Reliable Analysis of Settling Errors in SC Integrators: Application to Σ Modulators. IEE Electronics Letters, vol. 36, no. 6, pp , March G. Yin and W. Sansen, A High-Frequency and High-Resolution Fourth-Order Σ A/D Converter in BiCMOS Technology. IEEE Journal of Solid-State Circuits, vol. 29, pp , August More details on errors and case study [Rio06] R. del Río, F. Medeiro, B. Pérez-Verdú, J.M. de la Rosa, and A. Rodríguez-Vázquez, CMOS Cascade Sigma- Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design. Springer,

Basic Concepts and Architectures

CMOS Sigma-Delta Converters From Basics to State-of of-the-art Basic Concepts and Architectures Rocío del Río, R Belén Pérez-Verdú and José M. de la Rosa {rocio,belen,jrosa}@imse.cnm.es KTH, Stockholm,