Final Exam Spring 2012

Transcription

1 1 EE 435 Final Exam Spring 2012 Name Instructions: This is an open-book, open-notes, open computer exam but no collaboration either personal or electronic with anyone except the course instructor is permitted. All problems are equally weighted. On those problems that need technology parameters, assume you are working in a 0.5u CMOS process with process with n C OX =100 A/v 2 p C OX =30 A/v 2,V TNO =0.8V,V TPO = - 0.8V, C OX = =2fF/ 2, =0.01v -1, Cbdbot = 0.5fF/ 2, and Cbdsw = 2.5fF/. Problem 1 In the following amplifier, assume V DD is 5V,C L =1pF. a) Determine the power required to achieve a GB of 5MHz if V EB on all devices is 500mV. b) What is the voltage gain, A(s), of this op amp?(give this numerically) V DD M 3 M 4 V IN M 1 M 2 V IN C L V B2 M 9

2 2 Problem 2 Consider the design of a two-stage op amp driving a load of value C L. a) Give the circuit schematic of this op amp with a p-channel input telescopic cascode first stage with tail current bias and a current mirror load and a commonsource n-channel single-ended second stage with tail voltage bias. b) Give the voltage gain of this op amp in terms of the small signal model parameters of the devices.

3 3 Problem 3 The following circuit has been proposed as a 4-bit DAC. In this structure, all resistors in the R 1 band are the same, all resistors in the R 2 band are the same, all resistors in the R 3 band are the same, and all resistors in the R 4 band are the same. Likewise, all switch transistors are the same size. The Boolean control variables are assumed to have Boolean values of V H and V L. The inventor of this circuit made the following claims. 1. The circuit will perform as a 4-bit binary-coded DAC if the resistors in all bands are identical 2. The linearity of the DAC is not degraded because of the finite impedance of the switches. 3. The circuit will perform as a 4-bit binary-coded DAC even if the resistor values in band k differ from those in band m for any m and k (but they must remain identical within a band). 4. The circuit will perform as a 4-bit binary-coded DAC even if the resistors in any band are replaced with nonlinear devices provided the nonlinear devices in each band are identical. V XX R 1 Band R 2 Band R 3 Band R 4 Band VL b4 b3 b2 b1 R F VH b4 b3 b2 b1 Which of these claims are true? Substantiate your assessment with an appropriate justification.

4 4 Problem 4 The circuit shown has been proposed as a Quarter Circuit for building an operational amplifier. a) Draw, at the transistor level, a fully differential op amp based upon this Quarter Circuit. Use a tail current bias on this op amp. Show, in block diagram form, where a CMFB should be connected if a CMFB is needed. a) Determine the small-signal differential voltage gain A(s) (differential input divided by differential output) of the op amp in terms of the small-signal model parameters of the devices in the quarter circuit if driving a capacitive load of C L connected to ground on both outputs. V BB Q 1 V IN M 1

5 5 Problem 5 Consider the differential amplifier shown below where I T =1mA. Size the transistors M 1 and M 2 so that for a differential linear ramp input voltage of 250mV, the deviation in the output from linear is 1% (depicted below). V DD R R V ZZ 0.01VZZ V in+ M 1 M 2 V in- I T V in+ -V in mV

6 6 Problem 6 Consider a 14-bit pipelined ADC with a single-ended input and V REF =5V. If the input is a sinusoidal signal given by V IN =1+0.5sin1000t, determine the signal to noise ratio of the quantized output signal. V IN Pipelined ADC REF 14 5V

7 7 Problem 7 Consider the switched-capacitor circuit shown below. The switches are clocked with the switching sequence shown below where a switch is closed if the controlling signal ϕ k is high and open if ϕ k is low. Assume the inputs V IN1 and V IN2 are constant for t 1 < t < t 1 +T. Determine the output voltage at the end of phase ϕ 2. φ 2 C2 φ 1 C 1 V IN1 φ 1 V IN2 φ 2 φ 1 φ 1 φ 2 T t 1 t 1 +T

8 8 Problem 8 A periodic nearly sinusoidal signal was coherently sampled 4096 times (uniformly spaced samples) at a sampling rate of 100KHz with an ideal ADC over an integral number of periods of the input signal to obtain the time-domain sequence <x(kt>, k= The DFT what then taken of this sequence. The magnitude of the terms of this DFT can be represented with the sequence <X(i)>, i= Assume all terms in the magnitude sequence are below -300dB except 4 terms and these are X(1)=-20dB X(14)=0DB X(27)=-50dB X(40)=-60dB a) Determine the THD of the ADC b) Determine the SFDR of the ADC c) Determine the number of periods of the input signal that were sampled d) Determine the frequency of the input signal