EE 435 Homework 4 Spring 2018 (Due Wednesday Friday Feb 28)

Transcription

1 EE 435 Homework 4 Spring 2018 (Due Wednesday Friday Feb 28) In the following problems, if reference to a semiconductor process is needed, assume processes with the following characteristics: CMOS Process ncox=350 A/v 2 pcox=70 A/v 2, VTNO=0.5V, VTPO= - 0.5V, COX=8.5fF/ 2, n p= 0.01V -1, and V For a bipolar Process -- JS=10-15 A/ 2, β=100 and VAF=150V. Problem 1 Design an amplifier using the architecture shown below in the TSMC 0.18u process for a dc gain of 35dB and a GB of 20MHz. How much power is required to obtain this performance? How do W/L and the power change if the GB must be increased to 40MHz? Assume VDD=2.5V, VSS=-2.5V and CL=5pF. V DD I DQ M 1 C L V OUT V in V XX V SS Problem 2 It can be shown that if an open-loop amplifier A(s) is second-order lowpass the relationship between the pole Q and the phase margin φm is given by the expression Derive this relationship. Q cos(φ sin(φ M M ) ) Page 1 of 8

2 Problem 3 Consider a two-stage Miller-compensated Op Amp with p-channel inputs and an n-channel input on the second stage with a tail-current biased first stage and a tailvoltage biased second stage. Assume this Op Amp is to be internally Miller compensated using the RHP zero compensation. Use a current-mirror connected counterpart circuit. Neglect any loading of the β network on the open-loop amplifier. (this amplifier is depicted in the figure below). a) Give expressions for the dc gain and the GB of the op amp in terms of the smallsignal model parameters of the transistors. b) Give an expression for the open-loop gain A(s) in terms of the small-signal model parameters of the transistors c) Give an expression for the feedback gain AFB(s) for a noninverting feedback amplifier using this op amp. d) Give an expression for the compensation capacitor for a noninverting feedback amplifier in terms of the Q of the complex conjugate poles. e) Give an expression for the dc gain and the GB of the op amp in terms of the practical design parameters. The practical parameters should be the excess bias voltages of the transistors, the power P, and the parameter θ which is the fractional portion of the power that is allocated to the second stage. Common Source Current Mirror Differential Input Single-Ended Input Differential Output Single-Ended Output Stage 1 Tail Voltage Bias Tail Current Bias Common Source Current Mirror Differential Input Single-Ended Input Differential Output Single-Ended Output Stage 2 Tail Voltage Bias Tail Current Bias Internally Compensated RHP Zero Compensaion Output Compensated LHP Zero Compensaion p-channel Input n-channel Input Page 2 of 8

3 Problem 4 Design a two-stage Miller-compensated Op Amp with p-channel inputs on a telescopic cascode first stage using a current mirror-connected counterpart circuit and an n-channel input on the second stage. The first stage should use a tail-current bias and the second stage should use a tail-voltage bias. This should be designed in the TSMC 0.18µm CMOS process. Assume the total load capacitance is CL=1pF. In this design assume a supply voltage of 1.8V and an excess bias voltage of 150mV on all transistors. Compensate this operational amplifier (using the RHP zero Miller compensation) for a pole Q of 0.5 when connected in a unity gain configuration. Use a current-mirror connected counterpart circuit. Give the dimension of all transistors used in your design. Problem 5 Determine the slew rate of the telescopic cascode amplifier shown below V DD M 5 M 6 V DD M 7 M 8 V OUT V B3 M 3 M 4 C L I B V IN M 1 M 2 V IN V B5 I T M 12 M 11 Current Mirror Bias V SS Problem 6 If the amplifier in Problem 5 is designed so that the excess bias of all transistors is 0.3V with VDD=2.5V, and VSS=-2.5V and the power dissipation is 25uW, a) Determine the ac voltage gain b) Determine all of the natural design parameters for this amplifier c) Determine the GB if CL=2pF d) Determine the SR if CL=2pF Problem 7 Consider an amplifier with two inputs VIN1 and VIN2. If VIN1=.01sin1000t and VIN2= sin1000t, the output was 5sin1000t. When the inputs were VIN1=0.01sin1000t and VIN2= sin1000t the output was 4sin1000t. Determine a) The common-mode and difference-mode inputs for the first set of inputs b) Determine the common-mode gain, AC, and the difference mode gain, AD c) Determine the CMRR (CMRR=AD/AC) Page 3 of 8

4 Problem and 3.5 of Martin and Johns Problem and 4.12 of Martin and Johns Problem and 4.22 of Martin and Johns Page 4 of 8

5 MOSIS WAFER ACCEPTANCE TESTS RUN: T68B (MM_NON-EPI) VENDOR: TSMC TECHNOLOGY: SCN018 FEATURE SIZE: 0.18 microns Run type: SKD INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of MOSIS test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar measurements on a selected wafer are also attached. COMMENTS: DSCN6M018_TSMC TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS MINIMUM 0.27/0.18 Vth volts SHORT 20.0/0.18 Idss ua/um Vth volts Vpt volts WIDE 20.0/0.18 Ids pa/um LARGE 50/50 Vth volts Vjbkd volts Ijlk <50.0 <50.0 pa K' (Uo*Cox/2) ua/v^2 Low-field Mobility cm^2/v*s COMMENTS: Poly bias varies with design technology. To account for mask bias use the appropriate value for the parameters XL and XW in your SPICE model card. Design Technology XL (um) XW um) SCN6M_DEEP (lambda=0.09) thick oxide SCN6M_SUBM (lambda=0.10) thick oxide FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS Vth Poly >6.6 <-6.6 volts PROCESS PARAMETERS N+ P+ POLY N+BLK PLY+BLK M1 M2 UNITS Page 5 of 8

6 Sheet Resistance ohms/sq Contact Resistance ohms Gate Oxide Thickness 41 angstrom PROCESS PARAMETERS M3 POLY_HRI M4 M5 M6 N_W UNITS Sheet Resistance ohms/sq Contact Resistance ohms COMMENTS: BLK is silicide block. CAPACITANCE PARAMETERS N+ P+ POLY M1 M2 M3 M4 M5 M6 R_W D_N_W M5P N_W UNITS Area (substrate) af/um^2 Area (N+active) af/um^2 Area (P+active) 8232 af/um^2 Area (poly) af/um^2 Area (metal1) af/um^2 Area (metal2) af/um^2 Area (metal3) af/um^2 Area (metal4) af/um^2 Area (metal5) af/um^2 Area (r well) 920 af/um^2 Area (d well) 582 af/um^2 Area (no well) 137 af/um^2 Fringe (substrate) af/um Fringe (poly) af/um Fringe (metal1) af/um Fringe (metal2) af/um Fringe (metal3) af/um Fringe (metal4) af/um Fringe (metal5) 55 af/um Overlap (N+active) 895 af/um Overlap (P+active) 737 af/um CIRCUIT PARAMETERS UNITS Inverters K Vinv volts Vinv volts Vol (100 ua) volts Voh (100 ua) volts Vinv volts Gain Ring Oscillator Freq. D1024_THK (31-stg,3.3V) MHz DIV1024 (31-stg,1.8V) MHz Ring Oscillator Power D1024_THK (31-stg,3.3V) 0.07 uw/mhz/gate DIV1024 (31-stg,1.8V) 0.02 uw/mhz/gate Page 6 of 8