1. (2pts) What is the purpose of the buried collector in a bipolar process?

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1 EE 330 Exam 2 Fall 2013 Name Instructions: This is a 50-minute exam. Students may bring 2 pages of notes (front and back) to this exam. The points allocated to each question and each problem are as indicated. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If references to semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; n C OX =100 A/v 2 p C OX = n C OX /3,V TNO =1V,V TPO = - 1V, V -1/2,, ϕ=0.6v, C OX =2fF/ 2, and = 0 If reference to a bipolar process is made, assume this process has key process parameters J S =10-15 A/ 2, β=100 and V AF =. The ratio of Boltzmann s constant to the charge of an electron is k/q= 8.61E-5 V/K. If any other process parameters are needed, use the process parameters associated with the process described on the attachments to this exam. Specify clearly what process parameters you are using in any solution requiring process parameters. Also attached to this exam is a table that has information about large and small signal models of devices. 1. (2pts) What is the purpose of the buried collector in a bipolar process? 2. (2pts) Why is the n-type layer in a BJT process that forms the collector created by the epitaxial process rather than diffused into the surface of a lightly doped p- substrate? 3. (2pts) In an example circuit discussed in class where a MOS transistor was replaced with a BJT transistor in a fixed circuit structure and where key characteristics such as the load resistor and the bias currents were the same, it was observed that the small-signal gain of the BJT circuit was much larger than that of the corresponding MOS circuit. What is the major reason for this? 4. (2 pts) What is the major processing step in a bipolar process that makes the size of the bipolar transistor so big? Page 1 of 10

2 5. (2pts) We observed that there is a parasitic SCR in a standard BULK CMOS process and this parasitic SCR can cause a circuit to fail or self-destruct if it is turned on. What is done to prevent this from happening? 6. (2pts) Tyristors have the ability to switch very large currents yet the power dissipation of the thyristor is quite small. Why is the power dissipation quite small even when very large currents are flowing? 7. (2pts) What mathematical theorem was used to obtain a linear relationship between the input and output of a highly nonlinear amplifier when the input signals are small? 8. (2pts) The efficiency of converting minority carriers that enter the base region of a BJT into collector current was characterized by the parameter α and this is one of the most important properties of a BJT yet the parameter α did not appear in the device models. What model parameter was used in the model of the BJT that captures the effects of α on the performance of the transistor? 9 (2pts) What is the difference between an enhancement mode and a depletion mode n-channel transistor? 10 (2pts) What parameter in a JFET model corresponds to the threshold voltage in the model of a MOSFET? Page 2 of 10

3 Problem 1 (16 pts) Give the schematic of the small signal circuit corresponding to the amplifier structure shown below. Assume the MOS transistor is operating in the saturation region, the BJT is operating in the forward active region, and the capacitor is large. 10V W=1µ L=4µ M 1 10K R B V OUT C A E =100µ 2 Q 1 V IN Page 3 of 10

4 Problem 2 (16 pts) For the circuit shown, assume the transistor is characterized by β=50. a) Determine R B so that the quiescent collector current is 7mA b) Determine the quiescent collector voltage V C with the value of R B determined in part a). c) With the value of R B determined in part a), determine the quiescent output voltage if the β of the transistor is increased from 50 to V R B 1K V C V OUT V IN C 1 C 2 Q 1 A E =100u 2 β=50 1K Page 4 of 10

5 Problem 3 (16 pts) Determine W in the following circuit so that the quiescent value of V OUT is 3V. The length of the transistor is 5µ. 6V V IN (t) 50K C 50K 2K V OUT L=5µ 1K Page 5 of 10

6 Problem 4 (16 pts) Consider the following circuit. Assume the OpAmp is ideal. The waveforms V AC is the 60Hz line voltage. Assume the triac has a gate trigger voltage of 2Vand that the relationship between the gate current and the gate voltage of the traic is as shown on the I G :V G plot on the right. a) Obtain an expression for and plot V LOAD for one period of V AC b) Identify the quadrants that the triac is operating in. V AC 9K I F R L =25 V LOAD I G 10K 1K V G 2V V AC 170V t Page 6 of 10

7 Problem 5 (16 pts) The layout of a CMOS circuit is shown. On the right and bottom sides is a scale for the layout with a spacing between the scale lines of 1µ. All layers are labeled except Metal 1 which is shown with dashed lines. n-select and p-select are not shown but can be inferred from the layout. On the left side are four electrical connections to Metal 1 designated at 6V, V OUT, 2.5V, and the ground symbol. a) Give the circuit schematic including device sizing b) Determine V OUT N-well 6V POLY 1µ V OUT Active POLY 2.5V 1µ Page 7 of 10

8 TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS MINIMUM 3.0/0.6 Vth volts SHORT 20.0/0.6 Idss ua/um Vth volts Vpt volts WIDE 20.0/0.6 Ids0 < 2.5 < 2.5 pa/um LARGE 50/50 Vth volts Vjbkd volts Ijlk <50.0 <50.0 pa Gamma V^0.5 K' (Uo*Cox/2) ua/v^2 Low-field Mobility cm^2/v*s COMMENTS: XL_AMI_C5F FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS Vth Poly >15.0 <-15.0 volts PROCESS PARAMETERS N+ACTV P+ACTV POLY PLY2_HR POLY2 MTL1 MTL2 UNITS Sheet Resistance ohms/sq Contact Resistance ohms Gate Oxide Thickness 144 angstrom PROCESS PARAMETERS MTL3 N\PLY N_WELL UNITS Sheet Resistance ohms/sq Contact Resistance 0.78 ohms COMMENTS: N\POLY is N-well under polysilicon. CAPACITANCE PARAMETERS N+ACTV P+ACTV POLY POLY2 M1 M2 M3 N_WELL UNITS Area (substrate) af/um^2 Area (N+active) af/um^2 Area (P+active) 2308 af/um^2 Area (poly) af/um^2 Area (poly2) 53 af/um^2 Area (metal1) af/um^2 Area (metal2) 32 af/um^2 Fringe (substrate) af/um Fringe (poly) af/um Fringe (metal1) af/um Fringe (metal2) 48 af/um Overlap (N+active) 206 af/um Overlap (P+active) 278 af/um Page 8 of 10

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