EE 435 Homework 4 Spring 2019 (Due Wednesday Friday Feb 20) (reposted corrected Problem 7)

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1 EE 435 Homework 4 Spring 2019 (Due Wednesday Friday Feb 20) (reposted corrected Problem 7) In the following problems, if reference to a semiconductor process is needed, assume processes with the following characteristics: CMOS Process ncox=350 A/v 2 pcox=70 A/v 2, VTNO=0.5V, VTPO= - 0.5V, COX=8.5fF/ 2, n p= 0.01V -1, and V For a bipolar Process -- JS=10-15 A/ 2, β=100 and VAF=150V. Problem 1 Design an amplifier using the architecture shown below in the TSMC 0.18u process for a dc gain of 35dB and a GB of 20MHz. How much power is required to obtain this performance? How do W/L and the power change if the GB must be increased to 40MHz? Assume VDD=2.5V, VSS=-2.5V and CL=5pF. I DQ M 1 C L V in V XX Problem 2 Consider the current-mirror op amp shown below. Assume VDD=1V and VSS=-1V. a) Size the devices if the excess bias of all transistors is to be 150 mv, the mirror gain of the two p-channel mirrors is to be 20, the n-channel mirror gain is 1, and the total power dissipation is 10mW. b) If the amplifier designed in part a) is driving a 10pF load, determine the dc voltage gain and the GB of this amplifier. c) Determine the transconductance gain of the amplifier designed in part a). Page 1 of 7

2 M 5 M 3 M 4 M 6 M 1 M 2 I T M 9 V B1 M 7 M 8 Problem 3 Consider the following circuit where the OTAs are assumed to be ideal. VOUT a) Obtain the transfer function Ts. VIN b) If gm1=gm2=10-8 A/V, C2=500pF and C1=50pF, plot the magnitude of the transfer function T(s) versus frequency g m1 V g OUT m2 C 1 C 2 Problem 4 Determine the slew rate of the telescopic cascode amplifier shown below Page 2 of 7

3 M 5 M 6 M 7 M 8 V B3 M 3 M 4 C L I B M 1 M 2 V B5 I T M 12 M 11 Current Mirror Bias Problem 5 If the amplifier in Problem 4 is designed so that the excess bias of all transistors is 0.3V with VDD=2.5V, and VSS=-2.5V and the power dissipation is 25uW, a) Determine the ac voltage gain b) Determine all of the natural design parameters for this amplifier c) Determine the GB if CL=2pF d) Determine the SR if CL=2pF Problem 6 Consider an amplifier with two inputs VIN1 and VIN2. If VIN1=.01sin1000t and VIN2= sin1000t, the output was 5sin1000t. When the inputs were VIN1=0.01sin1000t and VIN2= sin1000t the output was 4sin1000t. Determine a) The common-mode and difference-mode inputs for the first set of inputs b) Determine the common-mode gain, AC, and the difference mode gain, AD c) Determine the CMRR (CMRR=AD/AC) Problem 7 Problem 3.5 of Martin and Johns Problem 8 Problem 9 Problems 4.10 and 4.12 of Martin and Johns Problems 4.14 and 4.22 of Martin and Johns Problem 10 Identify one Current Mirror patent that has been issued in the past 2 years. Give the basic circuit structure in this current mirror patent and comment on what characteristics the inventors claim make it unique and useful. Page 3 of 7

4 MOSIS WAFER ACCEPTANCE TESTS RUN: T68B (MM_NON-EPI) VENDOR: TSMC TECHNOLOGY: SCN018 FEATURE SIZE: 0.18 microns Run type: SKD INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of MOSIS test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar measurements on a selected wafer are also attached. COMMENTS: DSCN6M018_TSMC TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS MINIMUM 0.27/0.18 Vth volts SHORT 20.0/0.18 Idss ua/um Vth volts Vpt volts WIDE 20.0/0.18 Ids pa/um LARGE 50/50 Vth volts Vjbkd volts Ijlk <50.0 <50.0 pa K' (Uo*Cox/2) ua/v^2 Low-field Mobility cm^2/v*s COMMENTS: Poly bias varies with design technology. To account for mask bias use the appropriate value for the parameters XL and XW in your SPICE model card. Design Technology XL (um) XW um) SCN6M_DEEP (lambda=0.09) thick oxide SCN6M_SUBM (lambda=0.10) thick oxide FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS Vth Poly >6.6 <-6.6 volts PROCESS PARAMETERS N+ P+ POLY N+BLK PLY+BLK M1 M2 UNITS Page 4 of 7

5 Sheet Resistance ohms/sq Contact Resistance ohms Gate Oxide Thickness 41 angstrom PROCESS PARAMETERS M3 POLY_HRI M4 M5 M6 N_W UNITS Sheet Resistance ohms/sq Contact Resistance ohms COMMENTS: BLK is silicide block. CAPACITANCE PARAMETERS N+ P+ POLY M1 M2 M3 M4 M5 M6 R_W D_N_W M5P N_W UNITS Area (substrate) af/um^2 Area (N+active) af/um^2 Area (P+active) 8232 af/um^2 Area (poly) af/um^2 Area (metal1) af/um^2 Area (metal2) af/um^2 Area (metal3) af/um^2 Area (metal4) af/um^2 Area (metal5) af/um^2 Area (r well) 920 af/um^2 Area (d well) 582 af/um^2 Area (no well) 137 af/um^2 Fringe (substrate) af/um Fringe (poly) af/um Fringe (metal1) af/um Fringe (metal2) af/um Fringe (metal3) af/um Fringe (metal4) af/um Fringe (metal5) 55 af/um Overlap (N+active) 895 af/um Overlap (P+active) 737 af/um CIRCUIT PARAMETERS UNITS Inverters K Vinv volts Vinv volts Vol (100 ua) volts Voh (100 ua) volts Vinv volts Gain Ring Oscillator Freq. D1024_THK (31-stg,3.3V) MHz DIV1024 (31-stg,1.8V) MHz Ring Oscillator Power D1024_THK (31-stg,3.3V) 0.07 uw/mhz/gate DIV1024 (31-stg,1.8V) 0.02 uw/mhz/gate Page 5 of 7