Problem 1. Final Exam Spring 2018 (Reposted 11p.m. on April 30)

Transcription

1 EE 435 Final Exam Spring 2018 (Reposted 11p.m. on April 30) Name Instructions: This is an open-book, open-notes exam. It is due in the office of the course instructor by 12:00 noon on Wednesday May 2. All problems are equally weighted. On those problems that need technology parameters, assume you are working in a 0.18µm CMOS process with key parameters ncox=350a/v 2, pcox=70a/v 2, VTNO=0.8V, VTPO= - 0.5V, COX=8fF/ 2, =0.01v -1, Cbdbot = 0.5fF/ 2, and Cbdsw = 2.5fF/. YOU MAY NOT CONSULT ANYONE ELSE ON SOLVING ANY PROBLEMS ON THE EXAM EXCEPT THE COURSE INSTRUCTOR OR THE TA FOR THE COURSE. You will be asked to make the following statement and provide your signature on the top of your solutions. All of the work on this exam is my own and I did not collaborate with anyone about this exam except possibly with the course instructor signature here Problem 1 The operational amplifier has been designed with VEB = 100mV for all transistors with a total power dissipation of 2mW when biased with a single 2V supply (i.e. VDD=2V). The load capacitor is CL=5pF and the length of all transistors is 2µm. a) Determine the GB of the op amp. b) Determine the width of all transistors. c) Express the dc gain in terms of the small-signal model parameters of the devices. d) Give a numerical value for the dc gain of this op amp. e) What is the 3dB bandwidth? f) What is the slew rate of the op amp? g) Obtain an expression for and plot the common-mode input range and the output range of this op amp V DD M 3 M 4 C L M 1 M 2 V B2 M 9 Page 1 of 9

2 Problem 2 Assume the input to a DAC is the digital sequence obtained by sampling the waveform Vi = sin500t + 1 once every 1usec and passing this sampled signal to the input of an ideal 12-bit ADC with VREF=2V. The DAC input is thus the output of the ideal ADC. Assume that the DAC output is kept at each level for the 1 usec until the next sample is obtained. a) What is the SNR of the signal at the output of the DAC? b) What would it be if Vi = 0.5sin100t + 1? Page 2 of 9

3 Problem 3 A standard SAR ADC is shown below along with a simple dynamic comparator. It is well known that the dynamic comparators are vulnerable to a large offset voltage. Assume a new engineer proposed a new SAR ADC architecture the will take advantage of the offset of the dynamic comparator to eliminate the DAC in the SAR ADC. The engineer termed this new structure a DAC-less SAR ADC and the comparator an Offset Comparator. The proposed structure is shown below. It was argued that by adding additional offset that can be controlled by a Boolean signal, the DAC can be eliminated by making the trip-point of the comparator dependent upon the output of the SAR Controller. By appropriately adjusting the sizes of the offset transistors, MOS1 MOSn, the trip point of the comparator can be set at an arbitrary digitally controlled value. It was also argued that the common-mode input of the comparator is now fixed and that the large area normally required of the DAC can be dramatically reduced by eliminating the DAC completely! Make an assessment about whether the DAC-less SAR ADC will work as a SAR ADC and, if so, if this new solution is practical. Sample Hold C LK M 5 V DD M 3 M 4 M 6 _SH M 1 M 2 V DAC DAC n DAC Controller M 7 Standard SAR ADC and basic dynamic comparator Sample Hold C LK M 5 V DD M 3 M 4 Offset Block M 6 d1 d2 dn n MOS1 MOS2 MOSn M 1 M 2 n SAR Controller M 7 DAC-less SAR ADC and Offset Comparator Page 3 of 9

4 Problem 4 a) Give a circuit schematic for a 2-stage op amp with differential inputs and a singleended output with a telescopic cascoded p-channel input stage with a tail-current bias and with an n-channel common-source second stage and a tail voltage bias. The op amp is to be externally compensated with a dominant pole on the output of the first stage. b) Give an expression for the dc gain of the op amp of part a) in terms of the smallsignal model parameters c) Give an expression for the GB of the op amp in terms of the small-signal model parameters. Page 4 of 9

5 Problem 5 Operational amplifiers are often compensated for an acceptably transient response or gain peaking when connected in a standard feedback configuration such as shown in part (a) below. The consumer often uses the amplifier in other configurations. Shown below are four different amplifier structures. Assume that in all cases the resistors are chosen so that the dc gain is 100. Assume the op amp has been designed so that it has a dc gain of 100,000 and a pole at 10 rad/sec with a phase margin at unity gain of 60 o. Compare the 3dB bandwidth, the overall frequency response, and the step response of the following four circuits assuming the same op amp is used in all four cases. R 2 R 2A R 2A (a) (b) R 2 R 2 VOUT VOUT (c) (d) Page 5 of 9

6 Problem 6 A periodic signal was applied to an ADC and the output was sampled 4096 times at 1msec spacings over precisely 11 periods of the output. A DFT using the FFT was used to obtain the DFT of the sampled sequence. The magnitude of the first 120 terms, expressed in DB, are given on the following page. All remaining terms were smaller than -95dB. a) What is the magnitude of the signal? b) What was the frequency of the signal? c) What is the SFDR? d) What is the THD? Page 6 of 9

7 Index Number Mag (db) Index Number Mag (db) Index Number Mag (db) Page 7 of 9

8 Problem 7 A 5-bit charge redistribution DAC is shown below. Assume all capacitors are ideal except for the largest capacitor, which instead of being 16C, it is only 15C. Assume the op amp and switches are all ideal. a) Give the output of this DAC for all 32 codes of the input b) Determine the DNL c) Determine the ENOB based upon the INL C F =32C C 8C 2C C CX d n-1 d n-1 d n-2 d n-2 d 1 d 1 d 0 d 0 1A 2A 1 2 Page 8 of 9

9 Problem 8 Two operational amplifiers are shown below. Assume the standard symmetry properties in both structures. a) Compare the dc voltage gain (differential output voltage divided by the differential input voltage) of the two amplifiers in terms of the small-signal model parameters. b) If the lengths of all devices are the same and W5=0.9W3, compare the dc voltage gain of the two amplifiers in terms of the natural design parameters. c) Compare the power dissipation of the two amplifiers assuming the devices in the left circuit are sized identical to those in the right circuit. VDD VDD M3 M5 M6 M4 M3 M5 M6 M4 CL CL CL CL M1 M2 M1 M2 VXX M8 VXX M8 Page 9 of 9