2. (2pts) Why is the design parameter that is available to the designer in a typical bipolar process?

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1 EE 330 Exam 2 Fall 2014 Name Instructions: This is a 50-minute exam. Students may bring 2 pages of notes (front and back) to this exam. The points allocated to each question and each problem are as indicated. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If references to semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; ncox=100 A/v 2 pcox= ncox/3,vtno=1v,vtpo= - 1V, V -1/2,, ϕ=0.6v, COX=2fF/ 2, and = 0 If reference to a bipolar process is made, assume this process has key process parameters JS=10-15 A/ 2, β=100 and VAF =. The ratio of Boltzmann s constant to the charge of an electron is k/q= 8.61E-5 V/K. If any other process parameters are needed, use the process parameters associated with the process described on the attachments to this exam. Specify clearly what process parameters you are using in any solution requiring process parameters. Also attached to this exam is a table that has information about large and small signal models of devices. 1. (2pts) There are several devices available in a bipolar process but the process is typically optimized to obtain good performance of one device with little concern for the performance of the remaining devices. For which device is the bipolar process optimized for? 2. (2pts) Why is the design parameter that is available to the designer in a typical bipolar process? 3. (2pts) Although for many applications, a CMOS process is the process that is ultimately used, designers would often prefer to work in a bipolar process. What is the major reason designers often prefer to work in a bipolar process? 4. (2 pts) What is the major processing step in a bipolar process that makes the size of the bipolar transistor so big? Page 1 of 10

2 5. (2pts) What is the major difference between an SCR and a Triac? 6. (2pts) Some on-line definitions of an amplifier state that an amplifier increases the amplitude of a current or a voltage but the definition we gave for an amplifier was somewhat different. What key property of an amplifier is missing in the above definition? 7. (2pts) What is the purpose of guard rings in a bulk CMOS process? 8. (2pts) In the bulk CMOS process that was described in class, the gate was selfaligned. What does this mean and why is it important to have the gate self-aligned? 9 (2pts) What is the difference between an enhancement mode and a depletion mode n-channel transistor? 10 (2pts) What region of operation in the bipolar process corresponds to the saturation region of operation in a MOS process? Page 2 of 10

3 Problem 1 (16 pts) Determine W and L so that the quiescent drain voltage is 2V. 8V 500K 2K W=? L=? C 1 A E =100µ 2 V D M 1 C 2 V OUT V IN Q 1 10K 2K Page 3 of 10

4 Problem 2 (16 pts) Determine the quiescent output voltage. Assume the small-signal input VIN is very small. 2.5K V OUT W=4µ L=1µ 5V 1K V IN Page 4 of 10

5 Problem 3 (16 pts) Consider the following circuit where the capacitor C is very large. a) Determine the quiescent drain voltage, VD b) Determine the quiescent output voltage c) What is the quiescent power dissipation in the MOS transistor? 2V 10K V D C V OUT V IN (t) L=1µ W=2µ 2K -2V Page 5 of 10

6 Problem 4 (16 pts) Consider the following circuit. The waveforms VAC is the 60Hz line voltage. Assume the triac has a gate trigger voltage of 2Vand that the relationship between the gate current and the gate voltage of the traic is as shown on the IG:VG plot on the right. a) Size the resistor R1 so that the triac turns on at TS/8 and 5TS/8 and subsequently at the same times in the VLOAD waveform in each period as shown below. The time TS is the period of the 60 Hz AC line voltage. b) Identify the quadrants that the triac is operating in. V AC I G 10K I F R L V LOAD -2V V G 2V R 1 V AC 170V t T S 170V V LOAD t T S Page 6 of 10

7 Problem 5 (16 pts) Draw the small-signal equivalent circuit for the following amplifier structure. Do not solve. 10V 1K 1.5K 9K A E = 100µ 2 Q 1 7.4V 6.5V M2 W=10µ L=1µ M 3 W=10µ L=1µ C V out V in 2K 2mA W=2µ L=25µ 36K M 4 Page 7 of 10

8 TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS MINIMUM 3.0/0.6 Vth volts SHORT 20.0/0.6 Idss ua/um Vth volts Vpt volts WIDE 20.0/0.6 Ids0 < 2.5 < 2.5 pa/um LARGE 50/50 Vth volts Vjbkd volts Ijlk <50.0 <50.0 pa Gamma V^0.5 K' (Uo*Cox/2) ua/v^2 Low-field Mobility cm^2/v*s COMMENTS: XL_AMI_C5F FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS Vth Poly >15.0 <-15.0 volts PROCESS PARAMETERS N+ACTV P+ACTV POLY PLY2_HR POLY2 MTL1 MTL2 UNITS Sheet Resistance ohms/sq Contact Resistance ohms Gate Oxide Thickness 144 angstrom PROCESS PARAMETERS MTL3 N\PLY N_WELL UNITS Sheet Resistance ohms/sq Contact Resistance 0.78 ohms COMMENTS: N\POLY is N-well under polysilicon. CAPACITANCE PARAMETERS N+ACTV P+ACTV POLY POLY2 M1 M2 M3 N_WELL UNITS Area (substrate) af/um^2 Area (N+active) af/um^2 Area (P+active) 2308 af/um^2 Area (poly) af/um^2 Area (poly2) 53 af/um^2 Area (metal1) af/um^2 Area (metal2) 32 af/um^2 Fringe (substrate) af/um Fringe (poly) af/um Fringe (metal1) af/um Fringe (metal2) 48 af/um Overlap (N+active) 206 af/um Overlap (P+active) 278 af/um Page 8 of 10

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