EE 330 Homework 5 Fall 2016 (Due Friday Sept 23)

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1 EE 330 Homework 5 Fall 2016 (Due Friday Sept 23) Assume the CMOS process is characterized by model parameters VTH=1V and µcox=100µa/v 2. If any other model parameters are needed, use the measured parameters from the ON T6AU process run that are attached. On those problems that involve the design of passive components, a sketch of the design is sufficient provided you indicate dimensions (i.e. it need not be done in Cadence). Problem 1 Design a 2K resistor in the ON 0.5µ CMOS process. Use Poly 1 for the resistor. The width-length ratio of an imaginary box enclosing the resistor should have a W/L ratio of between 1:2 and 2:1. The layout of the resistor can be either sketched or come from a Cadence layout. Problem 2 Design a 1pF capacitor in the ON 0.5µ CMOS process. Clearly specify which layers you are using for this capacitor. The layout of the capacitor can be either sketched or come from a Cadence layout. Problem 3 Four non-contacting regions are shown. Identify the parasitic capacitances and their size if this is fabricated in the 0.5u CMOS process. Don t forget that there is substrate below all layers. (assume this drawing is to scale) 12λ Poly Metal 1 Metal 2 Metal 3 9λ Active Problem 4 If the voltage of a forward-biased pn junction is varied between 0.5V and 0.6V, what is the range in the diode current. Assume the junction area of the diode is 50µ 2 and JS=10-15 A/µ 2. Page 1 of 11

2 Problem 5 Determine the current ID (within ±5%) if VX=10V for the following circuit. Assume the area of the diode is 200µ 2 and JS=10-15 A/u 2. 2K V X V R I D Problem 6 Repeat Problem 5 if VX=520mV. Problem 7 Analytically determine the quantities indicated with a?. 5V 5V 5V 1K I OUT =? 1K I OUT =? 3V M 1 V OUT =? W=10u L=2u 3V M 1 W=10u L=2u 3V M 1 W=10u L=2u (a) (b) (c) Problem 8 Determine W so that VOUT = 6V 9V V OUT M 1 W=? L=2u Problem 9 Assume a resistor has a resistance of 2.034KΩ at T=250 K. If the TCR of this resistor is constant of value 800 ppm/ C, what will be the resistance at T=320 K? Page 2 of 11

3 Problem 10 Gate protection circuits are used to protect the sensitive gate oxide of devices connected to the input of an integrated circuit from modest short-duration over voltages. Although no input protection circuit can protect from all unknown over-voltages, the Human Body Model (HBM) is often used to model the type of over-voltages that are commonly experienced when humans might become statically charged during normal activities. Such a model is shown below with a connection to one pad on the integrated circuit. In this model, RB is the body resistance, CB is the body capacitance, and VB is the charge on the body capacitance. Touching of the circuit while the person is charged is modeled by closing the switch in this model. At a time designated as t=0 it is assumed that the switch is closed and this inserts a voltage into the input pad of the integrated circuit. In the absence of the gate protection circuit, the pad voltage will appear directly on the voltage VINT of the internal integrated circuit if the input impedance to the Internal Circuit is high. VDD t=0 D2 VINT VB CB RB Spark Pad RProt D1 Internal Circuit Chip Boundary Gate Protection Circuit Assume the Internal Circuit has an input that is four parallel-connected minimum sized inverters that are designed in the ON 0.5µ CMOS process. Assume that the diodes D1 and D2 can be modeled as an ideal diode with JS=10-20 A/µ 2 and that the area of each of the two diode junctions is 1000µ 2. Consider two HBMs. One is termed a low voltage model and the other a high voltage model. These are characterized respectively by HBM1: VB =250V, CB=150pF, RB=1. HBM2: VB =2KV, CB=150pF, RB=1. a) What will be the peak value of the voltage VINT when the switch is closed if the gate protection circuit is absent (i.e. the Pad is directly connected to the Internal Circuit) with each of the models? b) What will be the peak value of the voltage VINT when the switch is closed if the gate protection circuit is present with each of the models? Assume RPROT=10K. c) What will be the peak current in D2 with each of the models? Assume RPROT=10K. d) What is the purpose of including the resistor RPROT and what are the disadvantages of including this resistor in the gate protection circuit? Page 3 of 11

4 Problem 11 Using ModelSim, create a 1 bit adder with inputs {a,b, Cin} and outputs {S, Cout}. A 1 bit adder can be implemented using XOR, AND, and OR gates as seen in the example circuit below: Include code for your adder, the test bench, and your input and output waveforms. Page 4 of 11

5 Problem 12 (Extra Credit). The audio amplifier shown has a gain determined by the resistors R1 and R2. The resistor R1 is ideal of value 1K and R2 is nominally of value 10K (with a voltage across it of 0V) but has a voltage coefficient of resistance of 400ppm/V. a) If VIN=0.1sin2000t, what is the maximum error this amplifier will make in amplifying this signal due to the voltage coefficient of R2? b) Repeat part a) if VIN=sin2000t c) What is the THD of the output if VIN=sin2000t?) R 1 R 2 V IN V OUT Problem 13 (Extra Credit) Diodes are often used to build temperature sensors. If one considers that the standard diode equation accurately characterizes the I-V relationship for the diode under modest forward bias, taking the natural logarithm of both sides, an alternate equivalent expression for the diode equation is VD V k I t D I I e V =T ln D S D q I S where T is in K. In the second equation, we have replaced Vt with kt/q to explicitly show the temperature dependence of this term. Looking at the second form, it could be argued that if a constant current were used to excite the diode, then the diode voltage would be proportional to temperature and thus the diode could serve as a very linear temperature sensor. Unfortunately, this argument falls apart because the parameter IS in the diode equation itself shows some temperature dependence. The following equation explicitly shows the temperature dependence of the diode equation. -V VD V G0 I(T) J m Vt A T e e SX where the parameters JSX, VGO, and m are constants that are independent of temperature and where A is the cross-sectional area of the diode. a) If JSX=0.45A/μ 2, VG0=1.17V, m=2.3, and A=200 μ 2, obtain an expression for and plot IS versus temperature from T=0 C to T=100 C. b) If IS was measured in the laboratory at t=27 C, what percent change in IS would occur if the temperature in the room increased to 32 C. c) Quantitatively comment on the accuracy you can expect to obtain in measuring IS in the laboratory if the heating/cooling in the room has a ripple temperature of 2 C peak to peak. t Page 5 of 11

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7 MOSIS WAFER ACCEPTANCE TESTS RUN: T6AU VENDOR: AMIS TECHNOLOGY: SCN05 FEATURE SIZE: 0.5 microns Run type: SKD INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of MOSIS test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar measurements on a selected wafer are also attached. COMMENTS: American Microsystems, Inc. C5 TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS MINIMUM 3.0/0.6 Vth volts SHORT 20.0/0.6 Idss ua/um Vth volts Vpt volts WIDE 20.0/0.6 Ids0 < 2.5 < 2.5 pa/um LARGE 50/50 Vth volts Vjbkd volts Ijlk <50.0 <50.0 pa Gamma V^0.5 K' (Uo*Cox/2) ua/v^2 Low-field Mobility cm^2/v*s COMMENTS: Poly bias varies with design technology. To account for mask bias use the appropriate value for the parameter XL in your SPICE model card. Design Technology XL (um) XW (um) SCMOS_SUBM (lambda=0.30) SCMOS (lambda=0.35) FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS Vth Poly >15.0 <-15.0 volts PROCESS PARAMETERS N+ P+ POLY PLY2_HR POLY2 M1 M2 UNITS Sheet Resistance ohms/sq Contact Resistance ohms M3 N\PLY N_W UNITS Sheet Resistance ohms/sq Contact Resistance 0.79 ohms Gate Oxide Thickness 142 angstrom Page 7 of 11

8 COMMENTS: N\POLY is N-well under polysilicon. CAPACITANCE PARAMETERS N+ P+ POLY POLY2 M1 M2 M3 N_W UNITS Area (substrate) af/um^2 Area (N+active) af/um^2 Area (P+active) 2335 af/um^2 Area (poly) af/um^2 Area (poly2) 49 af/um^2 Area (metal1) af/um^2 Area (metal2) 35 af/um^2 Fringe (substrate) af/um Fringe (poly) af/um Fringe (metal1) af/um Fringe (metal2) 52 af/um Overlap (N+active) 232 af/um Overlap (P+active) 312 af/um CIRCUIT PARAMETERS UNITS Inverters K Vinv volts Vinv volts Vol (100 ua) volts Voh (100 ua) volts Vinv volts Gain Ring Oscillator Freq. DIV256 (31-stg,5.0V) MHz D256_WIDE (31-stg,5.0V) MHz Ring Oscillator Power DIV256 (31-stg,5.0V) 0.49 uw/mhz/gate D256_WIDE (31-stg,5.0V) 1.01 uw/mhz/gate Page 8 of 11

9 COMMENTS: SUBMICRON T6AU SPICE BSIM3 VERSION 3.1 PARAMETERS SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8 * DATE: Jan 11/07 * LOT: T6AU WAF: 7101 * Temperature_parameters=Default.MODEL CMOSN NMOS ( LEVEL = 49 +VERSION = 3.1 TNOM = 27 TOX = 1.42E-8 +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = K1 = K2 = K3 = K3B = W0 = E-8 NLX = 1E-9 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = DVT1 = DVT2 = U0 = UA = E-13 UB = E-18 +UC = E-11 VSAT = E5 A0 = AGS = B0 = E-6 B1 = 5E-6 +KETA = E-3 A1 = E-7 A2 = RDSW = E3 PRWG = PRWB = WR = 1 WINT = E-7 LINT = E-8 +XL = 1E-7 XW = 0 DWG = E-8 +DWB = E-8 VOFF = E-4 NFACTOR = CIT = 0 CDSC = 2.4E-4 CDSCD = 0 +CDSCB = 0 ETA0 = E-3 ETAB = E-4 +DSUB = PCLM = PDIBLC1 = PDIBLC2 = E-3 PDIBLCB = DROUT = PSCBE1 = E8 PSCBE2 = E-4 PVAG = 0 +DELTA = 0.01 RSH = 83.5 MOBMOD = 1 +PRT = 0 UTE = -1.5 KT1 = KT1L = 0 KT2 = UA1 = 4.31E-9 +UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4 +WL = 0 WLN = 1 WW = 0 +WWN = 1 WWL = 0 LL = 0 +LLN = 1 LW = 0 LWN = 1 +LWL = 0 CAPMOD = 2 XPART = 0.5 +CGDO = 2.32E-10 CGSO = 2.32E-10 CGBO = 1E-9 +CJ = E-4 PB = MJ = CJSW = E-10 PBSW = 0.8 MJSW = CJSWG = 1.64E-10 PBSWG = 0.8 MJSWG = CF = 0 PVTH0 = PRDSW = PK2 = WKETA = LKETA = E-3 ) * Page 9 of 11

10 .MODEL CMOSP PMOS ( LEVEL = 49 +VERSION = 3.1 TNOM = 27 TOX = 1.42E-8 +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = K1 = K2 = E-3 K3 = K3B = W0 = E-8 NLX = E-8 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = DVT1 = DVT2 = U0 = UA = E-9 UB = 1E-21 +UC = E-11 VSAT = E5 A0 = AGS = B0 = E-6 B1 = 5E-6 +KETA = E-3 A1 = E-4 A2 = RDSW = 3E3 PRWG = PRWB = WR = 1 WINT = E-7 LINT = E-7 +XL = 1E-7 XW = 0 DWG = E-8 +DWB = E-8 VOFF = NFACTOR = CIT = 0 CDSC = 2.4E-4 CDSCD = 0 +CDSCB = 0 ETA0 = ETAB = DSUB = 1 PCLM = PDIBLC1 = PDIBLC2 = E-3 PDIBLCB = DROUT = PSCBE1 = E9 PSCBE2 = 5E-10 PVAG = 0 +DELTA = 0.01 RSH = MOBMOD = 1 +PRT = 0 UTE = -1.5 KT1 = KT1L = 0 KT2 = UA1 = 4.31E-9 +UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4 +WL = 0 WLN = 1 WW = 0 +WWN = 1 WWL = 0 LL = 0 +LLN = 1 LW = 0 LWN = 1 +LWL = 0 CAPMOD = 2 XPART = 0.5 +CGDO = 3.12E-10 CGSO = 3.12E-10 CGBO = 1E-9 +CJ = E-4 PB = MJ = CJSW = E-10 PBSW = 0.99 MJSW = CJSWG = 6.4E-11 PBSWG = 0.99 MJSWG = CF = 0 PVTH0 = E-3 PRDSW = PK2 = E-3 WKETA = E-4 LKETA = E-3 ) * Page 10 of 11

11 Problem 10 Build a register in Verilog that holds a single 16-bit variable A. At every positive clock edge the register should replace A with the 16-bit INPUT. If the reset input is high, A will be reset to 0. If the xor input is high, A will be xor'd with 1. If the xor input is low, A will be xor'd with 0. If both the reset input and xor input are set to high, the register will be set to 0. Demonstrate proper results using a Verilog simulation. Problem 12 (Extra Credit) Obtain an expression for the output voltage versus temperature for the circuit shown below. Assume D1 and D2 are matched. 50K V OUT D 1 D 2 50K Problem 14 (Extra Credit) for the circuit shown below. Obtain an expression for the output voltage versus temperature D 1 D 2 V OUT 5V 2 Page 11 of 11