INTRODUCTION TO CIRCUIT SIMULATION USING SPICE

Transcription

1 LSI Circuits INTRODUCTION TO CIRCUIT SIMULATION USING SPICE Introduction: SPICE (Simulation Program with Integrated Circuit Emphasis) is a very powerful and probably the most widely used simulator for electrical and electronic circuits. This experiment aims at introducing you to some of the capabilities of the SPICE program applied to CMOS LSI circuit design. It can perform nonlinear dc, nonlinear transient, linear ac analysis and other types of simulations. The circuits may contain resistors, capacitors, inductors, mutual inductors independent voltage and current sources, four types of dependent sources, transmission lines, and four most common semiconductor devices: diodes, BJTs, JFETs, and MOSFETs. This experiment will use SPICE s dc and transient analysis capabilities to analyze circuits based on CMOS n-type and p-type enhancement mode MOSFETs and illustrate the importance of such a simulator in LSI Design. THE CMOS INERTER Consider the circuit of the CMOS inverter below. When the input is high the pulldown device (Mpd) is on but gs of the p-channel device is zero and hence the pullup device (Mpu) is off such that the output pulls all the way to ground. When the input is low, gs of the p-channel device is dd and hence it is on. The pulldown is off and the output rises to dd. dd Mpu in Mpd C load out To simulate the performance of the circuit, the various nodes are identified (e.g., 1,2,3) and each device is given a unique name (eg. Mpu, Cload, Mpd). The circuit can now be simulated in SPICE by a set of program statement stored in a data file. A typical input file consists of a title line, a set of element statements that describe the circuit, and a set of control statements that instruct spice during program execution. The entire input file must be terminated by an.end control statement. Input line in which the first character is an asterisk (*) are interpreted as comment line. Details rules for circuit description and control statements are described below. RULES FOR CIRCUIT DESCRIPTION 1. Node identifiers or numbers must be non-negative integers. 2. The ground node (0 olts) must be numbered zero. 3. Device names can be up to 8 characters in length. 4. The first letter of a device name identifies the device type.eg. R for registor, C for capacitor, M for MOSFET, for independent voltage source and I for independent current source 5. alues can be expressed as integers or floating point numbers, the following abbreviations may be employed: t: lel2 k: le3 n:le-9 g: le9 m: le-3 p: le-12 meg: le6 u: le-6 f: le Comments can be inserted into the circuit description by beginning the statement with an * as the first character WRITING YOUR CIRCUIT DESCRIPTION Use the following as a template to writing a description: 1

2 (title) * Spice options : * To limit width of output to 80 characters useful for ttys..width out=80. * To suppress page ejects and printout of model parameters..options nopage nomode * Circuit description(see Circuit Element Description): * Model specification (see Circuit Element Description): * Input signals (see Signal Source Description): * Simulation modes: * Generating outputs * End of simulation:. end ABBREIATED SPICE MANUAL Circuit Element Description. Registor and Capacitors: Devicename n1 n2 alue Devicename is rxxxxxxxx for a registor, cxxxxxx for a capacitor. n1, n2 are the node numbers of the device terminals alue is the resistance (in ohms) or capacitance (in Farads) of the device. Mosfets: Devicename is n1 n2 n3 n4 modelname 1 w Devicename is mxxxxxx The ordering of the nodes is drain, gate, source, and substrate l and w are channel length and width (in meters ) respectively eg. mpu penh l=3u w=10u mpd nenh l=3u w=4u Notice that the substrate of the p-type enhancement device is connected to the positive supply whilst that of the n-type enhancement device is connected to the ground node. Model name : The simulator needs detailed information on the technology being simulated. The MOSFET model in SPICE 2G5 permits 37 different parameters to be set in order to describe the target technology. These parameters are included in a model statement and the model name refers to the required model. The models of the CMOS p and n type enhancement mode transistors given in the questions following this introduction, are values derived by the fabricators for this particular CMOS technology and should be included in the circuit description file. Signal Source Description. In addition to describing the circuit it is necessary to describe the supply voltages and the various waveforms you wish to apply to the circuit. The element statement for an independent voltage or current source is written in the form Sourcename positive-node negative-node type specification Sourcename is the voltage source identifier, type specifies the general nature of the source which could be DC, AC, SIN, PULSE or PWL(Piecewise Linear) with details included in the specification entry. Some example are given below : DC SOURCE : 2

3 vdd 4 0 dc 5 vbias 15 0 dc 750mv oltage sources, in addition to being used for circuit excitation, are the ammeters for SPICE, that is, zero valued voltage sources may be inserted into the circuit for the purpose of measuring current. They will, of course, have no effect on circuit operation since they represent short circuits. Pulsed oltages. Sourcename n+ n- pulse (v1, v2, td, tr, tf, pw, per) n+ and n- have the same meaning as for a dc source, 1 is Initial voltage, 2 is the pulsed voltage, TD is delay time, TR is rise time, TF is fall time, PW is pulse width, PER is the pulse period. eg. vclock 1.0pulse(0,5,1ns,2ns,100ns,200ns) 2 1 PW 0 t TR TF TD PER Fig : PULSE Waveform Piece-wise Linear oltages. General form: Sourcename n+ n-pwl ( t1 v1 t2 v2 t3 v3... ) n+ and n- have the same meanings as for a dc source, Each pair of values of t and v specifies that the value of the source is v at time t. The value of the source at intermediate values of time is determined using linear interpolation on the input values T 1 T T 6 2 T 3 T 4 T 5 Fig : Piecewise Linear waveform t Simulation Modes SPICE can perform various types of analysis; we are concerned just with two: the transient analysis and the dc analysis modes. Transient Analysis In this mode, SPICE can be used as an oscilloscope to observe variations in voltage and current with time. General form:. tran tstep tstop tstart tstep is the increment time (in seconds ) tstop is the finish time tstart is the initial time (defaults to zero) eg..tran 1ns 100ns Note: The smaller the value of tstep, the finer the detail that can be seen in the waveforms. The price paid is more computer time, so you must ask yourself what is a reasonable value given the circuit parameter and input waveforms. 3

4 DC Analysis. In this mode SPICE gives the values of requested node voltage or currents as a function of an independent voltage or current source.. dc Source name vstart vstop vincr Sourcenme is the name of the voltage source to be varied. start is the initial value stop is the final value incr is the increment or step value eg:.dc vin Generating Output For any analysis mode the user must select which nodes are to be monitored. The output can then be displayed by either of the following two methods: 1) a print statement giving tabular listing of the results of one to eight output variables with the independent variable (time or voltage) in the left hand column and the other variables in the other columns 2) a plot statement defining the contents of one plot of from one to eight output variables versus the independent variable. The two options are requested as follows:. plot Mode out1 out2.out8. print Mode out1 out2 out8 Mode specifies the analysis mode, and out1 out2 is the list of nodes to be monitored and can have one of the following three forms: (n1) specifies the voltage at node n1 with respect to ground. (n1, n2) specifies the voltage difference between node n1 and n2. i(vname) specifies the current flowing in the independent voltage source named vname. eg :.plot dc v(2) v(5) v(7) i(vname). plot tran v(1) v(2) (0,5) The (0,5) forces all nodes to be plotted on the same scale of 0 to 5 volts. Exercise: 1. Write a SPICE sourcefile for the simple low-pass filter shown below and produce a transient analysis of the circuit over a period of usec with an increment of 10nsecs. To help you in this, have a look at the circuit description of assignment 2, but use rise and fall times of 1ns for your input waveforms volt 1nF 1 Mhz Determine the rise and fall times from the plot. How do these results compare with theory? 2. The SPICE circuit description shown below is for a CMOS inverter. Draw the circuit carefully labeling all the nodes and naming the components. A copy of the description file can be found in Itw/spice/cmosinv. simple CMOS inverter *spice option :.width out=80. options nopage nomod *circuit description: mpu penh w=10u l=3u mpd nenh w=4u l=3u vdd vin 1 0 pulse (0 5 3ns 3ns 3ns 20ns 40ns) 4

5 *model specification: *MCE 3 Micron CMOS processes parameters process 2 *N channel typ. model nenh nmos level=2 vto=0.85 kp=30e-6 tox =470e-10 nsub =38e14 +ld =0.6e-6 uo=624 uexp=.055 vmax=20e4 neff=9.8 delta=2.0 +cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33 pb=0.81 *p channel typ. model penh pmos level =2 vto = kp=12e-6 tox =470e-10 nsub=8.7e14 +ld =0.5e-6 uo =200 uexp =0.18 vmax =12e4 neff= 4.0 delta=2.0 +cj= 100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 pb=0.7 *end simulation file:.end Add a load of the same form as in assignment (1), to the CMOS inverter between ground and the junction of the two transistors. Use a 50ff(50E-15) capacitor which is representative of a typical load capacitance. (a) Use SPICE to perform a transient and a DC analysis of this circuit. (b) Observing both the output voltage (on the node connecting the load resistor and capacitor) and the input voltage, determine the rise time and the fall time of the inverter. Plot the results. Note the use of 3ns rise and fall times for vin. Remember to use similar edge speeds in the rest of the experiments for input waveforms (c) From the DC analysis measure the inversion voltage inv, i.e. the input voltage at which out =in. What do you think is the optimum value of inv? Why? (d) Now make the width of the p-channel device the same as the n-channel device and repeat the simulation. Repeat step (a) to (c) and determine the rise time, fall time and the inversion voltage of the inverter for this case. How has this change affected the dc transfer characteristics? Why is the rise time different from the fall time? Comment on the performance of a system based on this type of gate. APPENDIX : SPICE MOS MODEL PARAMETERS NAME PARAMETER UNITS DEFAULT REMARKS LEEL Model index - TO Threshold voltage 1.0 KP Transconductance A/ 2 1.0e-3 parameter TOX Thin-oxide thickness m GAMMA Bulk Threshold 1/2 0 Parameter PHI Surface potential 0.6 LAMBDA Channel Length Modulation parameter -1 0 CJ Zfero-bias bulk junction F/m 2 0 bottom capacitance CJSW Zfero-bias bulk junction F/m 0 side wall capacitance MJ Bulk Junction grading coefficient MJSW Bulk Junction sidewall Grading coefficient PB Bulk Junction potential 0.6 NSUB Substrate doping Cm -3 0 UO Surface mobility Cm 2 /v.s 600 UCRIT Critical field for /cm 1x10 4 LEEL 2 mobility degradation UEXP Critical field exponent - 0 LEEL 2 in mobility degradation THETA Mobility modulation -1 0 LEEL 3 MAX Maximum drift velocity of carrier M/s 0 5