HIP V, 10A Half Bridge Power MOSFET Array. Description. Features. Ordering Information. Symbol. Packages FN

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1 TM April 998 6V, A Half Bridge Power MOSFET Array Features Two A Power MOS N-Channel Transistors Output Voltage to 6V r DS(ON) Ω Max Per Transistor at = V r DS(ON) Ω Max Per Transistor at = V Pulsed Current A Each Transistor Avalanche Energy mj Each Transistor Grounded Tab Eliminates Heat Sink Isolation Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. AS - to 2 Ld SIP Z.67C AS2 - to 2 Ld Gullwing SIP Z.67A AS3 - to 2 Ld SIP Z.67B NOTE: When ordering use the entire part number. Description The is a power half-bridge MOSFET array that consists of two matched N-Channel enhancement-mode MOS transistors. The advanced Intersil PASIC2 process technology used in this product utilizes efficient geometries that provides outstanding device performance and ruggedness. The is designed to integrate two power devices in one chip thus providing board layout area and heat sink savings for applications such as Motor Controls, Uninterruptable Power Supplies, Switch Mode Power Supplies, Voice Coil Motors, and Class D Power Amplifier. Symbol GATE GATE2 2 DRAIN Z Z2 D SOURCE = DRAIN2 SOURCE2 3, TAB Packages JEDEC TS-AA (ALTERNATE VERSION) AS JEDEC MO-69 AS2 (TAB) 3 2 GATE 2 GATE2 3 SOURCE2 SOURCE-DRAIN2 DRAIN Z.67B (SIP) AS3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 22. All Rights Reserved FN3983.

2 Absolute Maximum Ratings T C = 2 o C, Unless Otherwise Specified UNITS Continuous Drain-Source Voltage Over Operating Junction and Case Temperature Range V Drain-Gate Voltage V DGR 6 V Gate-Source Voltage ±2 V Continuous Source-Drain Diode Current (Note 2) I SD A Pulsed Drain Current, each Output, all Outputs on (Notes, 2) I DM 2 A Continuous Drain Current, each Output, all Outputs on (Note 2) I DS A Single Pulse Avalanche Energy (Note 3) Refer to UIS Curve E AS mj Continuous Power Dissipation at T C = 2 o C (Infinite Heatsink) P D 6 W Continuous Power Dissipation, Derate above T C = 2 o C W/ o C Thermal Information θ JA 6 o C/W Operating Case Temperature Range T C - to 2 o C Junction and Storage Temperature Range T J, T STG - to o C Lead Temperature (For Soldering, s)(lead Tips Only) T L 3 o C Continuous Drain-Source2 Voltage Over Operating Junction Temperature Range V NOTES:. Pulse width limited by maximum junction temperature. 2. Drain current limited by package construction. 3. V DD = 2V, Start T J = 2 o C, L =.mh, R GS = Ω, R =. See Figures 2, 2, and 3. Electrical Specifications T C = 2 o C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain-Source Breakdown Voltage BS I D = µa, = V T C = - o C to 2 o C V T C = 2 o C V Gate Threshold Voltage (TH) =, I D = 2µA V Drain-Source2 Breakdown Voltage (Across D) B2 I DS2 = µa,, V G2S2 = V T C = 2 o C - - V Zero Gate Voltage Drain Current I DSS = 6V = V Drain-Source2 Current (Through D) I DS2 2 = 6V = V, V G2S2 = V T C = 2 o C - - µa T C = 2 o C -.3 µa T C = 2 o C - - µa Drain-Source On-State Voltage (Note ) Forward Gate Current, Drain Short Circuited to Source Reverse Gate Current, Drain Short Circuited to Source (ON) I D = A, = V V I D = A, = V -.. V I GSSF = V, = 2V - - na I GSSR = V, = -2V na Drain-Source On Resistance (Note ) r DS(ON) = V, I D = A T C = 2 o C Ω = V, I D = A T C = 2 o C -..2 Ω = V, I D = A T C = 2 o C -.. Ω = V, I D = A T C = 2 o C Ω Forward Transconductance (Note ) g fs = V, I D = A -. - S 2

3 Electrical Specifications T C = 2 o C, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Turn-On Delay Time (Note ) t d(on) V DD = 3V, R L = 3Ω - - ns Rise Time (Note ) t r I D = A, = V, R G = Ω See Figure - - ns Turn-Off Delay Time (Note ) t d(off) ns Fall Time (Note ) t f ns Total Gate Charge (Note ) Q g(tot) = V, = V, I D = A nc See Figures 6 and 7 Gate-Source Charge (Note ) Q gs nc Gate-Drain Charge (Note ) Q gd -.9. nc Short-Circuit Input Capacitance, Common Source Short-Circuit Output Capacitance, Common Source for Upper FET Short Circuit Output Capacitance Common Source for Lower FET Short-Circuit Reverse Transfer Capacitance, Common Source C ISS = 2V, = V, f = MHz pf C OSS(U) - - pf C OSS(L) pf C RSS - - pf Thermal Resistance Junction to Case R θjc o C/W Thermal Resistance Junction to Ambient R θja o C/W Source-Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SOURCE-TO-DRAIN DIODE SPECIFICATIONS (Across Z and Z2) Forward Voltage (Note ) V SD I SD = A, = V -..2 V Reverse Recovery Time (Across Z) t rr(s-d) I SD = A, di SD /dt = A/µs - - ns Reverse Recovery Time (Across Z2) t rr(s2-d2) I SD = A, di SD /dt = A/µs ns SOURCE2-TO-DRAIN DIODE SPECIFICATIONS D (Across D) Forward Voltage (Note ) V SD I SD = A, = V V Reverse Recovery Time t rr I SD = A, di SD /dt = A/µs ns DEVICE MATCHING Drain-Source On Resistance Match r DS(ON)M = V, I D = A, T C = 2 o C % NOTES:. Pulse test: Pulse Width 3µs, Duty Cycle 2%.. Independent of operating temperature. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 3

4 Typical Performance Curves OPERATION IN THIS AREA MAY BE LIMITED BY r DS(ON) T C = 2 o C µs µs ms ms DC I AS, AVALANCHE CURRENT (A) STARTING T C = 2 o C STARTING T C = 2 o C., DRAIN-TO-SOURCE VOLTAGE (V)... t AV, TIME IN AVALANCHE (ms) FIGURE. SAFE-OPERATING AREA CURVE FIGURE 2. UNCLAMPED INDUCTIVE-SWITCHING 2 = V = 2V = V = 8V 2 - o C 2 o C o C = V PULSE DURATION = 3µs, T C = 2 o C 2 6 8, DRAIN-TO-SOURCE VOLTAGE (V) 2 6 8, GATE-TO-SOURCE VOLTAGE (V) FIGURE 3. SATURATION CHARACTERISTICS FIGURE. TRANSFER CHARACTERISTICS 2. PULSE DURATION = 3µs, = V, I D = A.2 I D = µa NORMALIZED r DS(ON) NORMALIZED BS T J, JUNCTION TEMPERATURE ( o C) FIGURE. NORMALIZED r DS(ON) vs JUNCTION TEMPERATURE T J, JUNCTION TEMPERATURE ( o C) FIGURE 6. NORMALIZED BS vs JUNCTION TEMPERATURE

5 Typical Performance Curves (Continued) NORMALIZED (TH) =, I D = 2µA, GATE-SOURCE VOLTAGE (V) = V = 3V = 2V I D = A, T C = 2 o C T J, JUNCTION TEMPERATURE ( o C) FIGURE 7. NORMALIZED (TH) vs JUNCTION TEMPERATURE 2 Q, GATE CHARGE (nc) FIGURE 8. GATE-SOURCE VOLTAGE vs GATE CHARGE = V, f = MHz, T C = 2 o C 2 C, CAPACITANCE (pf) C RSS C OSS(U) C OSS(L) C ISS = V = V 2 2, DRAIN-TO-SOURCE VOLTAGE (V) FIGURE 9. CAPACITANCE vs VOLTAGE T C, CASE TEMPERATURE ( o C) FIGURE. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE Z θjc, NORMALIZED THERMAL RESPONSE.. - D = SINGLE PULSE T C = 2 o C NOTES:. DUTY FACTOR, D = t /t 2 2. PEAK T J = P DM x (Z θjc ) T C o t, RECTANGULAR PULSE DURATION (s) FIGURE. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

6 Test Circuits and Waveforms t P t AV V L I AS R G DUT V DD - I D V t P I D.Ω BS FIGURE 2. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 3. UNCLAMPED ENERGY WAVEFORMS t ON t OFF V DD t d(on) t d(off) t r t f R L 9% 9% % % V DUT 9% R GS % % PULSE WIDTH % FIGURE. RESISTIVE SWITCHING TEST CIRCUIT FIGURE. RESISTIVE SWITCHING WAVEFORMS V BATTERY -.2µF 2kΩ CURRENT REGULATOR.µF SAME TYPE AS DUT V Q G Q GS Q GD DUT V G I GS CHARGE FIGURE 6. GATE CHARGE TEST CIRCUIT FIGURE 7. BASIC GATE CHARGE WAVEFORM 6

7 36V 3µH R L = 8Ω UF 2.22µF.22µF µf.7µf 2V BHB HEN BHO BHS.22µF Ω 3µH 3.9Ω DIS VSS OUT IN BLO BLS VDD VCC 2V Ω µf IN- ALS HDEL LDEL ALO AHS Ω kω kω AHB AHO HIP8A UF 2.22µF Ω ILIM.22µF Ω.Ω.µF FEEDBACK AUDIO INPUT 2kHz FIGURE 8. 7W SWITCHING AUDIO AMPLIFIER APPLICATION CIRCUIT Device Model Netlist for Half Bridge Power MOSFET Array.SUBCKT 2 3 X _ LS 6 7.n X _ LS2 7 7.n LS n.ENDS.SUBCKT _ MOS 2 NMOS JFET J D 6 D DBODY D2 DBREAK 7 D3 DSUB 9 3 D VBREAK 7 DC 9 C2 2 8P C23 2 P C2 2 3P RDRAIN 3.e-3 RSOURCE 7.e-3 FDSCHRG 2 VMEAS. E. VPINCH 6 8 DC. VMEAS 8 DC..MODEL NMOS NMOS LEVEL=3 (VTO=2.7 TOX=e-8 KP=3.e-3 PHI=.6 GAMMA=2. VMAX=6.2e7 NSUB=.33e6 THETA=.6973 ETA=. KAPPA=.27 L=u W=9u).MODEL J NJF (VTO=-. BETA=.736 LAMBDA=.e-2 P.MODEL D D (IS=.e- N=.3 RS=.).MODEL D2 D (IS=3.e-3 RS=2.e-3 TT=2N CJO=3e-2).MODEL D3 D (IS=.e-3 N=. RS=2.).MODEL D D (IS=.e-3 RS=2.e-3 CJO=97e-2).ENDS NOTE: For further discussion of the PSPICE PowerFET Macromodel consult Spicing-up SPICE II Software for Power MOSFET Modeling, Intersil Application Note AN86. 7