MOSFET Biasing Supplement for Laboratory Experiment 5 EE348L. Spring 2005
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1 MOSFET Biasing Supplement for Laboratory Experiment 5 EE348L Spring 2005 B. Madhavan Spring 2005 B. Madhavan Page 1 of 10 EE348L, Spring 2005
2 5 Laboratory Assignment 5 biasing supplement 5.1 Biasing a MOSFET This section will cover the biasing of an n-channel MOSFET amplifier shown in Figure 5-1. The n-channel MOSFET is to be biased in the saturation region, at an operating point of desired drain current, drain voltage, and gate voltage. The use of the quadratic I D -V GS relationship for a MOSFET in saturation (equation 5.3 in laboratory assignment 5) requires knowledge of the mobility, oxide capacitance per unit area, the width and length of the device, and the threshold voltage. For discrete components, these values vary too much for the quadratic relationship to be a good predictor. One can measure these quantities in the laboratory, but the idea here is to get a design that works without knowing all of the device parameters beforehand. For this example, let us assume that we looked up the data sheet of a discrete MOSFET device that we are interested in, and determined that its threshold voltage, V tn, is in the range of 1V-to-3V. Remember that V GS must exceed the threshold voltage, V tn, for current to flow. V dd R D R b1 M 1 V D V G R b2 R SS Figure 5-1: Biasing example of a common-source amplifier with source-degeneration resistance R ss (signal source and load impedance are not shown). Say we desire a drain current of 1mA. We assume V tn = 3.0V (worst case V tn in range of 1V-3V). We set V GS = 3.25V so that we have V GS -V tn = 0.25V of worst-case gate-source overdrive voltage. Next, a 3.75V gate voltage is arbitrarily chosen. Given that we want V GS = V G V S = 3.25V, this dictates that V S =0.5V. Using Ohm s law, we get the source resistance, R SS = 0.5V/1mA = 500 Ω. Making sure the condition for saturation, V DS >= V GS - V tn, is satisfied, the drain voltage is chosen to be 3.5V (V DS = 3.5V 0.5V = 3.0V). With a supply voltage, V dd =5V, and drain current of 1mA, this requires a 1.5 KΩ resistance (R D ) between the supply and the drain terminal. Next, in order to set the gate voltage to at 3.75V, we use a voltage divider as shown in Figure 5-1 to derive V G = 3.75V from the supply, V dd =5V. The resistor ratio of R b1 : R b2 needs to be 1:3. Therefore we set R b1 =10 KΩ and R b2 =30 KΩ. Note that the bias network requires 125 µa from the 5V supply. The sensitivity of the quadratic I D -V GS characteristic of a MOSFET in saturation is not as severe as that of the exponential I-V characteristic of a diode. This means that V GS has to vary a great deal more than say, V b, the applied voltage across a diode, for the same range of currents. Sometimes, due to tolerances in fabrication, it can be tricky to achieve the exact biasing current. However, a simple solution is to make one of the gate resistors, say R b2, a potentiometer. This allows one to tune and monitor the desired MOSFET performance. B. Madhavan - 2 of 10- EE348L, Spring 2005
3 5.1.1 A systematic procedure for biasing a common-source amplifier Figure 5-1 shows the schematic of a common-source amplifier with source-degeneration resistance R SS. M 1 is a discrete n-channel MOSFET device such as the 2N7000 used in this lab experiment. R D is the resistor connected between the power supply, V dd, and the drain terminal of M 1. R b1 and R b2 establish a dc-bias voltage, V G, at the gate terminal of M 1. V D is the dc-bias voltage at the drain terminal of M 1. V s (not shown in the figure) is the dc-bias voltage at the source terminal of M 1. Note that the source and bulk terminals of M 1 are tied together, which is typical of most discrete MOSFET devices, unless specified otherwise. As discussed in section of Microelectronic Circuits by Sedra and Smith, the source-degeneration resistance R SS acts to reduce the variation in drain current I D due to transistor parameter variation, which is typical of all manufacturing processes. V dd R D R b1 M 1 V D V G C c2 + + C c1 v in (t) R b2 R SS v o (t) - - Figure 5-2: Common-source amplifier schematic with dc-blocking capacitors C c1 and C c2 isolating the dc-potentials at the gate and drain terminals of M 1 from that of the signal source and that of the load. The signal source and load impedance are not shown. As shown in Figure 5-2, dc-blocking (also referred to as ac-coupling) capacitors C c1 and C c2 are added to the input and output terminals respectively of the circuit schematic in Figure 5-1 to isolate the dc-potentials at the gate and drain terminals of MOSFET M1, from that of the signal source and that of the load. Note that the signal source and load impedances are not shown in Figure 5-2. The dc-blocking (ac-coupling) capacitors are chosen large enough (typically in the range of 10 µf to 1 µf) that they are essentially a short circuit in the frequency range of interest. If R b1 and R b2 are chosen large enough that R b1 R b2 is much larger than the signal source resistance, the small-signal voltage at the gate of M 1 is essentially the same as v in (t) in the frequency range of interest. Assuming that channel length modulation is negligible (λ n =0), the small-signal ac-gain from the gate (input) to the drain (output) of MOSFET M 1 is given by gmrd Av = (5.1) 1 + gmrss where g m is the transconductance of MOSFET M 1 at the dc-operating point of I D, V GS, and V DS. If g m R ss >> 1, R D A v = (5.2) Rss In order to determine the values of R D, R SS, R b1, R b2, and the operating point of the MOSFET M 1 for a desired value of ac-gain A v, we need to derive an expression relating the small-signal gain, A v, to the dc-operating point. Using the definition of K n (given in equation 5.4 and equation 5.5 in B. Madhavan Page 3 of 10 EE348L, Spring 2005
4 laboratory assignment 5), we use the expression for the dc-drain current, I D, of MOSFET M 1, which is assumed to be in the saturation region of operation, to get K I ( ) 2 D = VGS Vtn (5.3) 2 KnW K = (5.4) L The expression for the transconductance g m (equation 5.10) of MOSFET M 1 is given by gm = K( VGS Vtn ) = 2KI D (5.5) where V GS, I D, and V tn are the dc gate-to-source potential, the dc drain current and the threshold voltage of MOSFET M 1 in Figure 5-1. To bias MOSFET M 1 in Figure 5-1 in the saturation region, we make the following design choices, where V D is the dc-bias voltage at the drain terminal of M 1, V s is the dc-bias voltage at the source terminal of M 1, and V G is the dc-bias voltage at the gate terminal of M (V GS V tn ) is chosen to be 0.25 V. 2. The above means that V DS > 2V is sufficient to ensure that MOSFET M 1 is in saturation under reasonable variations of temperature and device parameters. Therefore, if V D is chosen to be 3V, V S should be no more than 1V. 3. We choose V dd = 10 V to give us adequate voltage headroom in the choice of a reasonable large R D given a potentially large value of I D. Using the above design choices, we get K I D = (5.6) 32 K g m = (5.7) 4 Vdd VD 32 RD = = ( Vdd VD ) (5.8) I D K VS 32 RSS = = VS (5.9) I D K Substituting the above into the expression for the magnitude of the small-signal gain, A v, we get K 32 ( Vdd VD ) K Vdd VD A 4 8( ) v = = (5.10) K 32V s 1 + 8V s K Given the design choices (2) and (3) above, we get 8(10 3) 56 Av = = (5.11) 1+ 8V s 1+ 8V s Using the above equation relating A v to V S, the dc-bias potential at the source terminal of MOSFET M 1, we get the following results in Table 5-1. We conclude from the preceding discussion and the results in Table 5-1 that in order to obtain an ac small-signal gain of 20 (= 26 db) for the common-source amplifier in Figure 5-1, we have the following design choices for the circuit schematic in Figure 5-1: V S = 0.225V V D = 3.00V (design choice (2) above) V dd = 10.0V (design choice (3) above) V GS V tn = 0.25 V (design choice (1) above), which implies V G V S V tn = 0.25V, resulting in V G = 1.475V for V tn = 1.0V. B. Madhavan - 4 of 10- EE348L, Spring 2005
5 Table 5-1 Relationship between V S and A v V S A v A v (db) MOSFET I-V characteristic for biasing low-power amplifier *Written Feb 28, 2005 for EE348L by Bindu Madhavan. **** options section.options post=1 brief nomod alt999 accurate acct=1 opts.options unwrap dccap=1 numdgt=9.param capop=4 **** circuit description m1 drain gate source bulk nmos_2n7000 W=0.8E-2 L=2.5E-6 **** sources section vdrain drain vss 3.0V vsource source vss 0.225V vbulk source bulk 0V vgate gate vss 1.475V v2 vss 0 0V **** analysis section * see page 8-63 and 8-66 of HSpice user manual.probe dc idrain = par('id(m1)').probe dc cgd = par('-lx19(m1)').probe dc cgs = par('-lx20(m1)').probe dc cgtotal = par('lx18(m1)').probe dc vthreshold = par('lv9(m1)').probe dc vdsat = par('lv10(m1)').probe dc gm = par('lx7(m1)').probe dc gmbs = par('lx9(m1)').probe dc gds = par('lx8(m1)').probe dc rds = par('1/lx8(m1)') **** specify nominal temperature of circuit in degrees C.TEMP=27 **** analysis section.dc vdrain sweep vgate poi **** models section *(this Model is from supertex.com).model nmos_2n7000 NMOS +LEVEL=3 RS=0.205 NSUB=1.0E15 +DELTA=0.1 KAPPA= TPG=1 CGDO=3.1716E-9 B. Madhavan Page 5 of 10 EE348L, Spring 2005
6 +RD=0.239 VTO=1.000 VMAX=1.0E7 ETA= NFS=6.6E10 +XJ=6.4666E-7 TOX=1.0E-7 THETA=1.0E-5 LD=1.698E-9 CGSO=9.09E-9 UO= END Figure 5-3: HSpice netlist for obtaining I-V characteristic of an n-channel MOSFET, 2N7000. We now need to determine I D, g m, and r ds of MOSFET M 1 corresponding to the dc-bias conditions in the design choices listed above. I D will allow us to determine R D and R SS in the circuit schematic in Figure 5-1 for the desired gain of 20 (= 26 db). We use the HSpice netlist in Figure 5-3 to determine the I D (plot parameter idrain = par( id(m1) )) and g m (plot parameter gm = par( lx7(m1) )) of MOSFET M 1 at the desired dc-bias voltages of V D =3V, V G =1.475V and V S =0.225V. From the results of the simulation, we see that I D = 5.29 ma, g m = ms, and r ds = 9.97 kω. This in turn, gives us R D = 7V/5.29mA = 1323 Ω and R SS = 0.225V/5.29mA = Ω. Substituting the above values in the full expression for the ac small-signal gain, A v, we get gmrd ( 29.72mS)( 1323) Av = = = = (5.12) + gmrss 1 + ( 29.72mS)( 42.53) The design is completed by choosing R b1 and R b2 such that V G = given V dd = 10V. The value of the ac small-signal gain calculated above is very close to the ac small-signal gain, A v, of 20 that we expected to get based on the results in Table 5-1. The discrepancy between the ac small-signal gains calculated by using the mathematical equations for I D and g m, and that obtained from using I D and g m obtained from the HSpice dc-sweep analysis is due to the use of more detailed expressions that account for second-order MOSFET device effects in the HSpice simulator. Therefore, we are done with the biasing the common-source amplifier in Figure 5-1. Very Important Point The most important lesson to be learned from this exercise is that intelligent use of circuit analysis guides the intelligent use of computer analysis, allowing one to accurately predict the response of electronic circuits. The efficacy of this methodology is contingent on obtaining accurate model decks for all devices used in the simulation of the HSpice netlist that is an accurate representation of the circuit that is to be built and tested on the laboratory bench Verification of the systematic procedure for biasing a common-source amplifier V dd R D R b1 M 1 C c2 + + C c1 R L v in (t) R b2 R SS v o (t) - - Figure 5-4: Common-source amplifier of Figure 5-2 with load impedance R L. The signal source is not shown. B. Madhavan - 6 of 10- EE348L, Spring 2005
7 In this section, we ensure that the dc-biasing results from the previous section accurately predict the frequency-domain and time-domain behavior of the common-source amplifier schematic in Figure 5-2, which has been obtained from Figure 5-1 by the addition of dc-blocking (ac-coupling) capacitors C c1 and C c2. We then add the load impedance R L as shown in Figure 5-4 to determine the influence of the load impedance R L on the performance of the amplifier. Homework 5 (laboratory assignment 5 pre-lab questions 6 10) asks the student to investigate the response of the amplifier to various values of R L AC-coupled MOSFET common-source amp with source degeneration resistor *Written March 3, 2005 for EE348L by Bindu Madhavan. **** options section.options post=1 brief nomod alt999 accurate acct=1 opts.options unwrap dccap=1.param capop=4 **** circuit description rb1 vdd gate 8.525K rb2 gate vss 1.475K m1 drain gate source bulk nmos_2n7000 W=0.8E-2 L=2.5E-6 rs source vss 'srcres' $500 rd vdd drain 'drainres' $1500 cc1 gatec gate 10uF cc2 drain drainc 10uF rl drainc vss 'loadres' **** sources section v1 vdd vss 10V vbulk source bulk 0V vgate gatec gate1 ac 1 sin(0v 10mV 100k) v2 vss 0 0V **** parameters section.param drainres=1323.param srcres=42.53.param loadres=100k **** probe statement section * see page 8-63 and 8-66 of HSpice user manual.probe dc idrain = par('id(m1)').probe dc cgd = par('-lx19(m1)').probe dc cgs = par('-lx20(m1)').probe dc cgtotal = par('lx18(m1)').probe dc vthreshold = par('lv9(m1)').probe dc vdsat = par('lv10(m1)').probe dc gm = par('lx7(m1)').probe dc gmbs = par('lx9(m1)').probe dc gds = par('lx8(m1)').probe dc rds = par('1/lx8(m1)').probe dc gain = par('20*log10(v(drain)/v(gate))').probe dc gain2 = par('20*log10(v(drain)/v(gatec))').probe dc vgs = par('(v(gate)-v(source))').probe dc vgsov = par('(v(gate)-v(source)-lv9(m1))').probe dc vds = par('(v(drain)-v(source))').probe ac idrain.probe ac cgd.probe ac cgs = par('id(m1)') = par('-lx19(m1)') = par('-lx20(m1)') B. Madhavan Page 7 of 10 EE348L, Spring 2005
8 .probe ac cgtotal = par('lx18(m1)').probe ac vthreshold = par('lv9(m1)').probe ac vdsat = par('lv10(m1)').probe ac gm = par('lx7(m1)').probe ac gmbs.probe ac gds = par('lx9(m1)') = par('lx8(m1)').probe ac rds = par('1/lx8(m1)').probe ac gain.probe ac gain2 = par('20*log10(v(drain)/v(gate))') = par('20*log10(v(drain)/v(gatec))').probe ac vgs = par('(v(gate)-v(source))').probe ac vgsov.probe ac vds = par('(v(gate)-v(source)-lv9(m1))') = par('(v(drain)-v(source))') **** specify nominal temperature of circuit in degrees C.TEMP=27 **** analysis section.ac dec G.tran 1us 100us *(this Model is from supertex.com).model nmos_2n7000 NMOS +LEVEL=3 RS=0.205 NSUB=1.0E15 +DELTA=0.1 +RD=0.239 KAPPA= VTO=1.000 TPG=1 VMAX=1.0E7 CGDO=3.1716E-9 ETA= NFS=6.6E10 TOX=1.0E-7 LD=1.698E-9 UO= XJ=6.4666E-7 THETA=1.0E-5 CGSO=9.09E-9.END Figure 5-5: HSpice netlist for verifying ac and transient performance of the amplifier in Figure 5-4. The frequency response of the common-source amplifier in Figure 5-4 obtained from the HSpice simulation of the HSpice netlist in Figure 5-5 is shown in Figure 5-6. The gain (= v o /v in ) in db from the input to the output is plotted against frequency on the x-axis on a log scale in Figure 5-6. The mid-band gain is measured to be db (=16.12) between 100 Hz and 1 MHz. The gain magnitude of obtained in the previous section, has to be corrected to account for the r ds =9.97 KΩ of MOSFET M 1, and the load resistance R L =100 KΩ. The effective load resistance = 1323 Ω 9970 Ω 100 KΩ = Ω, giving us the corrected ac small-signal gain gmrd ( 29.72mS)( ) Av = = = = (5.13) + gmrss 1 + ( 29.72mS)( 42.53) Figure 5-6: Frequency response of the common-source amplifier in Figure 5-4 whose netlist is shown in Figure 5-5. B. Madhavan - 8 of 10- EE348L, Spring 2005
9 Examining the list file obtained on running HSpice, we see that the node voltages of the circuit schematic in Figure 5-4 are printed out, which are in excellent agreement with our design choices of V G =1.475V, V D =3V, V S =V B =0.225V. In addition, the operating point of the MOSFET M 1 is printed out as well (see below), which shows a drain current of 5.29 ma and g m of 29.72mS, among other small-signal parameters of the MOSFET at the dc operating point. +0:bulk = m 0:drain = :drainc = 0. +0:gate = :gatec = 0. 0:source = m +0:vdd = :vss = 0. element 0:m1 model 0:nmos_2n7 region Saturati id ibs m a ibd f vgs vds vbs 0. vth vdsat m m beta m gam eff m gm m gds u gmb cdtot m p cgtot p cstot cbtot p f cgs p cgd p Figure 5-7: Node voltages and MOSFET parameters corresponding to the dc-operating point in the netlist in Figure 5-5. The transient simulation of the common-source amplifier in Figure 5-4 obtained from the HSpice simulation of the HSpice netlist in Figure 5-5 is shown in Figure 5-6. The peak-to-peak amplitude of the output signal at the drain of MOSFET M1 is measured to be mv for an input signal of peak-to-peak amplitude 20mV, giving a net gain of mV/20mV = 16.11, which is in excellent agreement with the frequency domain gain of db (=16.12) in Figure 5-6. Figure 5-8: transient response of mV peak-to-peak at the drain of MOSFET M 1 (shown on left) in the common-source amplifier in Figure 5-4 to a 100 khz, 20mV peak-to-peak sinusoidal excitation at the gate of MOSFET M 1 (shown on right) Figure 5-9 and Figure 5-10 show the frequency response variation of the common-source amplifier in Figure 5-4 with device temperature varying from 0 C to 125 C and gate voltage, V G, varying from 1.1V to 1.6V, respectively. In both instances, the variation in gain in the frequency B. Madhavan Page 9 of 10 EE348L, Spring 2005
10 range of interest (100 Hz to 1 MHz) is 0.88 db (Figure 5-9) and 3.6 db (Figure 5-10) respectively. TEMP=0 C,gain=24.4 db TEMP=25 C,gain=24.17 db TEMP=75 C,gain=23.82 db TEMP=125 C,gain=23.52 db Figure 5-9: Temperature variation of frequency response of the common-source amplifier in Figure 5-4 V G =1.6V, gain = 24.6 db V G =1.4V, gain = 23.8 db V G =1.1V, gain = 21.0 db Figure 5-10: Gain variation of the common-source amplifier in Figure 5-4 due to variation in the gate voltage V G. 5.2 Conclusion In this biasing supplement, we have developed a systematic biasing procedure for a commonsource amplifier with a source-degeneration resistor. We related the relationship between the ac small-signal gain of the amplifier to the dc-bias voltages of the amplifier after making some design choices. We then used HSpice simulation to determine the drain current, I D, and transconductance, g m, of the MOSFET corresponding to the dc bias point for a desired ac smallsignal gain. The simulated ac small-signal gain of the complete amplifier, and the gain observed from transient simulation of the amplifier were found to be in excellent agreement with the initial calculations. The gain variation due to variation in device temperature and MOSFET gate bias voltage were also found to be less than 0.88 db and 3.6 db respectively. B. Madhavan - 10 of 10- EE348L, Spring 2005
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