(0.9 Voo) /85/ $ IEEE. An Efficient Timing Model for CMOS Combinational Logic Gates
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1 636 IEEE TRANSACTION S ON COMPUTER-AI D E D D E S IGN, VOL. CAO-4, NO.4, OCTOBER 1985 An Efficient Timing Model for CMOS Combinational Logic Gates CHUNG- YU WU, JEN-SHENG HWANG, CHIH CHANG, AND CHING-CHU CHANG Abstract-A new general timing model for CMOS combinational logic gates is proposed. In this model, the linearized large-signal equivalent circuit of a gate is first constructed. Then applying the dominant-poledominant-zero (DPDZ) method, the dominant pole of the equivalent circuit is calculated. Using this pole, the signal timing can be explicitly expressed. Comparisons between calculation results and simulation results are made and error analyses are performed. The worst-case error in characteristic-waveform timing can be confined to be within 35 percent for CMOS inverters, multi-input NOR gates or multi-input NAND gates with different device dimensions, capacitive loads, and device parameters. Better accuracy can be obtained for logic gates with commonly-used channel dimension or large capacitive load. For internal waveforms not deviating much from the characteristic waveforms, the worst-case uror in signal timing is not substantially increased. Applying the proposed timing model in an experimental timing simulator, the signal timing can be analyzed accurately and efficiently with reduced CPU time and memory. LIST OF SYMBOLS B Mobility correction parameter (SPICE device parameter). Cbdn(p) Bulk-drain p-n junction capacitance of an n-channel (p-channel) MOSFET. Cbsn( P ) Bulk-source p-n junction capacitance of an n-channel (p-channel) MOSFET. Cgdoun(p) Gate-drain overlap capacitance of an n channel (p-channel) MOSFET. Cgsoun(p) Gate-source overlap capacitance of an n channel (p-channel) MOSFET. CL Fixed load capacitance of a logic gate. Con(P) Channel oxide capacitance of an n-channel (p-channel) MOSFET. DELT A Channel width factor (SPICE device parameter). GAMMA Bulk threshold parameter in SPICE, which represents the proportionality factor relating the change in threshold voltage to backgate bias. Idn(p) Drain current of an n- channel (p-channel) MOSFET in large-signal model. Manuscript received October 8, 1984; revised January 8, This work was supported by ERSO, IT RI, Republic of China. C.-Y. Wu was with the Institute of Electronics, National Chiao-Tung University, Hsin-Chu, Taiwan, Republic of China. He is now with the Department of Electrical Engineering, School of Engineering and Applied Science, Portland State University, Portland, OR Y.-H. Yang is with the Institute of Electronics,-National Chiao-Tung University, Hsin-Chu, Taiwan, Republic of China. C. Chang and C.-C. Chang are with the Electronic Research and Service Organization. Industrial Technology Research Institute, Hsin-Chu, Taiwan, Republic of China. l o s DC drain current of an MOSFET. Leff Effective channel length of an MOSFET. NSUB Substrate Doping. Pier) Effective dominant pole in the fall (rise) characteristic waveform case. Dominant pole (zero) in the fall characteristic waveform case. Dominant pole (zero) in the rise characteristic waveform case. q Magnitude of electronic charge. Initial fall (rise) delay time. PId(Zfd) Prd(Zrd) tdi(r) T F(R) Fall (rise) time which is the time interval within which the output voltage lowers (raises) from 0.9 Voo (0.1 Voo) to 0.1 Voo (0.9 Voo). T ox Channel oxide thickness. Tp, Pair delay time which is the sum of fall del ay time and rise delay time. TpHL(LH) Fall (rise) del ay time which is the time interval between Vi = Voo to Va = Voo UCRIT Critical field for mobility degradation (SPICE device parameter). UEXP Critical field exponent in mobility degradation (SPICE device parameter). UEXPL (W) Correction factor of UEXP for short channel (narrow channel) case (SPICE device parameter). UO Surface mobility (SPICE device parameter). UOL(W) Correction factor of UO for short channel (narrow channel) case (SPICE device parameter). Vi(o) Input (output) large-signal voltage of a logic gate. V02(3) Large-signal voltage at internal nodes of a 3-input CMOS NOR gate. VBS(D) Bulk-source (drain) reverse bias of an MOSFET. Voo Power supply voltage. Drain (gate) source voltage of an MOS FET. Maximum drift velocity of carriers. Threshold voltage of an MOSFET under backgate bias. V TO Zero-bias threshold voltage of the MOS FET (SPICE device parameter). Weff Effective channel width of an MOSFET. VOS(GS) Vrnax VT /85/ $ IEEE
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