Alternative Channel Materials for MOSFET Scaling Below 10nm

Transcription

1 Alternative Channel Materials for MOSFET Scaling Below 10nm Doug Barlage Electrical Requirements of Channel Mark Johnson Challenges With Material Synthesis

2 Introduction Outline Challenges with scaling below 10nm What will the MOS device look like at 10nm Opportunities in alternative channels

3 nm Gate Length Devices 1995* 2005** 2015** Gate Length (nm) EOT (Å) EOT from Channel and Gate Electrode Gate Capacitance (µf/cm 2 ) Gate Oxide Leakage (A/cm 2 ) Power Supply (V) FAST Free Charge Density (µc/cm 2 ) Saturation Threshold Voltage (V) Ioff (µa/µm) NA 0.3 Ion (ma/µm) Relative Mobility Enhancement Full Depletion Enhancement Saturation Velocity Enhancement Parasitic Source/Drain (Ω*µm) Gate Delay (ps) Cutoff Frequency (GHz) Power Delay Product (aj/µm) Static Power Dissipation (µw/µm) NA * Technology for Advanced High-Performance Microprocessors M.T. Bohr, Y.A. El-Mansy, pp IEEE Transactions on Electron Devices ** ITRS Road Map 2004 Updates

4 Assumptions In this study of electrical performance of the channel we make the following assumptions Material synthesis challenges can be overcome given sufficient experimental resources Effective source-drain doping can be achieved Barrier dielectric can be achieved with unpinned interfaces Metal gates can be formed with work function from -3.5eV to -5.5eV Room Temperature to Room Temperature +150C preferred Evaluation channel properties to determine suitability for sub 10nm gate scaling

5 Fully Depleted FET Generic fully depleted architecture Source/Drain Carrier Supply Spacer Needs sufficient carriers with sufficient velocity Metal Gate --Tunable to eV Gate Dielectric nm Channel Spacer Substrate needs to be insulating Source/Drain Carrier Collector Can this be metal?

6 Fully Depleted FET Generic fully depleted architecture Metal Gate --Tunable to eV Source Gate Dielectric nm Channel needs to be intrinsic homogenous for V th control Drain Substrate needs to be insulating

7 Fully Depleted FET Source Metal Gate --Tunable to eV Gate Dielectric nm Channel Drain Substrate needs to be insulating Source G Drain Channel Depleted material must be able to hold off current in off state Must be able to maintain a large charge density at high velocities in on state V =1.0V V =0.0V Source and Drain resistance is dominant under these conditions

8 Key Considerations Figure of merit: Off Current On Current Non-ideal sub-threshold effects For relevance must be able to: Form unpinned gate dielectric barrier Tunable gate work function Source/drain doping

9 Off-On Potential Carrier will see the same on-off potential difference regardless of material On/off potential ratio is improved via subthreshold enhancement Improving the ratio means bringing subthreshold slope closer to ideal

10 Carrier Velocity 10nm Source Drain El ect r on Vel oci t yl ( V) On Sour ce Of f On Channel Lsp Spacer Lg Gat e X ( nm) Off Spacer v sat Dr ai n Ballistic Transport Mobility Ballistic transport achieved in off state Saturation velocity achieved in contact area

11 <v> vs. E Length Scale Switching 1µm 100nm 10nm Carbon Nanotube (Calculated Range for Small Diameter CNT) Electron Drift Velocity( 10 7 cm/s) InSb III-N offer the most significant advantage at relative gate lengths.

12 Scale Comparison Silicon GaN InSb

13 Collective Figure of Merit F t vs. Gate Length GaN InN InGaAs F t (GHz) 100 Si MOSFET InSb 10 AlGaN MOSFET Gate Length (microns)

14 Off Current High mobility is actually detrimental to off state performance. Ballistic transport is also not favored for off current performance Tunneling can limit performance if band gap is too small Intrinsic Carrier Concentration limits minimum I off

15 Conclusions Silicon is tough to beat Wider band gap can be better Smaller gate lengths achievable Mobility, saturation velocity and overshoot velocity can be misleading Larger density of states Maximize current density