# MOSFET & IC Basics - GATE Problems (Part - I)

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1 MOSFET & IC Basics - GATE Problems (Part - I) 1. Channel current is reduced on application of a more positive voltage to the GATE of the depletion mode n channel MOSFET. (True/False) [GATE 1994: 1 Mark] Soln. The MOSFET is of depletion mode and n channel type. Like JFET, depletion mode MOSFET is normally ON device. i.e. has drain current when VGS = 0 V In depletion mode MOSFETs drain current can exceed IDSS (not like JFETs) if the gate voltage is of correct polarity to increase number of charge carriers in the channel. For n channel D MOSFET, ID is greater than IDSS when VGS is positive. Since with more +ve voltage the channel becomes more n type Thus, false 2. MOSFET can be used as a (a) Current controlled capacitor (b) Voltage controlled capacitor (c) Current controlled inductor (d) Voltage controlled inductor [GATE 2001: 1 Mark] Soln. The MOS capacitor is the heart of MOSFET. The capacitance of the device is defined as C = d Q d V Where dq is differential change in charge on one plate as a function of dv. Thus, it can be used as voltage controlled capacitor Option (b)

2 3. The effective channel length of a MOSFET in saturation decreases with increase in (a) Gate voltage (c) Source voltage (b) Drain voltage (d) Body voltage [GATE 2001: 1 Mark] Soln. In a MOSFET at the onset of saturation i.e. when drain to source voltage reaches VDSat the inversion layer charge at the drain end becomes zero (ideally). The channel is said to be pinched off at the drain end. If drain to source voltage VDS is increased even further beyond the saturation i.e. VDS > VDSat an even larger portion of the channel becomes pinched off, and effective channel length is reduced. (REF: Streetman) Option (b) 4. For an n channel enhancement type MOSFET, if the source is connected at a higher potential than that of the bulk (i.e. V SB > 0), the threshold voltage V T of the MOSFET will (a) Remain unchanged (b) Decrease (c) Change polarity (d) Increase [GATE 2003: 1 Mark] Soln. So for we considered that substrate or body is connected to source and held at ground. V SB 0 For n channel device VSB be +ve i.e. (change in threshold voltage) V T is always positive. So as VSB > 0, the VT will increase. REF: NEAMAN Option (d) 5. A MOS Capacitor made using p type substrate is in accumulation mode. The dominant charge in the channel is due to the presence of (a) Holes (c) Positively charged ions (b) Electrons (d) Negatively charged ions

3 Soln. MOS Capacitor is mode using p type substrate when gate is supplied with negative voltage i.e. VGS < 0. It will be in accumulation mode. In this case it attracts holes beneath the gate, therefore the charge in the channel is due to holes. Option (a) 6. The drain current of a MOSFET in saturation is given by I D = K (V GS V T ) 2, where K is a constant. The magnitude of the transconductance g m is (a) K(V GS V T ) 2 V DS (b) 2K(V GS V T ) Soln. Given, Drain current of MOSFET in saturation Since, I D = K (V GS V T ) 2 Transconductance (g m ) = I D V GS I D V GS = K. 2. (V gs V T ) Option (b) = 2K(V gs V T ) I D (c) V GS V DS (d) K(V GS V T ) 2 V GS [GATE 2008: 1 Mark] 7. At room temperature, a possible value for the mobility of electrons in the inversion layer of a silicon n channel MOSFET is (a) 450 cm 2 / V s (c) 1800 cm 2 / V s (b) 1350 cm 2 / V s (d) 3600 cm 2 / V s [GATE 2010: 1 Mark] Soln. The mobility of electrons is the standard value, it will be same for electrons in the inversion layer

4 Option (b) 8. In the circuit shown below. For the MOS transistors, μ n C OX = 100 μa/v 2 and the threshold voltage V T = 1 V. The voltage V X at the source of the upper transistor is 6 V W/L = 4 V x W/L = 1 (a) 1 V (b) 2 V (c) 3 V (d) 3.6 V [GATE 2011: 1 Mark] Soln. Assume, Top MOSFET as M1 Bottom MOSFET as M2 M1 is in saturation since V G > V T (Here VG is and VT is 1 V) Since MOSFET are connected in series the same current will flow through M2

5 6 V M 1 (W/L) 1 = 4 V x M 2 (W/L) 2 = 1 Drain current for M1 in saturation is I DS1 = 1 2 μ n C OX ( W L ) 1 (V GS1 V T ) 2 Similarly for M2 I DS2 = 1 2 μ n C OX ( W L ) (V GS2 V T ) 2 2 Since, I DS1 = I DS2 ( W L ) (V GS1 V T ) 2 = ( W 1 L ) (V GS2 V T ) 2 2 V GS1 = V G V x = 5 V x 4(5 V x V T ) 2 = 1. (V x V T ) 2 or, 2(5 V x V T ) = (V x V T ) or, V x = 3V Answer:- V x = 3V

6 9. In a MOSFET operating in the saturation region, the channel length modulation effect causes (a) An increase in the gate source capacitance (b) A decrease in the transconductance (c) A decrease in the unity gain cut off frequency (d) A decrease in the output resistance [GATE 2013: 1 Mark] Soln. For a MOSFET operating in saturation region the channel length modulation effect causes a decrease in output resistance. The drain characteristics becomes less flat. Option (d) 10. In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation (using steam or water vapour) produces (a) Superior quality oxide with a higher growth rate (b) Inferior quality oxide with a higher growth rate (c) Inferior quality oxide with a lower growth rate (d) Superior quality oxide with a lower growth rate [GATE 2013: 1 Mark] Soln. A superior quality oxide layer is formed with dry oxidation but with a lower growth rate. Option (d) 11. In following circuit employing pass transistor logic, all NMOS transistor are identical with a threshold voltage of 1V. Ignoring the body effect, the output out-put voltage at P, Q and R are P Q R

7 (a) 4 V, 3 V, 2 V (b),, Soln. Assume all NMOS are in saturation (c) 4 V, 4 V, 4 V (d), 4 V, 3 V [GATE 2014: 1 Mark] M 1 P M 2 Q M 3 R V DS (V GS V T ) For M1: (5 V P ) (5 V P 1) or, 5 V P > 4 V P Thus in saturation I D1 = k(v GS V T ) 2 or, I D1 = K(4 V P ) 2 (1) For M2: I D2 = K(5 V Q 1) 2 or, I D2 = K(4 V Q ) 2 (2) Since I D1 = I D2 (4 V P ) 2 = (4 V Q ) 2

8 or, V P = V Q and V P + V Q = 8 or, V P = V Q = 4V For M3: I D3 = K(5 V R 1) 2 or, I D2 = I D3 (4 V Q ) 2 = (4 V R ) 2 or, V R = V Q = 4V Thus, V P = V Q = V R = 4V Option (c) 12. If fixed positive charges are present in the gate oxide of an n channel enhancement type MOSFET, it will lead to (a) A decrease in the threshold voltage (b) Channel length modulation (c) An increase in substrate leakage current (d) An increase in accumulation capacitance [GATE 2014: 1 Mark] Soln. In n channel enhancement type MOSFET, a positive voltage is applied at the gate which creates channel between source and drain. In the problem it is given that fixed positive charges are present in the gate oxide, it will make easier to create the channel between source and drain. Hence the threshold voltage will decrease. Option (a) 13. In CMOS technology, shallow P well or N well regions can be formed using (a) Low pressure chemical vapour deposition (b) Low energy sputtering (c) Low temperature dry oxidation (d) Low energy ion implantation [GATE 2014: 1 Mark]

9 Soln. In triple well CMOS process a deep n well is first driven into the p type substrate, and is used as shielding frame against disturbances from the substrate and provides N channel MOSFET with better insulation from noise. The process used is low energy ion implantation. Option (d) 14. In MOSFET fabrication, the channel length is defined during the process of (a) Isolation oxide growth (b) Channel stop implantation (c) Poly silicon gate patterning (d) Lithography step leading to the contact pads [GATE 2014: 1 Mark] Soln. In MOSFET fabrication channel length is defined during Poly silicon gate patterning process. Option (c) 15. Which one of the following processes is preferred to from the gate dielectric (SiO 2 ) of MOSFETs? (a) Sputtering (c) Wet oxidation (b) Molecular beam epitaxy (d) Dry oxidation [GATE 2015: 1 Mark] Soln. In wet oxidation where water is used instead of oxidation process has significantly greater oxidation rate than dry oxidation. It is used to grow thick oxides such as masking oxides. Dry oxidation has a lower growth rate than wet oxidation although oxide film quality is better than wet oxide film. It is used in transistor gates and capacitances and especially in gate oxide in MOSFETs Option (d) 16. Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET): P: As channel length reduces, OFF state current increases. Q: As channel length reduces, output resistance increases. R: As channel length reduces, threshold voltage remains constant.

10 Soln. P: S: As channel reduces, ON current increases. Which of the above statements are INCORRECT? (a) P and Q (b) P and S (c) Q and R (d) R and S [GATE 2016: 1 Mark] As channel length reduces, OFF state current increases. The drain current is in saturation since it does not increase, but when channel length is reduced the drain current will increase slightly. This effect is called drain induced banner lowering (DIBL). This state is the OFF state (High resistance state): So, it is TRUE Q: As channel length reduces output resistance increases. The output resistance reduces with channel length reduction So, TRUE R: As channel length reduces, threshold voltage remains constant. As channel length reduces. S: As channel reduces, ON current increases TRUE Option (c) 17. A long channel NMOS transistor is biased in the liner region V DS = 50 mv and is used as a resistance. Which one of the following statements is NOT correct? (a) If the device width W is increased, the resistance decrease. (b) If the threshold voltage is reduced, the resistance decreases. (c) If the device length L is increased, the resistance. (d) If V GS is increased, the resistance increases. [GATE 2016: 1 Mark] Soln. Liner region of NMOS is the region of low resistance (on region). The equation is

11 1 r ds(on) = μ n C OX. W L [V GS V T ] Thus, as per above equation A: TRUE B: TRUE C: TRUE D: FALSE Option (d) is correct 18. The figure shows the band diagram of a Metal Oxide Semiconductor (MOS). The surface region of this MOS is in E c φ s φ B E i E F (a) Inversion (b) Accumulation (c) Depletion (d) Flat band [GATE 2016: 1 Mark] Soln. The given band diagram of a Metal Oxide Semiconductor. Note that Fermi level of semiconductor is between intrinsic level and conduction level (near to EC) so the semiconductor is of n type.

12 Whenever surface potential ( φ s ) is larger than, QB surface is inverted. Thus the surface region of MOS is in inversion. Option (a)

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