ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

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1 ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment Slide: 1

2 Review of Last Lecture Semiconductor technology trend and Moor s law Benefits of transistor scaling: More functionality in the same foot print Faster device Devices with less switching energy Less cost/function Challenges of transistor scaling: Device size reaching quantum level Power dissipation and heat removal concerns Interconnect worsen by scaling Manufacturing yield issues Slide: 2

3 Today s Lecture Overview of Diode Physics BASIC MOS Physics: Understanding of device operation Basic device equations for long channel MOSFET Long channel MOS models for manual analysis Slide: 3

4 Reading Assignment Today we will review Chapter 3 (MOS Physics) Skim through Diodes but focus on Section (diode transient behavior) Study Section 3.3 (MOS transistor) thoroughly Slide: 4

5 The Diode B Al A SiO 2 p n Cross-section of pn -junction in an IC process A p n B One-dimensional representation Al A B diode symbol Slide: 5

6 Depletion Region hole diffusion electron diffusion p n (a) Current flow. hole drift electron drift Charge Density - + x Distance (b) Charge density. Electrical Field x (c) Electric field. Potential V -W 1 W 2 x (d) Electrostatic potential. Built-in potential Slide: 6

7 Forward Bias Diode p n (W 2 ) p n0 L p n p0 p-region -W 1 0 W 2 n-region x diffusion Typically avoided in Digital ICs Slide: 7

8 Reverse Bias Diode p n0 n p0 p-region -W 1 0 W 2 n-region x diffusion The Dominant Operation Mode Slide: 8

9 Diode IV Curve Slide: 9

10 ECE520 - Lecture 2 Slide: 10 University of New Mexico Junction Capacitance 2 i D A 0 n N N Ln q KT 1 0 D A D A si D j0 N N N N 2 q A C Built-in potential

11 Diffusion Capacitance T KT q Thermal Potential Slide: 11

12 What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D Slide: 12

13 MOSFET Top & Cross Section View Metal Oxide Semiconductor Field Effect Transistor Slide: 13

14 NMOS Device Cross-Section I DS is Defined as from Drain to Source Current Majority carriers are electrons NMOS device conducts when gate-to-source voltage is positive I DS is as a function of: Channel width (W) Inverse of channel length (1/L) Gate-to-source potential (V GS ) Source Gate Bulk Drain Slide: 14

15 PMOS Device Cross-Section Complement of NMOS Built inside an N-well implant in substrate Majority carriers are holes, not electrons Conducts when gate-source voltage is negative Gate Source Bulk Drain Slide: 15

16 Device Operation: Cutoff Cutoff region (V GS = 0 ) The Source to Drain connection looks like two back to back series connected diode Therefore ideally I DS = 0 1 st order approximation only V GS =0 Slide: 16

17 Gate Oxide Capacitance Polysilicon gate forms a conductive top plate of a capacitor Gate oxide forms the dielectric of a parallel plate capacitor P-doped substrate forms the conductive bottom plate of a capacitor Slide: 17

18 Device Operation: Depletion As gate potential increases Positive majority carriers (holes) in the substrate repelled from the surface (depleting the material of carriers) A depletion region is formed under the surface of the gate This depletion region is formed as potential at the silicon surface underneath the gate reaches φ F F KT q Ln N n i A small V GS Slide: 18

19 Device Operation: Inversion As the surface potential beneath the gate increases beyond φ F Electrons from heavily doped source and drain are attracted to the gate and move into the channel When the surface potential reaches 2φ F the charge density of electrons in the channel equals the original doping density of the P-substrate At this time the channel is inverted Therefore, a conductive path is formed between source and drain Large V GS Slide: 19

20 Device Operation: Inversion Inversion region is simply a resistor We need an applied V DS to get current flow When drain voltage is applied the depletion region grows at the drain junction Large V GS Slide: 20

21 MOSFET Band Diagram Slide: 21

22 MOSFET Threshold Voltage five V GS component accounted for threshold adjustment implant Slide: 22

23 MOSFET Threshold Voltage Components V T 0 2 ms F Q C B ox Q C SS ox? QI C ox F KT q Ln N n i A Slide: 23

24 MOSFET Threshold Voltage Components Q ox Slide: 24

25 MOSFET Threshold Voltage Components V T 0 2 ms F Q C B ox? Q C SS ox Q C I ox F KT q Ln N n i A Slide: 25

26 MOSFET Threshold Voltage Components Q B = V B 2qN 2 A C si ox F Slide: 26

27 MOSFET Threshold Voltage Components V T 0 ms 2 F 2qN A C ox si 2 F Q C ox ox Where: F KT q Ln N n A i and C ox t ox ox But what happen Bulk and Source are at different potential? Slide: 27

28 Body Effect V B 2qN A 2 si C ox F V SB Slide: 28

29 Body Effect V T V T 0 2 F VBS 2 F V T (V) Key Point: Body effect raises V T V (V) BS Why does this matter? In a stack (such as NMOS in a NAND gate) the sources of higher devices in the stack do not equal 0V due to resistance of the lower transistors - this results in lower current drive (lower Ids) due to higher apparent V T Single polarity pass gates can only bring the drain to V DD -V T Body bias can be purposely created to lower standby power by modulating I OFF Slide: 29

30 Current Voltage Relation I D = -v n Q(x)W Slide: 30

31 Current Voltage Relation W Slide: 31

32 Device Operation: Linear Region Slide: 32

33 Device Operation: Saturation Slide: 33

34 Device Operation: Saturation Slide: 34

35 Device Operation: Saturation Slide: 35

36 Linear into Saturation Slide: 36

37 Saturation Region Slide: 37

38 Saturation Region Slide: 38

39 Saturation Region Analogy Slide: 39

40 MOSFET Parameter Measurement Slide: 40

41 MOSFET Parameter Measurement Slide: 41

42 Channel Length Modulation Slide: 42

43 Channel Length Modulation Slide: 43

44 Device Operation: I-V curves I DS 2 W V K n GS T DS 1 L 2 DS V V V V DS I DS K 2 W L 2 V V V n GS T 1 DS V DS V GS V T V DS V GS V T I DS [ma] V DS Slide: 44 [V]

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