Fundamentos de Electrónica Lab Guide

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1 Fundamentos de Electrónica Lab Guide Field Effect Transistor MOS-FET IST-2016/ nd Semester

2 I-Introduction These are the objectives: a. n-type MOSFET characterization from the I(U) characteristics. Extraction of the model parameters. b. pplications: use of the MOSFET as a logic gate and as na amplifier. Comparison with the results obtained by simulation. c. Enhance the link between the device models used in industry of integrated circuits CMOS (Complementary metal oxide semiconductor) Technologyand the physical principles. The PCB is represented in Fig. 1. Fig.1 The FET is obtained from the integrated circuit (IC) HEF4007, Fig.2. This IC of CMOS technology contains three n-channel MOSFET (NMOS) and three p-channel MOSFET (PMOS). The body of the transistors is the p substrate of the IC. In the substrate it is implanted a n region that will constitute the common body of the PMOS transistors. This p-n junction and all the other secondary junctions should not be forward-biased. Therefore, the p substrate is related to the lowest potential of the IC (V SS ) and, on the other hand, the n body is related to the highest potential (V ). V SS and V will ensure, for the dynamical situation, a small impedance path to the referential potential of the IC. In this lab work we will use only one n-channel MOSFET, the N2(NMOS) with terminals drain-n2(5), gate-g2(3), source-sn2(4) and body-v SS (7). The p-type MOSFET will not be used. In order that the body of those transistors does not fluctuate, a 1µF capacito ris placed between terminal 14 (V ) and terminal 7(V SS ). 1

Fig.2- Representation of IC HEF4007 along with its functional scheme. II-ctivity pre-lab II.1 Transistor characterization Consider the bias circuit of transistor M1 of Fig.

3 Fig.2- Representation of IC HEF4007 along with its functional scheme. II-ctivity pre-lab II.1 Transistor characterization Consider the bias circuit of transistor M1 of Fig.3, where the potentiometer constituted by R G1 e R G2 fixes the gate potential R 1 = 150kΩ, R = 5,1k Ω, RS = 5,1k Ω, RL = 1M Ω e V = 20V. Below you can find the 1st order model used for the theoretical analysis and the PSPICE simulation of the transistor. Consider that the parameter of the theretical model is defined as = K W / L. In order to use this model in the simulation, select p the transistor MbreakN4 of the symbol list of the Schematics, edit the respective model with edit>model>edit instance Model (Text.), and with Copy/Paste replace it by the model of N4007. G Fig.3 2

4 MOEL FOR PSPICE.model N4007 NMOS(Level=1 Kp=438u Vto=1.3 Lambda=.01 W=30u L=10u Gamma= 2 Xj=0 Tox=1200n Phi=.6 Cbd=2.0p Cbs=2.0p Pb=.8 Is=16.64p N=1 Cgso=.1p Cgdo=.1p) *$. Calculate analytically R G2 in order that U GS =2.5V (use the approach lambda=0). Indicate the values of the MOS quiescent point and calculate the values of the incremental parameters g m, r ds and c gs.consider ε ox = 3,96ε 0. B. raw the incremental equivalent circuit for the circuit of Fig. 3. Calculate the incremental gain G = VO / VG = vo / vi assuming that for the operating frequency the MOS capacitive effects are negligible and the impedance of the circuit capacitors are negligible. C. raw the scheme of Fig.3. in Schematics of PSPICE with the inclusion of the above model indicated for the n-channell MOSFET (N4007) with the body terminal linked to the source. Consider CG = CL = CS = 3, 3µ F RL = 1M Ω and the vi generator of the type VSIN with VOFF=0, VMPL=100mV and FREQ=1kHz. 1. C nalysis. Calculation of the quiescent point Enter in Setup nalysis, activate Bias Point etail and Temperature to analyze the situation with T = 27ºC and T = 40ºC. Consulting the output file, justify the found diferences. Only for 27ºC, indicate the incremental parameters g m, r ds and c gs. 1. Transient analysis for incremental components Enter in Setup nalysis. ctivate Transient. nalyze the transiente regime during 5ms with a step(step ceiling) of 10us. i. Obtain a copy of the voltage waveforms in the gate and in the drain terminals. ii. Calculate the amplifier voltage gain G = VO / VG = vo / vi and the mean value of output voltage v O. iii.link the body terminal to the earth. What is the new value for the gain? Justify.. Execute the analysis of the transient regime for an amplitude voltage of the input voltage vi equal to 1,5V when U BS =0. Show vi, v GS and v S (for v GS and v S use (Marker Voltage ifferential). Indicate the values of the inpu voltage that cut the transistor. 3

5 II.2 Transfer function in a common source circuit 1. raw the circuit of Fig.5 in Schematics using PSPICE. Consider V=10V and replace v I by a C source VI. Consider the range 0 V I 10V: a) Obtain v O (v I ), sign the points in the boundaries between zones and trace the line vs = vgs VT relative to the boundary triode/saturatione. III-Lab activity b) Obtain the graphic of the incremental gain G=dv O /dv I as function of v I, entering in dd>dd Trace of PSIPCE /, activating the function () and choosing v O as argument. c) Iindicate the intervals of the input voltage where the transistor can be considered a logic gate.( dv O /dv I <1). III.1 Calculation of V T, =K p W/L for a n-type MOS In saturation: 1 W i = ( vgs VT ) = K p ( vgs VT ) for vgs VT (1) 2 2 L where V T is the threshold gate-source voltage and Kp is the transcondutance parameter. s i is linearly dependent on v GS, the value of V T may be obtained with the intersection with x-axis and the slope of the line allows the calculation of / 2. The linear zone of the experimental graphic in the plane i vgs corresponds to the strong inversion in the channel of the MOSFET. Procedure: 1. Establish the electric connections of the circuit of Fig.4.a, (pay attention to the shunts S1 and S2). Voltage V is obtained from PS503. The amperimeter is M502 with the selection: function m > C, range 20m input terminal m and output LOW. The voltmeter V is also M502 with: function VOLTS >C, range 20V and terminals VOLTS/-LOW. 2. Vary gate voltage VGS = VS from 0 to 7V with a step of 0,5V until 3V and a step of 2V from 3 until 7V. Record the measured values and the values for the drain current. Goes on the lab procedure passing to point 1 of III.2 establishing the required modifications. 3. From the graphic obtained in the plane i vgs and using the line that better matches the behavior in the strong inversion zone of the MOSFET, calculate the transistor parameters, V T and Kp(assume W/L=3). 4. Calculate di dvgs when VGS = VS = 2, 5V. 4

6 R = 680Ω 1 R = 5.1kΩ 1 G V S B S1 + _ V S3 G S B S1 V + _ V RS = 5,1k Ω S2 (a) 0 2 Rg = 12kΩ + _ V G R S (b) S2 0 Fig.4-a) Transistor as a two terminal device. b) Transistor bias with two independente C sources. III.2 Calculation of the body effect parameter γ In the cases that the body terminal is accessible and not shorted with the source terminal, the application of a voltage U BS leads to a modification of the threshold gate-source voltage, according to: 1/ 2 1/ 2 VT = γ ( φsinv U BS ) φ Sinv (2) where φsinv is the channel inversion voltage, generally assumed as 0.6V. Procedure: 1. Consider VGS = VS = 5V in the circuit of Fig. 4.a. Eliminate the shunt S2 and record the new value of the drain current. Put again the shunt, switch off the generator and pass to the point 1 of III.3 making the required modifications. 2. Calculate U BS in this circuit and also the new value for V T that matches the equation (1) and the value of γ. III.3 etermination of r ds λ and g m for the n-type MOSFET When considering the modulation of the channel length λ, the saturation current depends also on U S, according to: i ( ) 2 = vgs Vt (1 + λvs ) (4.3) 2 The incremental output resistance is then given for a quiescent point (V GS0, V S0 ) and for a constant V GS constant by the equation 5

7 r ds -1 i 1 V = = v λi I V I S S V GS (4.4) The incremental resistance and the Early parameter V are the obtained from the line that matches the experimental characteristic I VS in the vicinity of a given V S in the saturation zone assuming that V GS is constant. The incremental resistance is the inverse of the line slope and the parameter V is obtained from the intersection of this line with the x-axis (I = 0, V S = -V ). For a given V S0 and for a constant V GS the incremental transconductance is given by: di 2I gm = 2I dvgs V V GS Vt S (4.5) I V GS Procedure: 1. Eliminate the conductor that links terminal to terminal G in the circuit of Fig. 4.a and, as seen in Fig. 4.b, establish the link from drain to the resistor R = 5,1k Ω. Link point 2 of the circuit to the generator VG in order that V GS =2,5V. 2. Measure the current in amperimeter and the voltage V S in voltmeter V and vary V in order that V S change from 0 to 2V with a step of 0,5V and from 3V to 7V with a step of 2V. Record the obtained values. 3. Record also I for V S =3V and V GS =3V. 4. Calculate, according to the definition, the incremental parameters g m, r ds and λ for a quiescent point V GS =2,5V and V S =3V. III.4 Transfer characteristic The circuit shown in Fig.5 is used to exemplify the application of the MOSFET either as an inverter or an amplifier. In a common source circuit. The slope of the curve v GS -v S represents the amplifier differential gain. The negative signal of dv S /dv GS shows that besides amplifying the circuit also makes an inversion of the input voltage. The region where the derivative is in modulus greater than 1 has applications in the area of nalogical Electronics as a linear amplifier. The regions where the derivative is lower than 1 has applications in the area of igital Electronics. Procedure: 1. Previously to the establishment of the electric connections, see the input voltage v I in the channel 1 of the oscilloscope. This signal is obtained from the signal generator FG503 rotating the knob FUNCTION in the counterclockwise in 6

8 Powered by TCPF ( Fundamentos de Electrónica 5 th Lab Work order to select the sinusoidal wave with C OFFSET. Next, adjust the following specifications: V offset =5V, V pic-to-pic =10V, frequency=100hz. 2. Switch on PS503 and, with the voltmeter, make sure that the voltage at the terminals is V=10V. 3. Establish the electric connections shown in Fig. 5 with all the instruments switched off. 4. Obtain a copy of v I (t), v O (t) and v O (v I ). 5. Indicate on that characteristic the values of v I that correspond to the different zones in the MOSFET. Trace the line that is tangent to the curve in v I = 2,5V. For that point calculate the incremental voltage gain G V = dv O /dv I and calculate the transistor transconductance (g m ). R = 5,1k Ω Rg = 12kΩ G v O S B Osc.-Ch-2 + _ V ~ v G Osc.-Ch-1 Fig 5 Common source circuit. 7

ECEN3250 Lab 9 CMOS Logic Inverter

ECEN3250 Lab 9 CMOS Logic Inverter Lab 9 CMOS Logic Inverter ECE Department University of Colorado, Boulder 1 Prelab Read Section 4.10 (4th edition Section 5.8), and the Lab procedure Do and turn in Exercise 4.41 (page 342) Do PSpice (.dc)