VLSI Design I. The MOSFET model Wow!

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VLSI Design I The MOSFET model Wow! Are device models as nice as Cindy? Overview The large signal MOSFET model and second order effects. MOSFET capacitances.

1 VLSI Design I The MOSFET model Wow! Are device models as nice as Cindy? Overview The large signal MOSFET model and second order effects. MOSFET capacitances. Introduction in fet process technology Goal: You can use the large signal equivalent MOS device equation. You are familiar with second order effects like body effect, channel length modulation. You know the MOS capacitances. You know the basic steps in MOS fabrication. MicroLab, VLSI-2 (1/24)

2 Let s build a MOSFET There are lots of different recipes to choose from. Like most things in life, you get what you pay for: the ability to have good bipolar devices, radiation hardness, reduced latch-up and substrate noise, are all extra cost options. We ll consider a general process: bulk CMOS with a p-type substrate: Use <100> surface to minimize surface charge 500um slice of a silicon ingot that has been doped with an acceptor (typically boron) to increase the concentration of holes to /cm /cm 3. p-type Back is metalli lized to provide a good ground connection. Good for n-channel fets, but p-channel fets will need a n-type well (or tub) to live in! MicroLab, VLSI-2 (2/24)

3 Next, a thick (0.4um) layer of silicon dioxide, called field oxide,, is formed on the surface by oxidation in wet oxygen. This is then etched to expose surface where we want to make a mosfet: Now grow a thin (0.01um = 100 Å) layer of silicon dioxide, called gate oxide, on the surface by exposing the wafer to dry oxygen. p The gate oxide needs to be of high quality: uniform thickness, no defects! The thinner the gate oxide, the more oomph the fet will have (we ll see why soon) but the harder it is to make it defect free. p MicroLab, VLSI-2 (3/24)

4 On top of the thin oxide a 0.7um thick layer of polycrystalline silicon, called polysilicon or poly for short, is deposited by CVD. The poly layer is patterned and plasma etched (thin ox not covered by poly is etched away too!) exposing the surface where the source and drain junctions will be formed: gate oxide (only under poly) poly wires field oxide exposed surface for source and drain junctions p Poly has a high sheet resistance (25 ohms/square) which can be reduced by adding a layer of a silicided refractory metal such titanium (TiSi 2 ), tantalum (TaSi 2 ) or molybdenum (MoSi 2 ). These have sheet resistances of 1, 3 or 5 ohms per square, respectively. This is great for memory structures that have lots of poly wiring. MicroLab, VLSI-2 (4/24)

5 The entire surface is doped, either by diffusion or ion implantation, with phosphorus (an electron donor) ) which creates two n-type regions in the substrate. The phosphorus also penetrates the poly reducing its resistance and affecting the nfet s threshold. diffusions are self-aligned with poly n+ n+ n+ wires: ohms/sq. p Finally an intermediate oxide layer is grown and then reflowed to flatten its surface. Holes are etched in the oxide (where contacts to poly/diff are wanted) and aluminum deposited, patterned and etched. metal wires (0.08 ohms/square) diff contact ( ohms) 10 ohms) n- channel MOS field effect transistor! MicroLab, VLSI-2 (5/24)???

6 NFET Operation Picture shows configuration when Vgs < Vto S G D I ds ds = 0 n+ n+ p mobile holes, fixed negative ions depletion layer no mobile carriers, but fixed negative ions (slight intrusion into n+, but mostly in p area) Other symbols: G B mobile electrons, fixed positive ions (n+ means heavily doped with donors, doesn t imply positive charge!) Terminal with higher voltage is labelled D, the other is labelled S so Ids >= 0. S D B almost always ground MicroLab, VLSI-2 (6/24)

7 FET = field effect transistor The four terminals of a fet (gate, source, drain and bulk) connect to conducting surfaces that generate a complicated set of electric fields in the channel region which depend on the relative voltages of each terminal. Picture shows configuration when Vgb > Vto gate inversion happens here source E h E v drain bulk INVERSION: A sufficiently stron ong vertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain. CONDUCTION: If a channel exists, a horizontal field will cause a drift current from the drain to the source. Expect Ids proportional to Vds*(W/L)? MicroLab, VLSI-2 (7/24)

8 Threshold voltage The gate voltage required to form the channel is called the threshold voltage.. Many factors affect the gate-source voltage at which the channel becomes conductive. Threshold voltage for source-bulk voltage zero: V = V + V TO t ms fb V TO ONQNU ONQNU Q b Q fc = 2φ F + + φms C C ox ox ε ox t ox 0.61V for n-channel -0.61V for p-channel kt 2 q N ln n A i 2ε q 2φ si N A kt q F NDN ln 2 n i A MicroLab, VLSI-2 (8/24)

9 Body effect (second order) As V sb increases, the depth of the depletion region increases, exposing more of the fixed acceptor (i.e. negative) ions in the substrate. Thus the second term in the threshold voltage equation on the previous slide increases from to 2ε qn si 2ε qn si A A 2Φ ( V + 2Φ ) sb F F the threshold voltage of the n-channel transistor is now: V ( V + 2Φ Φ ) tn = V tn0 + γ sb F 2 F γ = 2ε qn C si ox A As we ll see, this effect comes into play in series-connected fets where only one of the fets will have V sb = 0 and the other fets will have V sb > 0 and a higher threshold voltage. V t2 t2 > V t1 t1 T 2 T 1 V sb >0 V sb =0 MicroLab, VLSI-2 (9/24)

10 Basic DC equations MOS transistors have 3 regions of operation: cutoff region (subthreshold subthreshold) linear region (triode region) saturated region (active region) polysilicon gate S i O 2 source diffusion drain diffusion W L Cutoff or subthreshold region: V gs <= I ds = 0 <=V t There is still a small current described in the second order effects (weak inversion). Important to model for analog circuits: I V ds ds MicroLab, VLSI-2 (10/24)

11 Linear operating region V s V gs gs >V t 0 < V ds ds <V dsat Ids L Larger Vgs creates deeper channel which increases Ids channel length is almost always min allowable mobility (u > u n p ) Larger Vds increases drift current but also reduces vertical field component which in turn makes channel less deep. Channel will pinch-off, when V ds ds = V gs -V t = V dsat gs fet gain factor k=µc ox ox dsat I ds W µε = ox ( V V ) gs t V ds L t ox max value at V ds = V dsat, but then channel is pinched off (see next slide) 2 ds V 2 only linear when V ds is small, otherwise parabolic MicroLab, VLSI-2 (11/24)

12 Saturated operating region V s V gs >V t V dsat <V ds Ids Voltage at channel end remains essentially constant at V dsat so drift current also remains constant: device is in saturation. Electrons arriving from source are injected into drain depletion region and accelerated towards drain by field proportional to V ds -V dsat usually reaching the drift velocity limit. I ds W µ ε 2L t ( sat ) = ox ( V V ) gs t ox 2 this is just I ds from previous slide evaluated at V ds = V dsat ds dsat MicroLab, VLSI-2 (12/24)

13 Channel-length length modulation (second order) V s V gs >V t V dsat <V ds Ids L = L - dl dl This looks just like a fet with a channel length of L < L. Shorter L implies greater I ds... ds As V ds increases, dl get larger As V ds increases the effective channel length gets shorter so I ds (sat) increases. dl is proportional to V ds V dsat but most people approximate channel length modulation as a linear effect: I ds W 2L µ ε t ( sat ) ox ( V V ) 2 = ( 1 + λv ) ox gs t ds MicroLab, VLSI-2 (13/24)

14 NFET Ids curves Put it together and what have you got? plot of Ids vs. Vds for Vgs = 0,1, 2, 3, 4 and 5V Can you find the following in the plot? I ds vs. V ds when V gs = 0V I ds vs. V ds when V gs = 5V value of V t value of V dsat evidence of body effect evidence of channel length modulation MicroLab, VLSI-2 (14/24)

15 SPICE Models There are different models used in circuit simulators: level 1 is our simple model including the most important second order effects described level 2 model is based on device physics level 3 is a semi-empirical empirical model allowing to match equations to the real circuit: : example BSIM model from Berkeley models subthreshold characteristics summary of the main SPICE DC parameters used in all three models at the end of this chapter. M nfet W=1u L=0.5u AS=1p AD=1p PS=3u PD=3u...MODEL nfet NMOS +TOX=1E-8 +CGB0=345p CGS0=138p CGD0=138p +CJ=775u CJSW=344p MJ=0.35 MJSW=0.26 PB= MicroLab, VLSI-2 (15/24)

16 MOSFET Capacitance Estimation the dynamic response of MOS systems strongly depends on the parasitic capacitances associated with the MOS device. The total load capacitance on the output of a CMOS gate is the sum of: gate capacitance (of other inputs connected to out) diffusion capacitance (of drain/source regions) routing capacitances (output to other inputs) gate C gd drain C db substrate C gs C gb source C sb gate source C gs C gb channel depletion layer C gd t ox drain C sb C db substrate MicroLab, VLSI-2 (16/24)

17 MOSFET gate capacitances Cg = Cgd + Cgs + Cgb Oxide-related capacitances come in two forms: overlap capacitance (extrinsic) since gate slightly overhangs diffusions and bulk: C(overlap) = W L D C ox ox C(overlap) = 2L CGB0 channel-charge charge related capacitances (intrinsic): cut-off: Cgb = C ox W L Cgs = Cgd = 0 linear: for both Cgs and Cgd for Cgb saturation: amount of overlap Cgb = 0 Cgs = Cgd = 0.5 C ox W L Cgb = 0 Cgd = 0 Cgs = 0.67 C ox W L shielded by channel equally shared between S and D note capacitive coupling of gate and drain/source channel pinched off channel shortened ox for SPICE Cgs = W CGS0 Cgd = W CGD0 Cgb = 2L CGB0 ox MicroLab, VLSI-2 (17/24)

18 MOSFET diffusion capacitances Junction capacitances C db and C sb are a function of the applied terminal voltages and diffusion dimensions: source/drain diffusion x j channel sidewall faces channel bottom junction faces p-type substrate zero-bias C/unit area of bottom junction area of diffusion negative for reverse biased C diff built-in in junction potential C ja = Vj 1 Vb Mj C jsw P + Vj 1 Vb grading coeff. sidewalls face p+ channel stop zero-bias C/unit length of sidewall junction perimeter of diffusion Mjsw grading coeff. junction voltage MicroLab, VLSI-2 (18/24)

19 P-channel MOSFETs S G D p+ p+ n p threshold voltage is negative since we need attract holes to form inversion layer B PFET is built inside its own substrate : a n-type well or tub diffused into p-type bulk substrate. Don t forget well contacts! Other symbols: G Terminal with lower voltage is labelled D, the other is labelled S S off: V gs > V t lin: V gs >V t, V ds sat: V gs >V t, V ds gs ds >V gs -V t ds <V gs -V t B D n-well always connected to Vdd to keep pn junction back-biased biased MicroLab, VLSI-2 (19/24)

20 Depletion-mode MOSFETs S G D n+ n+ p channel doped with donors B to give negative threshold voltage, i.e., depletion fets are always on. This mosfet is always conducting but, like ordinary enhancement fets, it will conduct more current as V gs increases. One can build logic circuits with only n-channel devices (NMOS): enhancement fets for pulldowns and depletion fets as static pullups.. Since NMOS logic dissipates DC power it s been largely replaced by CMOS. MicroLab, VLSI-2 (20/24)

21 Coming Up... Next topic Static characteristics of MOS inverters: input and output voltages, noise margins, power dissipation. Readings for next time Weste: sections 2 thru 2.23 except (fet ( models), 3 thru (process technology) and 4.3 through (capacitances) CBT: Study the chip fabrication text of the university of Manchester at the MicroLab VLSI course web link. MicroLab, VLSI-2 (21/24)

22 Useful Constants sym value units description ε E-12 F/m permittivity ε ox 3.9 ε 0 F/m permittivity of SiO 2 ε Si 11.7 ε 0 F/m permittivity of silicon V T 25.8 mv kt/q (@300 K) q E C charge of electron k 1.381E-23 J/ K Boltzmann s constant n i 1.45E10 cm cm -3 intrinsic carrier concentration MicroLab, VLSI-2 (22/24)

23 Alcatel 0,5um Process Parameters sym param nmos V t0 t ox N A pmos units description VTO V threshold voltage TOX 1E-8 1E-8 m thin oxide thickness NSUB 4E16 4E16 cm cm -3 substrate doping density µ U cm 2 /Vs charge mobility k KP A/V 2 fet gain factor γ GAMMA V bulk threshold param. COX F/m 2 oxide capacitance C ox λ α/l V -1 channel length α modulat.1e 1e-8 2e-8 V - 1 m -1 channel length mod fact. φ 0 2φ F C gb0 C gs0 C gd0 C j C jsw M j M jsw PB V built in junction potent. PHI V surface inversion pot. CGB0 3.45E-10 dito F/m overlapping cap per 2L CGS0 1.38E dito F/m overlapping cap per W CGD0 1.38E dito F/m overlapping cap per W CJ 7.75E E-4 F/m 2 zero-bias cap / unit A CJSW 3.44E E-10 F/m zero-bias cap per unit P MJ grading coeff for bottom jsw MJSW grading coeff sidewall MicroLab, VLSI-2 (23/24)

24 Exercises: VLSI-2 Ex vlsi2.1 (difficulty: easy): Calculate the missing parameters on the previous transparency like intrinsic transconductance k, bulk threshold parameter γ and oxide capacitance C ox of an nfet (Alatel 0.5µm process) Result: k =100µA/V n 2, k =24.9µA/V p 2, γ=0.334v 0.5, C ox =3.45E-7 F/cm 2 (see Weste pp48ff) Ex vlsi2.2 (difficulty: easy): Calculate the threshold voltage shift due to the body effect of an nfet at V sb = 2.2V (Alcatel 0.5µm process) Result: dv tn = 0.282V (see Weste pp55) Ex vlsi2.3 (difficulty: easy): Calculate the transconductance β n of an nfet (Alatel 0.5µm process), W=1 µm, L= 0.5 µm Result: β n =200 µα/v2 (see Weste pp53) Ex vlsi2.4 (difficulty: easy): Calculate the capacitances of an nfet with Vsb=Vdb Vdb=3V, W=1µm, L=0.5µm, A=1µm 2, P=3µm (Alatel 0.5µm process) Result: C gate =2.35fF, C drain =C source =1.2fF (see Weste pp ) 191) Weste pp99: 2.10: Have a look at ex 8, 9 MicroLab, VLSI-2 (24/24)

problem grade total

problem grade total Fall 2005 6.012 Microelectronic Devices and Circuits Prof. J. A. del Alamo Name: Recitation: November 16, 2005 Quiz #2 problem grade 1 2 3 4 total General guidelines (please read carefully before starting):