1 FET Field Effect Transistors ELEKTRONIKA KONTROL Basic structure Gate G Source S n n-channel Cross section p + p + p + G Depletion region Drain D Eka Maulana, ST, MT, M.Eng. Universitas Brawijaya S Channel thickness n p + n-channel (a) n D
2 INTRODUCTION TO FET FET: FIELD EFFECT TRANSISTOR THERE ARE TWO TYPES JFET: JUNCTION FET MOSFET: METAL-OXIDE-SEMICONDUCTOR FET MOSFET IS ALSO CALLED THE INSULATED-GATE FET OR IGFET. QUITE SMALL SIMPLE MANUFACTURING PROCESS LOW POWER CONSUMPTION WIDELY USED IN VLSI CIRCUITS(>800 MILLION ON A SINGLE IC CHIP) 2
3 3 CLASSIFICATION OF FET ACCORDING TO THE TYPE OF THE CHANNEL, FETS CAN BE CLASSIFIED AS JFET P CHANNEL N CHANNEL MOSFET N CHANNEL P CHANNEL Enhancement type Depletion type Enhancement type Depletion type
4 SIMBOL JFET DAN MOSFET 4
5 THE FIELD EFFECT TRANSISTOR (FET) IN 1945, SHOCKLEY HAD AN IDEA FOR MAKING A SOLID STATE DEVICE OUT OF SEMICONDUCTORS. HE REASONED THAT A STRONG ELECTRICAL FIELD COULD CAUSE THE FLOW OF ELECTRICITY WITHIN A NEARBY SEMICONDUCTOR. HE TRIED TO BUILD ONE, BUT IT DIDN'T WORK. THREE YEARS LATER, BRATTAIN & BARDEEN BUILT THE FIRST WORKING TRANSISTOR, THE GERMANIUM POINT-CONTACT TRANSISTOR, WHICH WAS DESIGNED AS THE JUNCTION (SANDWICH) TRANSISTOR. IN 1960 BELL SCIENTIST JOHN ATALLA DEVELOPED A NEW DESIGN BASED ON SHOCKLEY'S ORIGINAL FIELD-EFFECT THEORIES. BY THE LATE 1960S, MANUFACTURERS CONVERTED FROM JUNCTION TYPE INTEGRATED CIRCUITS TO FIELD EFFECT DEVICES.
6 THE FIELD EFFECT TRANSISTOR (FET) FIELD EFFECT DEVICES ARE THOSE IN WHICH CURRENT IS CONTROLLED BY THE ACTION OF AN ELECTRON FIELD, RATHER THAN CARRIER INJECTION. FIELD-EFFECT TRANSISTORS ARE SO NAMED BECAUSE A WEAK ELECTRICAL SIGNAL COMING IN THROUGH ONE ELECTRODE CREATES AN ELECTRICAL FIELD THROUGH THE REST OF THE TRANSISTOR. THE FET WAS KNOWN AS A UNIPOLAR TRANSISTOR. THE TERM REFERS TO THE FACT THAT CURRENT IS TRANSPORTED BY CARRIERS OF ONE POLARITY (MAJORITY), WHEREAS IN THE CONVENTIONAL BIPOLAR TRANSISTOR CARRIERS OF BOTH POLARITIES (MAJORITY AND MINORITY) ARE INVOLVED.
8 OPERASI JFET 8
9 JUNCTION FET D Depletion layer G N-channel P + P + n-type Semiconductor G D S S 9
10 10 PHYSICAL OPERATION UNDER V DS =0 D D D P + G P + G P+ P + G P+ P + S S S U GS = 0 U GS < 0 U GS = U GS(off)
11 The effect of U DS on I D for U GS(off) <U GS < 0 11
12 TEST 12
13 TEST MODE ENHANCEMENT 13
14 RANGKAIAN COPER FET 14
15 Specification Sheet (JFETs)
16 CASE CONSTRUCTION AND TERMINAL IDENTIFICATION
17 IRFZ44 DATASHEET
18 JUNCTION FETS (JFETS) JFETS CONSISTS OF A PIECE OF HIGH-RESISTIVITY SEMICONDUCTOR MATERIAL (USUALLY SI) WHICH CONSTITUTES A CHANNEL FOR THE MAJORITY CARRIER FLOW. CONDUCTING SEMICONDUCTOR CHANNEL BETWEEN TWO OHMIC CONTACTS SOURCE & DRAIN
19 JUNCTION FETS (JFETS) THE MAGNITUDE OF THIS CURRENT IS CONTROLLED BY A VOLTAGE APPLIED TO A GATE, WHICH IS A REVERSE-BIASED. THE FUNDAMENTAL DIFFERENCE BETWEEN JFET AND BJT DEVICES: WHEN THE JFET JUNCTION IS REVERSE-BIASED THE GATE CURRENT IS PRACTICALLY ZERO, WHEREAS THE BASE CURRENT OF THE BJT IS ALWAYS SOME VALUE GREATER THAN ZERO.
20 JUNCTION FETS JFET IS A HIGH-INPUT RESISTANCE DEVICE, WHILE THE BJT IS COMPARATIVELY LOW. IF THE CHANNEL IS DOPED WITH A DONOR IMPURITY, N-TYPE MATERIAL IS FORMED AND THE CHANNEL CURRENT WILL CONSIST OF ELECTRONS. IF THE CHANNEL IS DOPED WITH AN ACCEPTOR IMPURITY, P-TYPE MATERIAL WILL BE FORMED AND THE CHANNEL CURRENT WILL CONSIST OF HOLES. N-CHANNEL DEVICES HAVE GREATER CONDUCTIVITY THAN P-CHANNEL TYPES, SINCE ELECTRONS HAVE HIGHER MOBILITY THAN DO HOLES; THUS N-CHANNEL JFETS ARE APPROXIMATELY TWICE AS EFFICIENT CONDUCTORS COMPARED TO THEIR P-CHANNEL COUNTERPARTS.
21 BASIC STRUCTURE OF JFETS IN ADDITION TO THE CHANNEL, A JFET CONTAINS TWO OHMIC CONTACTS: THE SOURCE AND THE DRAIN. THE JFET WILL CONDUCT CURRENT EQUALLY WELL IN EITHER DIRECTION AND THE SOURCE AND DRAIN LEADS ARE USUALLY INTERCHANGEABLE.
22 Basic structure Source S Cross section n p + p + p + n-channel G Gate G Depletion region Drain D Circuit symbol for n-channel FET Depletion regions n-channel S n S G G p D p + D Metal electrode Insulation (SiO 2 ) S Channel thickness n p + n-channel n D (b) (a)
23 N-CHANNEL JFET THIS TRANSISTOR IS MADE BY FORMING A CHANNEL OF N- TYPE MATERIAL IN A P-TYPE SUBSTRATE. THREE WIRES ARE THEN CONNECTED TO THE DEVICE. ONE AT EACH END OF THE CHANNEL. ONE CONNECTED TO THE SUBSTRATE. IN A SENSE, THE DEVICE IS A BIT LIKE A PN-JUNCTION DIODE, EXCEPT THAT THERE ARE TWO WIRES CONNECTED TO THE N-TYPE SIDE.
24 HOW JFET FUNCTION THE GATE IS CONNECTED TO THE SOURCE. SINCE THE PN JUNCTION IS REVERSE-BIASED, LITTLE CURRENT WILL FLOW IN THE GATE CONNECTION. THE POTENTIAL GRADIENT ESTABLISHED WILL FORM A DEPLETION LAYER, WHERE ALMOST ALL THE ELECTRONS PRESENT IN THE N-TYPE CHANNEL WILL BE SWEPT AWAY. THE MOST DEPLETED PORTION IS IN THE HIGH FIELD BETWEEN THE G AND THE D, AND THE LEAST-DEPLETED AREA IS BETWEEN THE G AND THE S.
25 HOW JFET FUNCTION BECAUSE THE FLOW OF CURRENT ALONG THE CHANNEL FROM THE (+VE) DRAIN TO THE (-VE) SOURCE IS REALLY A FLOW OF FREE ELECTRONS FROM S TO D IN THE N- TYPE SI, THE MAGNITUDE OF THIS CURRENT WILL FALL AS MORE SI BECOMES DEPLETED OF FREE ELECTRONS. THERE IS A LIMIT TO THE DRAIN CURRENT (I D ) WHICH INCREASED V DS CAN DRIVE THROUGH THE CHANNEL. THIS LIMITING CURRENT IS KNOWN AS I DSS (DRAIN-TO-SOURCE CURRENT WITH THE GATE SHORTED TO THE SOURCE).
26 THE OUTPUT CHARACTERISTICS OF AN N-CHANNEL JFET WITH THE GATE SHORT-CIRCUITED TO THE SOURCE. THE INITIAL RISE IN I D IS RELATED TO THE BUILDUP OF THE DEPLETION LAYER AS V DS INCREASES. THE CURVE APPROACHES THE LEVEL OF THE LIMITING CURRENT I DSS WHEN I D BEGINS TO BE PINCHED OFF. THE PHYSICAL MEANING OF THIS TERM LEADS TO ONE DEFINITION OF PINCH-OFF VOLTAGE, V P, WHICH IS THE VALUE OF V DS AT WHICH THE MAXIMUM I DSS FLOWS.
27 WITH A STEADY GATE-SOURCE VOLTAGE OF 1 V THERE IS ALWAYS 1 V ACROSS THE WALL OF THE CHANNEL AT THE SOURCE END. A DRAIN-SOURCE VOLTAGE OF 1 V MEANS THAT THERE WILL BE 2 V ACROSS THE WALL AT THE DRAIN END. (THE DRAIN IS UP 1V FROM THE SOURCE POTENTIAL AND THE GATE IS 1V DOWN, HENCE THE TOTAL DIFFERENCE IS 2V.) THE HIGHER VOLTAGE DIFFERENCE AT THE DRAIN END MEANS THAT THE ELECTRON CHANNEL IS SQUEEZED DOWN A BIT MORE AT THIS END.
28 WHEN THE DRAIN-SOURCE VOLTAGE IS INCREASED TO 10V THE VOLTAGE ACROSS THE CHANNEL WALLS AT THE DRAIN END INCREASES TO 11V, BUT REMAINS JUST 1V AT THE SOURCE END. THE FIELD ACROSS THE WALLS NEAR THE DRAIN END IS NOW A LOT LARGER THAN AT THE SOURCE END. AS A RESULT THE CHANNEL NEAR THE DRAIN IS SQUEEZED DOWN QUITE A LOT.
29 INCREASING THE SOURCE-DRAIN VOLTAGE TO 20V SQUEEZES DOWN THIS END OF THE CHANNEL STILL MORE. AS WE INCREASE THIS VOLTAGE WE INCREASE THE ELECTRIC FIELD WHICH DRIVES ELECTRONS ALONG THE OPEN PART OF THE CHANNEL. HOWEVER, ALSO SQUEEZES DOWN THE CHANNEL NEAR THE DRAIN END. THIS REDUCTION IN THE OPEN CHANNEL WIDTH MAKES IT HARDER FOR ELECTRONS TO PASS. AS A RESULT THE DRAIN-SOURCE CURRENT TENDS TO REMAIN CONSTANT WHEN WE INCREASE THE DRAIN-SOURCE VOLTAGE.
31 INCREASING V DS INCREASES THE WIDTHS OF DEPLETION LAYERS, WHICH PENETRATE MORE INTO CHANNEL AND HENCE RESULT IN MORE CHANNEL NARROWING TOWARD THE DRAIN. THE RESISTANCE OF THE N-CHANNEL, R AB THEREFORE INCREASES WITH V DS. THE DRAIN CURRENT: I DS = V DS /R AB I D VERSUS V DS EXHIBITS A SUBLINEAR BEHAVIOR, SEE FIGURE FOR V DS < 5V. THE PINCH-OFF VOLTAGE, V P IS THE MAGNITUDE OF REVERSE BIAS NEEDED ACROSS THE P + N JUNCTION TO MAKE THEM JUST TOUCH AT THE DRAIN END. SINCE ACTUAL BIAS VOLTAGE ACROSS P + N JUNCTION AT DRAIN END IS V GD, THE PINCH-OFF OCCUR WHENEVER: V GD = -V P.
33 BEYOND V DS = V P, THERE IS A SHORT PINCH-OFF CHANNEL OF LENGTH, l PO. AS V DS INCREASES, MOST OF ADDITIONAL VOLTAGE SIMPLY DROPS ACROSS l PO AS THIS REGION IS DEPLETED OF CARRIERS AND HENCE HIGHLY RESISTIVE. VOLTAGE DROP ACROSS CHANNEL LENGTH, L CH REMAIN AS V P. BEYOND PINCH-OFF THEN I D = V P /R AP (V DS >V P ).
34 WHAT HAPPEN WHEN NEGATIVE VOLTAGE, SAYS V GS = -2V, IS APPLIED TO GATE WITH RESPECT TO SOURCE (WITH V DS =0). THE P + N JUNCTION ARE NOW REVERSE BIASED FROM THE START, THE CHANNEL IS NARROWER, AND CHANNEL RESISTANCE IS NOW LARGER THAN IN THE V GS = 0 CASE.
35 THE DRAIN CURRENT THAT FLOWS WHEN A SMALL V DS APPLIED (FIG B) IS NOW SMALLER THAN IN V GS = 0 CASE. APPLIED V DS = 3 V TO PINCH-OFF THE CHANNEL (FIG C). WHEN V DS = 3V, V GD ACROSS P + N JUNCTION AT DRAIN END IS -5V, WHICH IS V P, SO CHANNEL BECOMES PINCH-OFF. BEYOND PINCH-OFF, I D IS NEARLY SATURATED JUST AS IN THE V GS =0 CASE. PINCH-OFF OCCURS AT V DS = V DS(SAT), V DS(SAT) = V P +V GS, WHERE V GS IS VE VOLTAGE (REDUCING V P ). FOR V DS >V DS(SAT), I D BECOMES NEARLY SATURATED AT VALUE AS I DS.
36 BEYOND PINCH-OF, WITH VE V GS, I DS IS WHERE R AP (V GS ) IS THE EFFECTIVE RESISTANCE OF THE CONDUCTING N-CHANNEL FROM A TO P, WHICH DEPENDS ON CHANNEL THICKNESS AND HENCE V GS. WHEN V GS = -V P = -5V WITH V DS = 0, THE TWO DEPLETION LAYERS TOUCH OVER THE ENTIRE CHANNEL LENGTH AND THE WHOLE CHANNEL IS CLOSED. THE CHANNEL SAID TO BE OFF.
39 THERE IS A CONVENIENT RELATIONSHIP BETWEEN I DS AND V GS. BEYOND PINCH-OFF 2 I DS I DSS 1 V V GS GS ( off ) WHERE I DSS IS DRAIN CURRENT WHEN V GS = 0 AND V GS(OFF) IS DEFINED AS V P, THAT IS GATE-SOURCE VOLTAGE THAT JUST PINCHES OFF THE CHANNEL. THE PINCH OFF VOLTAGE V P HERE IS A +VE QUANTITY BECAUSE IT WAS INTRODUCED THROUGH V DS(SAT). V GS(OFF) HOWEVER IS NEGATIVE, -V P.
42 I-V CHARACTERISTICS
43 I-V CHARACTERISTICS
44 JFET: I-V CHARACTERISTICS
45 THE TRANSCONDUCTANCE CURVE THE PROCESS FOR PLOTTING TRANSCONDUCTANCE CURVE FOR A GIVEN JFET: PLOT A POINT THAT CORRESPONDS TO VALUE OF V GS(OFF). PLOT A POIT THAT CORRESPONDS TO VALUE OF I DSS. SELECT 3 OR MORE VALUES OF V GS BETWEEN 0 V AND V GS(OFF). FOR VALUE OF V GS, DETERMINE THE CORRESPONDING VALUE OF I D FROM PLOT THE POINT FROM (3) AND CONNECT ALL THE PLOTTED POINT WITH A SMOOTH CURVE.
46 DEVICE STRUCTURE OF MOSFET (N-TYPE) Source(S) Oxide (SiO 2 ) Gate(G) Metal Drain(D) n + Channel area n + p-type Semiconductor Substrate (Body) Body(B) For normal operation, it is needed to create a conducting channel between Source and Drain 2014/9/30 SJTU J. Chen 46
47 DEVICE STRUCTURE OF MOSFET (N-TYPE) L = 0.1 to 3 mm W = 0.2 to 100 mm T ox = 2 to 50 nm Cross-section view 2014/9/30 SJTU J. Chen 47
48 DRAIN CURRENT UNDER PINCH OFF The electrons pass through the pinch off area at very high speed so as the current continuity holds, similar to the water flow at the Yangtze Gorges Pinched-off channel 2014/9/30 SJTU J. Chen 48
49 DRAIN CURRENT CONTROLLED BY V GS V GS CREATES THE CHANNEL. INCREASING V GS WILL INCREASE THE CONDUCTANCE OF THE CHANNEL. AT SATURATION REGION ONLY THE V GS CONTROLS THE DRAIN CURRENT. AT SUBTHRESHOLD REGION, DRAIN CURRENT HAS THE EXPONENTIAL RELATIONSHIP WITH V GS 49
50 P CHANNEL DEVICE TWO REASONS FOR READERS TO BE FAMILIAR WITH P CHANNEL DEVICE Existence in discrete-circuit. More important is the utilization of complementary MOS or CMOS circuits. 2014/9/30 SJTU J. Chen 50
51 51 OUTPUT CHARACTERISTIC CURVES OF NMOS (a) An n-channel enhancementtype MOSFET with v GS and v DS applied and with the normal directions of current flow indicated. (b) The i D v DS characteristics for a device with k n (W/L) = 1.0 ma/v 2.
52 OUTPUT CHARACTERISTIC CURVES OF NMOS Three distinct region Cutoff region Triode region Saturation region Characteristic equations Circuit model 2014/9/30 SJTU J. Chen 52
53 53 CUTOFF REGION Biased voltage v V GS t The transistor is turned off. i D 0 Operating in cutoff region as a switch.
54 54 TRIODE REGION Biased voltage v v GS DS V v t GS V t The channel depth changes from uniform to tapered shape. Drain current is controlled not only by v DS but also by v GS i D k k n n W ' L W ' L ( v ( v GS GS V ) v t t V ) v DS DS 1 2 v 2 DS process transconductance parameter
55 55 CHANNEL LENGTH MODULATION The MOSFET parameter V A depends on the process technology and, for a given process, is proportional to the channel length L.
56 THE DEPLETION-TYPE MOSFET PHYSICAL STRUCTURE THE STRUCTURE OF DEPLETION-TYPE MOSFET IS SIMILAR TO THAT OF ENHANCEMENT-TYPE MOSFET WITH ONE IMPORTANT DIFFERENCE: THE DEPLETION-TYPE MOSFET HAS A PHYSICALLY IMPLANTED CHANNEL There is no need to induce a channel The depletion MOSFET can be operated at both enhancement mode and depletion mode 56
57 57 CIRCUIT SYMBOL FOR THE N-CHANNEL DEPLETION-MOS Circuit symbol for the n- channel depletion-type MOSFET Simplified circuit symbol applicable for the case the substrate (B) is connected to the source (S).
58 58 CHARACTERISTIC CURVES Expression of characteristic equation i D W k ' ( v L n GS t ) Drain current with I DSS W L kn' Vt v GS V 0 the i D v GS characteristic in saturation
59 59 THE I D V GS CHARACTERISTIC IN SATURATION Sketches of the i D v GS characteristics for MOSFETs of enhancement and depletion types The characteristic curves intersect the v GS axis at V t.
60 THE OUTPUT CHARACTERISTIC CURVES 60
61 Depletion Mode MOSFET Construction The Drain (D) and Source (S) leads connect to the to n-doped regions These N-doped regions are connected via an n-channel This n-channel is connected to the Gate (G) via a thin insulating layer of SiO 2 The n-doped material lies on a p-doped substrate that may have an additional terminal connection called SS
62 OPERASI DASAR A D-MOSFET may be biased to operate in two modes: the Depletion mode or the Enhancement mode
63 D-MOSFET DEPLETION MODE OPERATION 63 The transfer characteristics are similar to the JFET In Depletion Mode operation: When VGS = 0V, ID = IDSS When VGS < 0V, ID < IDSS When VGS > 0V, ID > IDSS The formula used to plot the Transfer Curve, is: I D = I DSS 1 - V V GS P 2
64 64 D-MOSFET ENHANCEMENT MODE OPERATION Enhancement Mode operation In this mode, the transistor operates with V GS > 0V, and I D increases above I DSS Shockley s equation, the formula used to plot the Transfer Curve, still applies but VGS is positive: 2 V GS I D = I DSS 1 - VP
65 p-channel Depletion Mode MOSFET The p-channel Depletion mode MOSFET is similar to the n-channel except that the voltage polarities and current directions are reversed
66 Basic Operation The Enhancement mode MOSFET only operates in the enhancement mode. VGS is always positive IDSS = 0 when VGS < VT As VGS increases above VT, ID increases If VGS is kept constant and VDS is increased, then ID saturates (IDSS) The saturation level, VDSsat is reached.
67 TRANSFER CURVE ID(on) k= To determine ID given VGS: 2 I D = k (V GS - V T) (V 2 GS(ON) - V T ) where VT = threshold voltage or voltage at which the MOSFET turns on. k = constant found in the specification sheet The PSpice determination of k is based on the geometry of the device: W KP k = where KP = μnc L 2 OX
68 P-CHANNEL ENHANCEMENT MODE MOSFETS The p-channel Enhancement mode MOSFET is similar to the n-channel except that the voltage polarities and current directions are reversed.
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Lecture 16: MOS Transistor models: Linear models, SPICE models Context In the last lecture, we discussed the MOS transistor, and added a correction due to the changing depletion region, called the body
Field Effect Transistors (FET s) University of Connecticut 136 Field Effect Transistors (FET s) FET s are classified three ways: by conduction type n-channel - conduction by electrons p-channel - conduction
Sub-threshold Region - So far, we have discussed the MOSFET behavior in linear region and saturation region - Sub-threshold region is refer to region where Vt is less than Vt - Sub-threshold region reflects
Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-
Questions on JFET: 1) Which of the following component is a unipolar device? a) BJT b) FET c) DJT d) EFT 2) Current Conduction in FET takes place due e) Majority charge carriers only f) Minority charge
Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,
Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris, Ch 2 & 5.1-5.3 Rabaey, Ch 3) URL: www.ee.ic.ac.uk/pcheung/
Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,
Transistors ipolar Junction transistors Principle of operation haracteristics Field effect transistors Principle of operation haracteristics ntroduction Radio based on vacuum tubes Fundamental building
55:041 Electronic Circuits Mosfet Review Sections of Chapter 3 &4 A. Kruger Mosfet Review, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width 1 10-6 m or less Thickness 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor
55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 10-6 m or less Thickness = 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor
Mani Vaidyanathan 1 Summary of Lecture Notes on Metal-Oxide-Semiconductor, Field-Effect Transistors (MOSFETs) Introduction 1. We began by asking, Why study MOSFETs? The answer is, Because MOSFETs are the