2.8 - CMOS TECHNOLOGY

Transcription

1 CMOS Technology (6/7/00) Page CMOS TECHNOLOGY INTRODUCTION Objective The objective of this presentation is: 1.) Illustrate the fabrication sequence for a typical MOS transistor 2.) Show the physical aspects of the MOSFET Outline CMOS technology Compatible active devices Summary

2 CMOS Technology (6/7/00) Page 2 CMOS TECHNOLOGY Fabrication Fabrication involves the implementation of semiconductor processes to build a MOSFET transistor and compatible passive components as an integrated circuit. N-Well CMOS Fabrication Major Steps 1.) Implant and diffuse the 2.) Deposition of silicon nitride 3.) n-type field (channel stop) implant 4.) p-type field (channel stop) implant 5.) Grow a thick field oxide () 6.) Grow a thin oxide and deposit polysilicon 7.) Remove poly and form LDD spacers 8.) Implantation of NMOS S/D and n-material contacts 9.) Remove spacers and implant NMOS LDDs 10.) Repeat steps 8.) and 9.) for PMOS 11.) Anneal to activate the implanted ions 12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass) 13.) Open contacts, deposit first level metal and etch unwanted metal 14.) Deposit another interlayer dielectric (CVD SiO 2 ), open vias and deposit second level metal 15.) Etch unwanted metal, deposit a passivation layer and open over bonding pads

3 CMOS Technology (6/7/00) Page 3 Major CMOS Process Steps Step 1 - Implantation and diffusion of the s implant Photoresist SiO 2 Photoresist Step 2 - Growth of thin oxide and deposition of silicon nitride Si 3 N 4 SiO 2 Fig

4 CMOS Technology (6/7/00) Page 4 Major CMOS Process Steps - Continued Step 3.) Implantation of the n-type field channel stop n- field implant Photoresist Si 3 N 4 Photoresist Pad oxide (SiO 2 ) Step 4.) Implantation of the p-type field channel stop p- field implant Si 3 N 4 Photoresist Fig

5 CMOS Technology (6/7/00) Page 5 Major CMOS Process Steps - Continued Step 5.) Growth of the thick field oxide (LOCOS - localized oxidation of silicon) Si 3 N 4 Step 6.) Growth of the gate thin oxide and deposition of polysilicon,,,, Polysilicon,,,, Fig

6 CMOS Technology (6/7/00) Page 6 Major CMOS Process Steps - Continued Step 7.) Removal of polysilicon and formation of the sidewall spacers Polysilicon SiO 2 spacer,,, Photoresist Step 8.) Implantation of NMOS source and drain and contact to (not shown) n+ S/D implant Polysilicon Photoresist Fig

7 CMOS Technology (6/7/00) Page 7 Major CMOS Process Steps - Continued Step 9.) Remove sidewall spacers and implant the NMOS lightly doped source/drains n- S/D LDD implant Polysilicon Photoresist Step 10.) Implant the PMOS source/drains and contacts to the p- substrate (not shown), remove the sidewall spacers and implant the PMOS lightly doped source/drains, Polysilicon LDD Diffusion Fig

8 CMOS Technology (6/7/00) Page 8 Major CMOS Process Steps - Continued Step 11.) Anneal to activate the implanted ions n+ Diffusion p+ Diffusion Polysilicon Step 12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass) n+ Diffusion p+ Diffusion Polysilicon BPSG Fig

9 CMOS Technology (6/7/00) Page 9 Major CMOS Process Steps - Continued Step 13.) Open contacts, deposit first level metal and etch unwanted metal CVD oxide, Spin-on glass (SOG) Metal 1 BPSG Step 14.) Deposit another interlayer dielectric (CVD SiO2), open contacts, deposit second level metall Metal 2 Metal 1 BPSG Fig

10 CMOS Technology (6/7/00) Page 10 Major CMOS Process Steps - Continued Step 15.) Etch unwanted metal and deposit a passivation layer and open over bonding pads Metal 2 Passivation protection layer Metal 1 BPSG Fig p-well process is similar but starts with a p-well implant rather than an implant.

11 CMOS Technology (6/7/00) Page 11 Approximate Side View of CMOS Fabrication Passivation,,, Metal 4 Metal 3 2 microns Polysilicon Metal 2 Metal 1 Diffusion Fig

12 CMOS Technology (6/7/00) Page 12 Silicide/Salicide Technology Used to reduce interconnect resistivity by placing a low-resistance silicide such as TiSi 2, WSi 2, TaSi 2, etc. on top of polysilicon Salicide technology (self-aligned silicide) provides low resistance source/drain connections as well as lowresistance polysilicon. Polysilicide Metal Polysilicide Metal Salicide Polycide structure Salicide structure Fig2.2-10

13 CMOS Technology (6/7/00) Page 13 COMPATIBLE ACTIVE DEVICES Lateral Bipolar Junction Transistor P-Well Process NPN Lateral- V DD Base Emitter Collector n + p+ n + n + p-well n-substrate

14 CMOS Technology (6/7/00) Page 14 Lateral Bipolar Junction Transistor - Field-aided LateralßF 50 to 100 depending on the process V DD Base Continued Emitter V Gate Collector Keep channel from forming n + p+ n + n + p-well n-substrate Good geometry matching Low 1/f noise (if channel doesn t form) Acts like a photodetector with good efficiency

15 CMOS Technology (6/7/00) Page 15 Geometry of the Lateral PNP BJT Minimum Size layout of a single emitter dot lateral PNP BJT: contact p-diffusion contact p-substrate diffusion 40 emitter dot LPNP transistor (total device area is 0.006mm 2 in a 1.2µm CMOS process): Lateral Collector Base Emitter 31.2 µm 71.4 µm Base Gate V SS Lateral Collector Emitter 33.0 µm Gate (poly) V SS 84.0 µm

16 CMOS Technology (6/7/00) Page 16 Performance of the Lateral PNP BJT Schematic: Emitter Gate Base Lateral Collector Vertical Collector ( V SS ) ß L vs I CL for the 40 emitter dot LPNP BJT: 150 V CE = 4.0 V Lateral efficiency versus I E for the 40 emitter dot LPNP BJT: V CE = 4.0 V Lateral ß V CE = 0. 4V Lateral Efficiency V CE = 0. 4V 50 1 na 10 na 100 na 1 µa 10 µa 100 µa 1 ma Lateral Collector Current na 10 na 100 na 1 µa 10 µa 100 µa 1 ma Emitter Current

17 CMOS Technology (6/7/00) Page 17 Performance of the Lateral PNP BJT - Continued Typical Performance for the 40 emitter dot LPNP BJT: Transistor area mm2 Lateral ß 90 Lateral efficiency 0.70 Base resistance 150 E 5 Hz 2.46 nv / Hz E n (midband) 1.92 nv / Hz f c (E n ) 3.2 Hz I 5 Hz 3.53 pa / Hz I n (midband) 0.61 pa / Hz f c (In) 162 Hz f T 85 MHz Early voltage 16 V

18 CMOS Technology (6/7/00) Page 18 High Voltage MOS Transistor The well can be substituted for the drain giving a lower conductivity drain and therefore higher breakdown voltage. NMOS in example: Oxide Source Gate Drain Polysilicon Source n+ Channel n+ p+ p-substrate Substrate Drain-substrate/channel can be as large as 20V or more. Fig A

19 CMOS Technology (6/7/00) Page 19 Latch-up in CMOS Technology Latch-up Mechanisms 1. SCR regenerative switching action. 2. Secondary breakdown. 3. Sustaining voltage breakdown. Parasitic lateral,, PNP,, and vertical,, NPN BJTs in a p-well,, CMOS,, technology: V DD D G S S G D VSS B A,, n+,,,, p+ p+ p-well,,,,,,,, n+ n+ p+ R N - R P - n- substrate Equivalent circuit of the SCR formed from the parasitic BJTs: Fig V DD V in V SS V DD A B V out B + - R N - R P - A V SS V SS Fig

20 CMOS Technology (6/7/00) Page 20 Preventing Latch-Up in a P-Well Technology 1.) Keep the source/drain of the MOS device not in the well as far away from the well as possible. This will lower the value of the BJT betas. 2.) Reduce the values of R N - and R P -. This requires more current before latch-up can occur. 3.) Make a p - diffusion around the p-well. This shorts the collector of Q1 to ground. p-channel transistor n-channel transistor n+ guard bars p+ guard bars V DD V SS n- substrate p-well Figure For more information see R. Troutman, CMOS Latchup, Kluwer Academic Publishers.

21 CMOS Technology (6/7/00) Page 21 Electrostatic Discharge Protection (ESD) Objective: To prevent large external voltages from destroying the gate oxide. Electrical equivalent circuit p+ to diode To internal gates n+ to p-substrate diode Metal VDD VSS Implementation in CMOS technology p+ resistor Bonding Pad n+ p+ p-substrate Fig

22 CMOS Technology (6/7/00) Page 22 Temperature Characteristics of Transistors Fractional Temperature Coefficient TCF = 1 x x T Typically in ppm/ C MOS Transistor V T = V(T 0 ) + α(t-t 0 ) +, where α -2.3mV/ C (200 K to 400 K) µ = K µ T -1.5 BJT Transistor Reverse Current, I S : 1 I S I S T = 3 T + 1 T V G0 kt/q Empirically, I S doubles approximately every 5 C increase Forward Voltage, v D : v D Τ = - V G0 - v D T - 3kT/q T -2mV/ C at v D = 0.6V

23 CMOS Technology (6/7/00) Page 23 Noise in Transistors Shot Noise i 2 = 2qI D f (amperes 2 ) where q = charge of an electron I D = dc value of i D f = bandwidth in Hz Noise current spectral density = i2 (amperes 2 /Hz) Thermal Noise Resistor: v 2 = 4kTR f (volts 2 ) MOSFET: where i D 2 = 8kTg m f 3 f (ignoring bottom gate) k = Boltzmann s constant R = resistor or equivalent resistor in which the thermal noise is occurring. g m = transconductance of the MOSFET

24 CMOS Technology (6/7/00) Page 24 Noise in Transistors - Continued Flicker (1/f) Noise i 2 D = K f Ia f b f where K f = constant (10-28 Farad amperes) Noise power spectral density a = constant (0.5 to 2) b = constant ( 1) 1/f log(f) Fig

25 CMOS Technology (6/7/00) Page 25 SUMMARY CMOS is a fairly simple, technology which is used primarily for digital circuits The minimum channel length of CMOS tends to decrease by a factor of 1/ 2 every three years (Moore s Law) CMOS technology can be used for analog circuits but it would not be the preferred choice if everything else were equal. Active devices compatible with standard CMOS technology are: - Lateral BJTs - Vertical BJTs (not shown) Other considerations - Latchup - Electrostatic Breakdown