ECSE-6300 IC Fabrication Laboratory Lecture 9 MOSFETs. Lecture Outline

Transcription

1 ECSE-6300 IC Fabrication Laboratory Lecture 9 MOSFETs Prof. Rensselaer Polytechnic Institute Troy, NY Office: CII-6229 Tel.: (518) s: luj@rpi.edu /index.html 9-1 Lecture Outline MOSFET Structures MOS Physics Accumulation, Depletion and Inversion Threshold Voltage I-V Characteristics MOSFET Process Chip Layout Note: The lecture slides were prepared based on the original materials written by Profs. T.P. Chow and J.-Q. Lu 9-2

2 FabLab Goal: n-channel MOSFETs Source Gate Drain Poly Si Gate Oxide ILD n+ Channel n+ P Substrate 15 Weeks 4 Masks 1 Ion Implant Tools: Furnaces (2) P5000 OAI Aligner RIE etcher (Trion, Alcatel) Sputter Wet bench 9-3 P-type Flatband Condition Ideal MOS Structure N-type V FB = m [ + (E C -E F )/q] = 0 9-4

3 Accumulation 9-5 Depletion 9-6

4 Inversion 9-7 Surface Potential Semiconductor Surface q E g E C q S ( S >0) Insulator ~10 nm (x) q B P Type Semiconductor qn x A Q n E i E F E V S < 0 Accumulation S = 0 Flatband B > S >0 Depletion S > B Inversion Surface charge density Q S can be obtained by solving the Poisson s equation Q S 9-8

5 Basic MOS Physics Surface Charge vs. S Under accumulation,, Under depletion, 2 2 Under strong inversion, when 2 2 ln 2 S kt exp 2 C Q S S 9-9 Quasi Static MOS Capacitance For V G << 0, For 0 < V G < 2 B, For V G > 2 B, Inversion layer shields electric field from penetrating into the semiconductor bulk. Do the minority carriers follow the ac gate signal? (a) Low frequency (b) High frequency (c) Deep depletion (pulse) 9-10

6 Basic MOS Physics Threshold Voltage, V T Threshold voltage is the minimum gate voltage at which the strong inversion exists Oxide field: 9-11 Oxide and Interface Charges It is convenient to define a net effective oxide charge per unit area Q 1 t 0 ox t ox ( x' t ox so that V FB = MS -Q/C ox ) ( x') dx' Besides Q it and Q f, Q m (alkali ion charge, positive) and Q ot (oxide trap charge, positive or negative) are also possible: Q = Q f + Q it + Q m + Q ot 9-12

7 Threshold Voltage Non Ideal MOS Non-ideal MOS factors include: (a) Metal-Semiconductor work function difference, MS = ( m - S ) = ( B + ox ) - ( + E g /2q + B ) (b) Fixed oxide charges (Q f ), (c) Mobile ion charges in the oxide (Q m ), (d) Interface state charges (Q it ). V T V T = V T ideal + MS + (Q f +Q m +Q it )/C ox V T ideal + MS + Q f /C ox 9-13 Threshold Voltage Gate Oxide vs. Field Oxide 9-14

8 MOSFET Basic Operation: A field-induced channel to connect two adjacent source and drain junctions. MOSFET Features: 4 th terminal (substrate or backgate terminal) MOS-induced channel Pinchoff near the drain end Parasitic npn 9-15 MOSFET Assumptions: V SB = 0 and V DS > 0 If V GS > V T, a layer of inversion electrons is formed and flows from the source region to the drain. The electrical current, corresponding to this electron flow, I DS, flows from the drain to the source. If V GS < V T, I DS 0. This is an Enhancement-Mode, N-Channel MOSFET When V SB > 0, V T increases. Other types of MOSFETs: Depletion-Mode, N-Channel Enhancement-Mode, P-Channel Depletion-Mode, P-Channel 9-16

9 MOSFET 9-17 MOSFET Type of MOSFETs Enhancement Mode, N Channel Depletion Mode, N Channel Enhancement Mode, P Channel Depletion Mode, P Channel V T I DS > 0 > 0 < 0 > 0 < 0 < 0 > 0 <

10 MOSFET A unipolar carrier device. Minority carriers in the surface channel are separated from the majority carriers in the substrate by a space-charge or depletion layer. Carriers are transported across the channel by drift. Current condition continues even when the inversion layer disappears on the drain end MOSFET 9-20

11 MOSFET Channel Resistance Gate voltage exceeds threshold voltage to induce an inversion layer in the channel region (Vertical electric field across the gate oxide) Drain voltage to cause electron flow from source to drain (Lateral electric field to drift electrons across the channel) 9-21 MOSFET Channel Resistance Inversion charge Q n = C ox ( V G -V T ) Gradual Channel Approximation dr = dy / (Z ns Q n (y)) Q n (y) = C ox [V GS -V T - V(y)] dv = I D dr At low drain voltages (linear region), and MOSFET acts as a gatecontrolled resistor Z: Channel width L: Channel length 9-22

12 MOSFET Channel Pinch off With increasing drain voltage V DS =V GS V T (i.e., V GD =V T ) 2 S Channel length modulation: V V L DS DS, sat qn A 9-23 MOSFET I V Characteristics In the linear region, I Z D gm V DS ns VGS L At pinch off and beyond (saturation region), g I D m, sat Z nsc 2L Z nsc L ox ox ( V V G G C ox V V T T V 2 ) DS MOSFET acts as a current source 2 S Channel length modulation: V V L DS DS, sat qn A 9-24

13 Start Material P Substrate Starting wafers (75) (100), 10 cm, P type Scribe wafers number IDs 9-25 Field Oxide P Substrate Field Oxide Mask #: M1 Active Area RCA clean Grow oxide 1 m 1000C, dry/wet/dry/n2 Pattern field oxide Etch field oxide Plasma/BHF Strip PR Function: Device isolation, cross talk suppression Device Parameter: Field Threshold: >20 V desired 9-26

14 Field Oxide Poly Si Gate P Substrate Gate Definition Gate Oxide (100nm) Mask #: M2 Gate RCA clean Function: MOS gate electrode Device Parameter MOS Threshold Voltage: V desired Poly Si: < 5 k/square sheet resistance desired Grow gate oxide: 100 nm 1000C dry O2/N2 (30min) CVC Sputter: a Si 800 nm Bruce Furnace: 1000 o C 1hr Pattern gate Plasma etch Poly Si N+ Implantation: Arsenic 4e15cm 2, 150keV Anneal at 1000 o Cafter ILD 9-27 Field Oxide Poly Si Gate N + Source/Drain n+ n+ P Substrate n + (As) Function: Access regions to MOS channel Junction Depth: 0.5 m targeted Device Parameter R source, R drain <500 /square sheet resistance desired Pirahna clean BOE etch (leave <30 nm oxide) N+ Implantation Arsenic 2e15cm 2, 150keV Strip PR 9-28

15 Source Gate and Source/Drain Contacts Gate P Substrate ILD Drain n+ n+ Mask #: M5 Contacts Pirahna clean BOE Ox etch Function: Transistor access to metallization Device Parameters Specific contact resistivity: <10 cm 2 desired 1 m ILD (oxide) deposition (P5000) Densify ILD and activate implants (1000 o C/N2) Pattern gate and Source/drain contacts Etch oxide: Plasma (BHF dip) 9-29 Source Gate Metallization Drain ILD n+ n+ P Substrate Mask #: M6 Metallization Al/1% Si sputter deposition: 1.2 µm Pattern metal Etch Al/Si Plasma or wet etch Back side Al metal deposition Metal sintering Function: Transistor access to outside Device Parameters Metal sheet resistance: 0.1 /square desired 9-30