Advantage of Having Large Numbers of Function on a Single Chip. Less Area occupied Less power Consumption Higher Speed Higher Reliability Economical

Transcription

1 VLSI DESIGN(UNIT 1)

2 Introduction Some History Invention of the transistor (BJT) 1947 Single-transistor integrated circuit 1958 Invention of CMOS logic gates 1963 First microprocessor (Intel 4004)1970 Very Large Scale Integration transistor per chips More Recently Ultra Large Scale Integration System on Chip (SoC) 20 ~ 30 million transistors in 2002 Conclusion The chip complexity has increased by a factor of 1000 since its first introduction

3 Advantage of Having Large Numbers of Function on a Single Chip Less Area occupied Less power Consumption Higher Speed Higher Reliability Economical

4 Moore s law Number of transistors per square inch on integrated circuits had doubled every year since the integrated circuit was invented.

5 Overview of Vlsi Design Methodologies VLSI products includes Development of Technology Computer aided design tools Chip Design Fabrication Packaging Testing & reliability qualification

6 Vlsi Design Style Full Custom where geometry & placement of every transistor can be optimized individually. Semi custom Allows shorter design time until design maturity can be achieved. For success of commercial product,majority of the design cycle time is devoted to achieve certain desired performance of the chip at acceptable cost.

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8 Inference FULL CUSTOM DESIGN Requires longer time till design maturity Adjustment flexibility of almost every aspect improves circuit performance High performance but larger cost SEMI CUSTOM DESIGN Requires less time till design maturity In early stage, performance is better than full custom design Lesser performance but shorter design time cycle

9 Design Style for Vlsi Product Depends on Performance requirements Technology used Expected lifetime of the product Cost of the project

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11 In every 2 years, a new generation of technology is introduced for smaller device dimension & high performance. INFERENCE To make use of current technology,chip development time should be short enough to give timely delivery of the product to the customer. In reality, the design cycle of the next generation chips usually overlaps with the production cycle of the current generation chips.

12 VLSI Design Flow Y Chart Gives simplified design flow for logic chips on three different axes. Three domains of representation are 1. Behavioral Domain 2. Structural Domain 3. Geometrical Layout Domain

13 Figure Typical VLSI design flow in three domains (Y-chart representation).

14 VLSI Design Flow (Simplified View)

15 Design Hierarchy The use of hierarchy involves dividing a module into sub-modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable. VLSI chip can be represented in three domains. Correspondingly, a hierarchy structure can be described in each domain separately. As an example of structural hierarchy, shows the structural decomposition of a CMOS four-bit adder into its components. The adder can be decomposed progressively into one- bit adders, separate carry and sum circuits, and finally, into individual logic gates.

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17 Concept of Regularity, Modularity and Locality Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible. A good example of regularity is the design of array structures consisting of identical cells - such as a parallel multiplication array. Regularity can exist at all levels of abstraction: at the transistor level,at the logic level Figure 1.11 shows regular circuit-level designs of a 2-1 MUX (multiplexer), an D-type edgetriggered flip flop, and a one-bit full adder.

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19 Modularity in design means that the various functional blocks which make up the larger system must have well-defined functions and interfaces. Modularity allows that each block or module can be designed relatively independently from each other, since there is no ambiguity about the function and the signal interface of these blocks. The concept of locality also ensures that connections are mostly between neighboring modules, avoiding long-distance connections as much as possible.

20 MOSFET Fabrication

21 CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched. Typically use p-type substrate for nmos transistors Requires n-well for body of pmos transistors

22 Inverter Cross-section A GND Y V DD SiO 2 n+ diffusion n+ n+ p+ p substrate n well p+ p+ diffusion polysilicon metal1 nmos transistor pmos transistor

23 Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal n well Polysilicon n+ Diffusion p+ Diffusion Contact Metal

24 Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO 2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO 2 p substrate

25 Oxidation Grow SiO 2 on top of Si wafer C with H 2 O or O 2 in oxidation furnace SiO 2 p substrate

26 Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light Photoresist SiO 2 p substrate

27 Lithography Expose photoresist through n-well mask Strip off exposed photoresist Photoresist SiO 2 p substrate

28 Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed Photoresist SiO 2 p substrate

29 Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn t melt in next step SiO 2 p substrate

30 n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO 2, only enter exposed Si SiO 2 n well

31 Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps p substrate n well

32 Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH 4 ) Forms many small crystals called polysilicon Heavily doped to be good conductor Polysilicon Thin gate oxide p substrate n well

33 Polysilicon Patterning Use same lithography process to pattern polysilicon Polysilicon Polysilicon Thin gate oxide p substrate n well

34 Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nmos source, drain, and n- well contact p substrate n well

35 N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn t melt during later processing n+ Diffusion p substrate n well

36 N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion n+ n+ n+ p substrate n well

37 N-diffusion cont. Strip off oxide to complete patterning step n+ n+ n+ p substrate n well

38 P-Diffusion Similar set of steps form p+ diffusion regions for pmos source and drain and substrate contact p+ Diffusion p+ n+ n+ p+ p+ n+ p substrate n well

39 Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed Contact p+ n+ n+ p+ p+ n+ Thick field oxide p substrate n well

40 Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires Metal p+ n+ n+ p+ p+ n+ Metal Thick field oxide p substrate n well

41 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

42 Symbols of MOS Transistor

43 Cont...

44 CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation

45 Intra-Layer Design Rules Same Potential Different Potential Well 10 0 or 6 9 Polysilicon 2 2 Active Select Contact or Via Hole 2 2 Metal1 Metal

46 Transistor Layout Transistor

47 Via s and Contacts 2 1 Via Metal to Active Contact 1 Metal to Poly Contact

48 Stick Diagrams VLSI design aims to translate circuit concepts onto silicon. stick diagrams are a means of capturing topography and layer information using simple diagrams. Stick diagrams convey layer information through colour codes (or monochrome encoding). Acts as an interface between symbolic circuit and the actual layout. 48

49 Stick Diagrams Does show all components/vias. It shows relative placement of components. Goes one step closer to the layout Helps plan the layout and routing 49

50 Stick Diagrams Does not show Exact placement of components Transistor sizes Wire lengths, wire widths, tub boundaries. Any other low level details such as parasitics.. 50

51 Stick Diagrams Notations Metal 1 poly ndiff pdiff Can also draw in shades of gray/line style.

52 Stick Diagrams Some rules Rule 1. When two or more sticks of the same type cross or touch each other that represents electrical contact. 52

53 Stick Diagrams Some rules Rule 2. When two or more sticks of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).

54 Rule 3. Stick Diagrams Some rules When a poly crosses diffusion it represents a transistor. 54

55 Stick Diagrams Some rules Rule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pmos must lie on one side of the line and all nmos will have to be on the other side.

56 How to draw Stick Diagrams

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58 Power A Out C B Ground 58

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60 3 modes of transistor channel Accumulation Mode Depletion Mode Inversion Mode

61 Accumulation Mode

62 Depletion mode

63 Inversion Mode

64 NMOS Transistor Opertion

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67 Body Effect Threshold voltage is increased when back bias voltage is increased Junction between channel and substrate must be reverse biased to reduce current leakage. Vsb >0 for NMOS Vsb <0 for PMOS

68 MOS Device Equation In Linear region, I ds depends on How much charge is in the channel? How fast is the charge moving?

69 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ox WL/t ox = C ox WL V = V gc V t = (V gs V ds /2) V t t ox L n+ n+ p-type body polysilicon gate W SiO2 gate oxide (good insulator, ox = 3.9) gate + + source V gs C g V gd drain - - channel n+ - + n+ V s V g V ds p-type body V d

70 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = E E = V ds /L called mobility Time for carrier to cross channel: t = L / v

71 nmos Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I ds Qchannel t W V C V V V L ds ox gs t 2 ds V V V ds V 2 gs t ds = C ox W L

72 nmos Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current V I V V dsat V 2 ds gs t dsat 2 V gs V t 2

73 nmos I-V Summary Shockley 1 st order transistor models 0 V I V V ds V V V 2 ds gs t ds ds dsat V gs V t cutoff linear 2 2 V V V V gs t ds dsat saturation MOS devices Slide 73

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76 MOS Scaling What is Scaling? Reduction in size of an MOS chip by reducing the dimensions of MOSFETs and interconnects. Reduction is symmetric and preserves geometric ratios which are important to the functioning of the chip. Ideally, allows design reuse. Two major forms of scaling Full scaling (constant-field scaling) All dimensions are scaled by S and the supply voltage and other voltages are so scaled. Constant-voltage scaling The voltages are not scaled and, in some cases, dimensions associated with voltage are not scaled. 76

77 MOS Scaling Quantity Sensitivity Constant Field Constant Voltage Scaling Parameters Length L 1/S 1/S Width W 1/S 1/S Gate Oxide Thickness t ox 1/S 1/S Supply Voltage V dd 1/S 1 Threshold Voltage V T0 1/S 1 Doping Density N A, N D S S 2 Device Characteristics Area (A) WL 1/S 2 1/S 2 W/Lt ox S S D-S Current (I DS ) (V dd - v T ) 2 1/S S Gate Capacitance (C g ) WL/t ox 1/S 1/S Transistor On-Resistance (R tr ) V dd /I DS 1 S Intrinsic Gate Delay ( ) R tr C g 1/S 1/S Clock Frequency f f f Power Dissipation (P) I DS V dd 1/S 2 S Power Dissipation Density (P/A) P/A 1 S 3 77

78 MOS Scaling Disadvantages of Constant Voltage Scaling Practical, since the power supply and signal voltage are unchanged But, I DS => SI DS. W => W/S and x j => x j /S for the source and drain (same for metal width and thickness). So J D => S3J D, increasing current density by S3. Causes metal migration and self-heating in interconnects. Since V dd => V dd and I DS => SI DS, the power P => SP. The area A => A/S 2. The power density per unit area increases by factor S3. Cause localized heating and heat dissipation problems. Electric field increases by factor S. Can cause failures such as oxide breakdown, punch-through, and hot electron charging of the oxide. 78

79 Small Geometry Effects Short-Channel Effects General Due to small dimensions Effects always present, but masked for larger channel lengths Effects absent until a channel dimension becomes small Short Channel Effects What is a short-channel device? The effective channel length (L eff ) is the same order of magnitude as the source and drain junction depth (x j ). Velocity Saturation and Surface Mobility Degradation Drift velocity v d for channel electrons is proportional to electric field along channel for electric fields of 10 5 V/cm (as occur as L becomes small with V DD fixed), v d saturates and becomes a constant v d(sat) = 10 7 cm/s. This reduces I D(SAT) which no longer depends quadratically on V GS & is linearly dependent on V GS when fully velocity saturated. 79

80 Small Geometry Effects Short-Channel Effects (Cont.) The drain current is linearly dependent on V GS when fully velocity saturated. The vertical field (E x ) effects cause μ n to decline represented by effective surface mobility μ n(eff). 80

81 Small Geometry Effects Short-Channel Effects (Cont.) Channel Depletion Region Charge Reduction Often viewed as the short channel effect At the source and drain ends of the channel, channel depletion region charge is actually depletion charge for the source and drain For L large, attributing this charge to the channel results in small errors But for short-channel devices, the proportion of the depletion charge tied to the source and drain becomes large V S =0 L V GS >VT0 V DS (p+) (p-si) Source n+ Junction Depletion Region L S Oxide Gate-induced Buck Depletion Region V B =0 L D Drain n+ Junction Depletion Region (p+) 81

82 Small Geometry Effects Channel Depletion Region Charge Reduction (Cont.) The reduction in charge is represented by the change of the channel depletion region cross-section from a rectangle of length L and depth x dm to a trapezoid with lengths L and L-ΔL S - ΔL D and depth x dm. This trapezoid is equivalent to a rectangle with length: L 1 LS 2L Thus, the channel charge per unit area is reduced by the factor: 1 L S Next, need ΔL S and ΔL D in terms of the source and drain junction depths and depletion region junction depth using more geometric arguments. Once this is done, the resulting reduction in threshold voltage V T due to the short channel effect can be written as: L 2L D L D 82

83 Small Geometry Effects Channel Depletion Region Charge Reduction (Cont.) (x j +x dd ) 2 =x dm2 +(x j + L D ) 2 L D =x j + x j2 - (x dm2 -x dd2 )+2x j x dd x j ( 1+ 2x dd /x j -1) Similarly, L S =x j + x j2 -(x dm2 -x ds2 )+2x j x ds x j ( 1+ 2x ds /x j -1) Therefore, V T 0 1 C ox 2q Si N A 2 F x j 2L 1 2x x ds j 1 1 2x x dd j 1 L D x j x dm n+ (p-si) Junction Depletion Region 83

84 Small Geometry Effects Narrow-Channel Effect W is on the same order of the maximum depletion region thickness x dm. The channel depletion region spreads out under the polysilicon at its rises over the thick oxide. Thus, there is extra charge in the depletion region. The increase in V T0 due to this extra charge is 1 xdm V T 0 2q N A 2 Si F Cox W κ is an empirical parameter dependent upon the assumed added charge cross-section. This increase of V T0 may offset much of the short channel effect which is subtracted from V T0. Drain Diffusion (n + ) Gate Thin Gate Oxide x dm Thick Field Oxide Q NC Substrate (p) W Q NC 84

85 Small Geometry Effects Subthreshold Condition The potential barrier that prevents channel formation is actually controlled by both the gate voltage V GS and the drain voltage V DS V DS lowers this potential, an effect known as DIBL (Drain-Induced Barrier Lowering). If the barrier is lowered sufficiently by V GS and V DS, then there is channel formation for V GS < V T0. Subthreshold current is the result. qd Wx n c 0 I D ( subthreshold) LB Upward curvature of the I D versus V GS curve for V GS < V T with V DS 0. n e q r kt e q kt A V GS B V DS 85

86 Small Geometry Effects Other Effects Punch-Through Merging of depletion regions of the source and drain. Carriers injected by the source into the depletion region are swept by the strong field to the drain. With the deep depletion, a large current under limited control of V GS and V SB results. Thus, normal operation of devices in punch-through not feasible. Might cause permanent damage to transistors by localized melting of material. Thinning of t ox As oxide becomes thin, localized sites of nonuniform oxide growth (pinholes) can occur. Can cause electrical shorts between the gate and substrate. Also, dielectric strength of the thin oxide may permit oxide breakdown due to application of an electric field in excess of breakdown field. May cause permanent damage due to current flow through the oxide. 86

87 Small Geometry Effects Other Effects Hot Electron Effects High electric fields in both the channel and pinch-off region for short channel lengths occur for small L. Particularly apparent in the pinch-off region where voltage V DS V D(SAT) large with L L eff small causes very high fields. High electric fields accelerate electrons which have sufficient energy with the accompanying vertical field to be injected into the oxide and are trapped in defect sites or contribute to interface states. These are called hot electrons. Resulting trapped charge increases V T and otherwise affects transconductance, reducing the drain current. Since these effects are concentrated at the drain end of the channel, the effects produce asymmetry in the I-V characteristics. Effect further aggravated by impact ionization. 87

88 MOSFET Capacitances Transistor Dimensions Y (n+) L D Gate L D (n+) W L M Source t ox Gate Oxide Drain (p+) n+ L x j n+ (p+) Substrate (p-si) L M : mask length of the gate L: actual channel length L D : gate-drain overlap Y: typical diffusion length W: length of the source and drain diffusion region 88

89 MOSFET Capacitances Oxide Capacitances Parameters studied so far apply to steady-state (DC) behavior. We need add parameters modeling transient behavior. MOSFET capacitances are distributed and complex. But, for tractable modeling, we use lumped approximations. Two categories of capacitances: 1) oxide-related and 2) junction. Inter-terminal capacitances result as follows: C gb D C gd C db G MOSFET (DC Model) B C gs C sb S 89

90 MOSFET Capacitances Overlap Capacitances Capacitances C gb, C gs, and C gd Have the thin oxide as their dielectric Overlap Capacitances Two special components of C gs and C gd caused by the lateral diffusion under the gate and thin oxide C GS(overlap) = C ox WL D C GD(overlap) = C ox WL D L D : lateral diffusion length W : the width of channel C ox = ε ox /t ox : capacitance per unit area Theses overlap capacitances are bias independent and are added components of C gs and C gd. 90

91 MOSFET Capacitances Gate-to-Channel Charge Capacitances Remaining oxide capacitances not fixed, but are dependent in the mode of operation of the transistor; referred to as being bias-dependent. Capacitances between the gate and source, and the gate and drain are really distributed capacitances between the gate and the channel apportioned to the source and drain. Cutoff No channel formation => C gs = C gd = 0. The gate capacitance to the substrate C gb = C ox W L Linear The channel has formed and the capacitance is from the gate to the source and drain, not to the substrate. Thus C gb =0 and Cgs Cgd (Cox W L)/2 91

92 MOSFET Capacitances Gate-to-Channel Charge Capacitances (Cont.) Saturation In saturation, the channel does not extend to the drain. Thus, Cgd=0 and Cgs (Cox W L)*2/3 Capacitance Cut-off Linear Saturation C gb (total) C ox WL 0 0 C gd (total) C ox WL D C ox WL/2+C ox WL D C ox WL D C gs (total) C ox WL D C ox WL/2+ C ox WL D 2C ox WL/3+ C ox WL D This component of input capacitance is directly proportional to L and W and inversely proportional to tox. 92

93 MOSFET Capacitances Gate-to-Channel Charge Capacitances (Cont.) Junction Capacitances Capacitances associated with the source and the drain Capacitances of the reversed biased substrate-tosource and substrate-to-drain p-n junctions. Lumped, but if the diffusion used as a conductor of any length, both its capacitance and resistance need to be modeled in a way that tends more toward a distributed model which is used for resistive interconnect. 93

94 The Geometry MOSFET Capacitances Junction Capacitance Geometry Y G D W xj Junction between p substrate and n+ drain (Bottom) Area: W(Y+x j ) = AD Junction between p+ channel stop and n+ drain (Sidewalls) Area: x j (W+2Y) = x j PD 94

95 MOSFET Capacitances Junction Capacitance/Unit Area Two junction capacitances per unit area for each distinct diffusion region, the bottom capacitance and the sidewall. Equations are the same, but values different. Thus, we use a single value C j which is the capacitance of a p-n junction diode. Recall that most of the depletion region in a diode lies in the region with the lower impunity concentration, in this case, the p-type substrate. Finding the depletion region thickness in term of basic physical parameters and V the applied voltage (note that V is negative since the junction is reversed biased). x d 2 q S i N N A A N N D D 0 V 95

96 MOSFET Capacitances Junction Capacitance/Unit Area (Continued) The junction potential in this equation is kt 0 ln q N A N 2 ni The total depletion region charge can be calculated by using x d : N A N D N A N D Q j Aq xd A 2 S q V i 0 N A N D N A N D D The capacitance found by differentiating Q j with respect to V to give: with C C j ( V ) j0 dq dv j AC j0 ( 1 V / 0) S q i N A N 2 N A N D D 1/

97 MOSFET Capacitances Junction Capacitance - Approximations Approximation for Manual Calculations The voltage dependence of C j (V) makes manual calculations difficult. An equivalent large-signal capacitance for a voltage change from V 1 to V 2 can be defined as C eq = Q/ V = (Q j (V 2 )-Q j (V 1 ))/(V 2 -V 1 ) The formula of this equivalent large-signal capacitance is derived in the book with the final version: C eq =AC j0 K eq where K eq (0<K eq <1) is the voltage equivalence factor, K 0 eq 0 V 2 0 V V 2 V 97

98 THANK YOU

99 VLSI Design (EEC-703) Unit II MOS Inverter

100 CMOS Inverter

101 Relation between voltages for the three regions of a cmos inverter

102 CMOS Invereter Characterstics

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105 CMOS Inverter DC Transfer Charasteristic and operating Regions

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107 NMOS Inverter For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. Once the operation and characterization of an inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.

108 NMOS Inverter with Resistive Load

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112 Fig (a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic; (c) transfer characteristic.

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122 Given target delay value τphl and τplh the minimum channel widths of the NMOS transistor and the PMOS transistor which satisfy these delay can be calculated by solving Wn and Wp.