MOS Transistor Theory

Transcription

1 MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 MOS Transistor Theory Study conducting channel between source and drain Modulated by voltage applied to the gate (voltagecontrolled device) nmos transistor: majority carriers are electrons (greater mobility), p-substrate doped (positively doped) pmos transistor: majority carriers are holes (less mobility), n-substrate (negatively doped) EE 261 Krish Chakrabarty 2 1

2 Some Notes on Technology Trends 1971: Intel 4004, 2300 transistors, 16 pins/package 1972: Intel 8008, 3300 transistors, 18 pins/package 1979: Motorola MC68000, transistors, 64 pins/package 8 MHz clock speed (now you know why it s the 68,000 series!) 1984: Motorola MC68020, transistors, on-chip cache (first time), four pipeline stages Projection for 2004: 4.1 km of metal interconnect 7 layers of metal 1 micron spacing between layers EE 261 Krish Chakrabarty 3 Now that you know what s CMOS, what is JMOS? JMOS: Just a Matter Of Software! Why are computer/ic shipments sent when they are sent by car, air, etc? Send by car: shipment! Send by ship: cargo! EE 261 Krish Chakrabarty 4 2

3 Source Gate Biasing Gate SiO 2 Drain n + Channel n E p-substrate V gs =0: no current flows from source to drain (insulated by two reverse biased pn junctions V gs >0: electric field created across substrate V SS (Gnd) Electrons accumulate under gate: region changes from p-type to n-type Conduction path between source and drain EE 261 Krish Chakrabarty 5 p-substrate nmos Device Behavior Polysilicon gate Oxide insulator Inversion Region (n-type) Depletion region Depletion region V gs << V t Accumulation mode V gs = V t Depletion mode V gs > V t Inversion mode Enhancement-mode transistor: Conducts when gate bias V gs > V t Depletion-mode transistor: Conducts when gate bias is zero EE 261 Krish Chakrabarty 6 3

4 Transistor Operating Regions Cut-off region: accumulation mode, zero current flow Linear region: V ds <= V gs -V t, weak inversion layer, drain current depends on V gs and V ds Saturated region: V ds > V gs -V t, strong inversion layer, drain current independent of V ds EE 261 Krish Chakrabarty 7 Threshold Voltage: Concept S V GS + - G D n+ n+ n-channel p-substrate Depletion R egion B EE 261 Krish Chakrabarty 8 4

5 Current-Voltage Relations S V GS G V DS D I D n + V(x) + n + L x p-substrate B M OS transistorand its bias conditions EE 261 Krish Chakrabarty 9 Current-Voltage Relations EE 261 Krish Chakrabarty 10 5

6 Current-Voltage Relations k n : transconductance of transistor W : width-to-length ratio L As W increases, more carriers available to conduct current As L increases, V ds diminishes in effect (more voltage drop). Takes longer to push carriers across the transistor, reducing current flow EE 261 Krish Chakrabarty 11 Typical Parameter Values k V t n-type 24 microa/v 2 0.8V p-type 9 microa/v 2-0.8V Why is k higher for n-type transistors? EE 261 Krish Chakrabarty 12 6

7 Transistor in Saturation V GS G V DS > V GS - V T S D n+ - + V GS - V T n+ Channel is pinched off EE 261 Krish Chakrabarty 13 The Gate Capacitance EE 261 Krish Chakrabarty 14 7

8 Average Gate Capacitance Different distri butions of gate capacitan ce for varying operating conditio ns Most import ant regions in al digit design: saturation and f cut-o EE 261 Krish Chakrabarty 15 Diffusion Capacitance EE 261 Krish Chakrabarty 16 8

9 Threshold Variations V T Long-channel threshold Low V DS threshold L Threshold as a function of the length(for low V DS ) Drain-induced barrier lowering (for low L) EE 261 Krish Chakrabarty 17 Parasitic Resistances G Polysilicon gate L D Drain contact V GS,e f S R S R D D W Drain R S = (L S /W)R + R C R D = (L D /W)R + R C R C : contact resistance R : sheet resistance per square of drain-source diffusion EE 261 Krish Chakrabarty 18 9

10 Body Effect Many MOS devices on a common substrate Substrate voltage of all devices are normally equal But several devices may be connected in series Increase in source-to-substrate voltage as we proceed vertically along the chain V 12 g2 g1 V11 d2 s2 d1 s1 V sb2 = 0 V sb1 = 0 Net effect: slight increase in threshold voltage V t, V t2 >V t1 EE 261 Krish Chakrabarty 19 10