Basic Electronics. Introductory Lecture Course for. Technology and Instrumentation in Particle Physics Chicago, Illinois June 9-14, 2011

Transcription

1 Basic Electronics Introductory Lecture Course for Technology and Instrumentation in Particle Physics 2011 Chicago, Illinois June 9-14, 2011 Presented By Gary Drake Argonne National Laboratory Session 3

2 Session 3 Semiconductor Devices Basic Electronics Special Lecture for TIPP

3 Preliminary Concepts Resistivity Revisited L R = L / A Area A = 1 / = 2 m / (n q ) n, v d,, Units: Kg-meter 3 / Coulomb-sec = Ohm-meter (or often, Ohm-cm) Only depends on physical properties Resitivity of Materials Metals 10-6 to cm Upper electron shells nearly empty Semiconductors 10-3 to cm Partially filled shells Bonds covalently to form weakly stable structures Insulators > cm Completely filled shells Basic Electronics Special Lecture for TIPP

4 Preliminary Concepts Semiconductors on the Periodic Chart Basic Electronics Special Lecture for TIPP

5 Preliminary Concepts Atomic Structure of Silicon Group IVA Electron structure Silicon: 1S2 2S2 2P6 3S2 3P2 Z = 14 4 / 8 positions filled 4 empty positions in the 3P shell Represented as: Si Each line is an electron in the 3 rd shell Covalent Bonding Intrinsic silicon bonds covalently in a crystalline structure, sharing electrons with neighbors to completely fill the 3P shell Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Bonds can break from thermal energy or E field to give mobile charge Basic Electronics Special Lecture for TIPP

6 Preliminary Concepts Adding Impurities into Silicon Consider Phosphorous Group VA 3 empty positions Phosphorous: 1S2 2S2 2P6 3S2 3P3 Z = 15 5 / 8 positions filled Represented as: P Each line is an electron in the 3 rd shell Introduction into Silicon Crystalline Structure Extra electron is weakly bound, and easily removed Donor Impurity Si Si Si Si Si Si Si P Si Si Si Si Si Si Si Basic Electronics Special Lecture for TIPP

7 Preliminary Concepts Adding Impurities into Silicon (Continued) Consider Aluminum = Group IIIA Aluminum: 1S2 2S2 2P6 3S2 3P1 Z = 13 3 / 8 positions filled 5 empty positions Represented as: Al Each line is an electron in the 3 rd shell Introduction into Silicon Crystalline Structure Missing electron is weakly accepted into lattice Acceptor Impurity Concept of mobile holes When electron is captured, hole moves from location to location Si Si Si Si Si Si Si Al Si Si Si Si Si Si Si Basic Electronics Special Lecture for TIPP

8 Preliminary Concepts Adding Impurities into Silicon (Continued) Introduction of impurities into intrinsic silicon is called Doping Amount of doping characterized by concentration of charge carriers n i = # intrinsic carriers in pure silicon / unit volume y 1.4E10 / cm 3 N d = # donor atoms / unit volume N a = # acceptor atoms / unit volume N-type Silicon N d N a >> n i High concentration of donor atoms Provides excess electrons to lattice as mobile charge carriers P-type Silicon N a N d >> n i High concentration of acceptor atoms Provides excess holes to lattice as mobile charge 300 o K Basic Electronics Special Lecture for TIPP

9 Preliminary Concepts Adding Impurities into Silicon (Continued) How to make use of mobile charge carriers Bonds can be broken by: Application of an Electric Field» Basic principle of how integrated circuits work Application of Light Photons impart energy» Basic principle of how photo cells work» Use reverse principle for light emitting diodes (LEDs) Heat Kinetic Energy» Basic use for temperature sensors» Generally a bad property for semiconductors Basic Electronics Special Lecture for TIPP

10 PN Junctions Forming a PN Junction Take P-type & N-type silicon, and butt them together Bulk P-Type Bulk N-Type When butt together, opposite charges attract Mobile electrons from N-type silicon attracted to vacancies in P-type Mobile holes from P-type silicon attracted to vacancies in N-type Results in Acceptor & Donor atoms being ionized Creates space charge regions Results in the creation of a built-in Electric Field Ionized Acceptors (not mobile) Electric Field Ionized Donors (not mobile) Bulk P-Type (mobile charge) Bulk N-Type (mobile charge) Space charge region (Depletion region) Basic Electronics Special Lecture for TIPP

11 PN Junctions Biasing a PN Junction Suppose apply a voltage to the PN Junction electrons Bulk P-Type V BIAS holes Bulk N-Type Positive terminal of V BIAS attracts electrons Negative terminal of V BIAS attracts holes Makes space charge region bigger Increases E field across junction Reduces ability of current to flow across junction Reverse Bias Now suppose we reverse the polarity of V BIAS holes Bulk P-Type V BIAS electrons Bulk N-Type Positive terminal of V BIAS adds holes to P region Negative terminal of V BIAS adds electrons to N Makes space charge region smaller Decreases E field across junction Enhances ability of current to flow across junction Majority Carrier: Holes recombine with ionized acceptors Electrons recombine with ionized donors Basic Electronics Special Lecture for TIPP

12 PN Junctions Biasing a PN Junction (Continued) At a critical bias, space charge region disappears holes Bulk P-Type V BIAS electrons Bulk N-Type Built-in E field across junction is gone Now charge carriers provided by V BIAS can move across PN junction Forward Bias Conduction Each new electron/hole pair pushes existing pair out of bulk How much voltage is required to reach forward bias? Answer: Related to how much energy is required to remove bound electrons (or holes) from their nuclei Work Function Depends on doping concentrations Depends on intrinsic carrier concentration Depends on temperature = kt/q ln [ N d N a / n i2 ] Basic Electronics Special Lecture for TIPP

13 Physical Description Diodes Essentially a simple PN Junction Symbol V DIODE V I DIODE DIODE anode cathode Bulk P-Type Bulk N-Type I DIODE IV Characteristics Shockley Diode Equation I D = I S [ e k VD/ (n q T) 1] I D Where: I S = Reverse Saturation Current k = Boltzman Constant (1.38E-23 J/K) T = Temperature ( o Kelvin) q = charge (1.6E19 C/e ) n = quality factor, 1 P n P 2 V IS V T = k T / q = 25.8 room temp D = Thermal Voltage Nonlinear IV relationship In most diodes, I S is very small Basic Electronics Special Lecture for TIPP

14 Diodes IV Characteristics (Cont.) Many diodes exhibit reverse breakdown Zener Effect I D Typical values: V Z ~ 5V 15V Sometimes used for voltage references V Z IS V D Ideal Characteristics Sometimes, it is useful to use a linear approximation V Z I D Typical values V F ~ 0.6V 0.7V for Si Looks like Voltage Source! Approximates current flow in one direction only V F V D Looks like a switch! Basic Electronics Special Lecture for TIPP

15 Circuits Diodes Rarely use Shockley equation in hand calculations SPICE uses Shockley equation or behavioral models Gives accurate solution For hand calculations 2 methods: Use linear approximation Use graphical techniques R 1 V S D 1 R2 V O Basic Electronics Special Lecture for TIPP

16 Circuits (Continued V S Diodes Example Use Linear Approximation: R 1 D 1 R2 V O If diode is OFF: R 1 V S I 1 R 2 V O Ideal: V O = V S R 2 / (R 1 + R 2 ) Valid for: V O < V F Or: V S < V F [ 1 + ( R 1 / R 2 ) ] If diode is ON: V S R 1 I 1 V F I 2 R2 V O Slope [ 1 + (R 1 / R 2 ) ] V O V F V F [ 1 + (R 1 / R 2 ) ] V S V O = V F Valid for: I 1 > 0 Called a Clamp Circuit Or: V S > V F [ 1 + (R 1 / R 2 ) ] Basic Electronics Special Lecture for TIPP

17 Circuits (Continued) Diodes Example Use Graphical Methods Load Line Analysis: Take Diode out Calculate open-circuit voltage I D = 0 Then replace diode with short Calculate short circuit current V D = 0 Plot on diode IV graph Find Operating Point Q V S R 1 I D R2 V O I D I SC = V S / R 2 I DQ IS Q V D V OC = V S V S R 1 V OC I D = 0 R2 V O V OC = V S V DQ Then: V O = I DQ R 2 V S R 1 I SC V D = 0 R2 V O I SC = V S / R2 Don t always have the IV curves for particular diodes Basic Electronics Special Lecture for TIPP

18 Introduction Field Effect Transistors Field Effect Transistors (FETs) are 3-terminal devices, where the current flow between two of the terminals (Drain & Source) is controlled through the use of an electric field applied at the third terminal (Gate), which modulates a conduction channel between the two active terminals. Current flow is achieved by drift currents through the channel Charge carriers are majority carriers Drain (p-type holes, n-type electrons) Current flow is uni-directional Gate Several different kinds: Metal Oxide Semiconductor FET (MOSFET) Junction FET (JFET) Metal Oxide Semiconductor FET (MESFET) High Electron Mobility Transistor (HEMT) Depleted FET (DEPFET) (Many other variations ) Source We will focus on this today Used extensively in HEP Custom ASIC design! Basic Electronics Special Lecture for TIPP

19 MOSFETs Basic Construction Begin with lightly-doped P-type substrate (could be N-type as well ) P Cover surface with layer of silicon dioxide (SiO2) Like glass Insulator Very high resistivity ~ 1E18 -cm SiO 2 Very Important Aspect! P Basic Electronics Special Lecture for TIPP

20 MOSFETs Basic Construction (Continued) Etch openings into the SiO 2 using hydrofluoric acid (HF) Dissolves SiO 2 but not the silicon underneath Etched Openings SiO 2 P Diffuse donor impurities into substrate to make N-type implants Heavy doping N + SiO 2 N P N Basic Electronics Special Lecture for TIPP

21 MOSFETs Basic Construction (Continued) Add metal contacts Applied using Sputtering or Evaporating Metal Metal Contacts SiO 2 N P N Basic construction done All process steps done with masks lithography Define terminals Drain Gate Source SiO 2 N P N Basic Electronics Special Lecture for TIPP

22 MOSFETs Basic Operation Idea is to use the Drain and Source terminals for conduction, and to control the flow of current through these terminals by applying a voltage to the Gate Current I D IG? Gate Voltage V GS Current I D Current I G = 0 due to SiO 2 Drain Gate Source SiO 2 N P N There are three states of operation: Accumulation Depletion Inversion Basic Electronics Special Lecture for TIPP

23 MOSFETs Basic Operation (Continued) Accumulation Occurs when Gate voltage creates an electric field in the region between the N wells that attracts majority carriers holes To attract holes in a P-type substrate, use a negative gate voltage Current I D Gate Voltage V GS Current I D Drain Gate Source SiO 2 N P N The electric field lines from the Gate terminate on the accumulated holes, so that there is no attraction of electrons from the Drain and Source regions Results in no current flow between Drain and Source Basic Electronics Special Lecture for TIPP

24 MOSFETs Basic Operation (Continued) Depletion Occurs when Gate voltage creates an electric field in the region between the N implants that repels majority carriers holes To repel holes in a P-type substrate, use a positive gate voltage Current I D Gate Voltage V GS Current I D Drain Gate Source SiO 2 N P N Note that charge under Gate region is fixed charge, created by removing holes from their acceptor atoms in the P substrate The electric field lines from the Gate terminate on the depleted acceptor atoms Results in no current flow between Drain and Source Basic Electronics Special Lecture for TIPP

25 Basic Operation (Continued) Inversion Occurs when Gate voltage reaches a critical point, where electrons begin to be attracted from N + Drain and Source regions Forms an N-type channel between the Drain and Source Density of electrons in the channel ~ density of donor atoms in the N + implants Current I D MOSFETs Gate Voltage V GS Current I D Drain Gate Source SiO 2 N Depletion Region P N Channel Created by Inversion Now can have flow of electrons from Drain to Source Current flow is controlled by the Gate Voltage The point at which the Gate voltage creates a conductive channel under the Gate is called the Threshold Voltage V Th V GS P V TH Basic Electronics Special Lecture for TIPP

26 MOSFETs Basic Operation (Continued) Inversion (Continued) Suppose now connect a voltage source between Drain and Source Allows current to flow between Drain and Source Results in voltage drop across channel Channel begins to narrow at Drain end V DS Current I D Drain Gate V GS Source SiO 2 N Depletion Region P Narrowing of N Channel Holes pumped into the Drain recombine with ionized acceptors in the channel near the Drain Electric field from the Gate is not strong enough to sustain the full width of the channel at the Drain, resulting in a narrowing of the channel Basic Electronics Special Lecture for TIPP

27 MOSFETs Basic Operation (Continued) Inversion (Continued) If there is a voltage drop across the channel, then the voltage at the drain must be greater than at the source: Current I D (Holes) V DS V GS V V G D VS Drain Gate Source SiO 2 For the channel to exist: V GS > V TH, V GD > V TH Then: V GD = V GS + V SD > V TH Or: V DS < V GS V TH N Depletion Region P Narrowing of N Channel It can be shown that, for this mode of operation, the voltage drop in the channel is resistive, and that the current I D is given by: I D y K V DS [ V GS V TH ], valid for V DS < V GS V TH Basic Electronics Special Lecture for TIPP

28 Basic Operation (Continued) Inversion (Continued) As continue to increase V DS, channel reaches a point where the width goes to 0 at the Drain Pinch-Off As continue to increase VDS, channel begins to recede at the Drain N Depletion Region Beyond Pinch-Off Current I D (Holes) V DS P V GS MOSFETs V V G D VS Drain Gate Source SiO 2 Beyond Pinch-off of N Channel At Pinch-off: V DS = V GS - V TH Beyond Pinch-off: V DS > V GS V TH Now, current flow from drain to source depends only on V GS, not on resistance in channel Drain looks like current source! It can be shown that for Beyond Pinch-off, the Drain looks like a current source, independent of V DS, and that the current I D is given by: I D y K/2 (V GS V TH ) 2, valid for V DS P V GS V TH Basic Electronics Special Lecture for TIPP

29 MOSFETs IV Characteristics Have defined 2 regions of operation Linear region IV characteristics look resistive Voltage-controlled resistor Beyond Pinch-off IV characteristics look like a current source Typically plot I D versus V DS as a function of V GS Family of curves I D V DS = V GS V TH I D V GS = V TH + 4 Linear Region V GS = V TH + 3 V GS = V TH + 2 Linear Region: Beyond Pinch-off Also called the Active Region V GS = V TH + 1 VGS = V TH I D = 0 V DS I D = K V DS V TH [ V GS V TH ], valid for V DS < V GS V TH V GS I D vs V GS in the Active Region Active Region: I D = K/2 (V GS V TH ) 2, valid for V DS P V GS V TH Basic Electronics Special Lecture for TIPP

30 MOSFETs Types of N-Channel MOSFETs Enhancement Mode FETs Channel does not exist at V GS = 0 This is what has been described previously Must provide bias V GS to create I D channel V DS = V GS V TH Electrical Symbol Gate V GS = V TH + 4 V GS = V TH + 3 V GS = V TH + 2 Drain V GS = V TH + 1 V DS V GS = V TH I D = 0 N Channel Enhancement Mode Depletion Mode FETs Channel does exist at V GS = 0 These devices are made this way through doping the channel Must provide negative bias V GS to I D turn channel off V DS = V GS V TH Electrical Symbol Gate V GS = V TH + 4 = +2 V GS = V TH + 3 = +1 V GS = V TH + 2 = 0 V GS = V TH + 1 = -1 V TH = -2 I D = 0 V DS Drain N Channel Depletion Mode Source Source Basic Electronics Special Lecture for TIPP

31 MOSFETs Types of P Channel MOSFETs Enhancement Mode FETs Channel does not exist at V GS = 0 Must provide bias V GS to create channel I D V DS = V GS V TH V GS = V TH + 4 V GS = V TH + 3 V GS = V TH + 2 V GS = V TH + 1 Everything is reversed Same plots, just use absolute value signs Depletion Mode FETs Channel does exist at V GS = 0 Must provide negative bias V GS to I D turn channel off V DS = V GS V TH V GS = V TH + 4 = +2 V GS = V TH + 3 = +1 V GS = V TH + 2 = 0 V GS = V TH + 1 = -1 V DS V DS Electrical Symbol Gate Drain P Channel Enhancement Mode Electrical Symbol Gate Drain P Channel Depletion Mode Source Source Basic Electronics Special Lecture for TIPP

32 Circuit Applications MOSFETS Linear circuits Amplifiers Voltage-controlled current source with gain Excellent when need high input impedance Analog Switches V CTRL V I V O V CC V CTRL Digital Logic CMOS V I V O Basic Electronics Special Lecture for TIPP

33 MOSFETs Linear Circuit Models (N channel Enhancement Mode) Properties: High impedance between Gate and Source In Active Region, Drain-Source looks like a voltage-controlled current source Generally, there are two types of models: DC biasing AC performance General Approach Find DC operating point AC parameters found from small excursions around operating point Load Line Tangential Q Load Line Operating Point Q AC Transconductance: g m = ci D / cv GS Found at Operating Point Q Q Generally, AC response occurs at small deviations around Operating Point Output will be the sum of the DC operating point + the AC response Basic Electronics Special Lecture for TIPP

34 MOSFETs Linear Circuit Models (N channel Enhancement Mode) (Continued) AC Model (assumes operation in active region) Includes voltage-dependent current source with transconductance g m Sometimes includes parasiitic capacitances between Gate and Drain c gd, and between Gate and Source c gs Usually, FET parameters are supplied by the manufacturer Drain Gate + i d + Drain Gate + c gd i d + Drain Gate v gs v ds v gs c gs v ds Source g - m v gs - Source Source Mid-Frequency AC Model Source g - m v gs - High Frequency AC Model Source Spice Models Level 2: Use equations BSIM: Behavorial Much more accurate Takes advantage of knowing process parameters Used extensively for ASIC design Basic Electronics Special Lecture for TIPP

35 MOSFETs Linear Circuits Example Common Source Amplifier N-channel, Enhancement Mode Data from Manufacturer R 3 V S 15V C 1 R 1 400K 10F 7K Q 1 10mA v i R 2 100K V O V TH = 2V V i (t) = 0.1 sin( t) 2V 5V Basic Electronics Special Lecture for TIPP

36 Linear Circuits Example Amplifier DC Analysis Find Q Point Remove all L s & C s > Capacitors open MOSFETs > Inductors short Remove all time-dependent sources > Voltage sources shorted > Current sources open Insert DC model Analyze circuit Find operating point V S 15V v i C 1 R 1 400K 10F R 2 100K V i = 0.1 sin( t) R 3 7K Q 1 V O In general, there is not a DC Model In Beyond Pinch-off, operating point is nonlinear > Must find operating point using info from manufacturer V S 15V R 1 400K R 2 V GS I D R 3 7K V O I D = K/2 (V GS V TH ) 2, valid for V DS P V GS V TH 100K Basic Electronics Special Lecture for TIPP

37 MOSFETs Linear Circuits Example Amplifier DC Analysis Find Q Point (Cont.) 10mA Find Q pt. from calculations g m is slope of tangent line V S 15V R 1 400K R 2 100K V GS g m v gs Find V GS Simple voltage divider: R 3 7K V GS = V S R 2 / (R 1 + R 2 ) = (15) (100K) / (500K) = 3V > V TH Operating in Active Region I D V O 1.1mA I D = K/2 (V GS V TH ) 2 From curve, find: Q 2V 3V 5V V TH = 2V 10mA = K/2 (5 2 ) 2 K = 2.2E-3 Plug in K, V GS, & V TH to find I D at Q: I D = (2.2E-3)/2 (3 2 ) 2 = 1.1mA V O = V S (I D R 3 ) = = 7.3V Now find gm from curve at Q point: g m = ci D / cv GS y 5 ma / 2.5V = 2E-3 Basic Electronics Special Lecture for TIPP Q

38 MOSFETs Linear Circuits (Continued) Example Amplifier (Cont.) AC Analysis Find the Gain Remove all DC sources > Voltage sources short > Current sources open Insert AC model Analyze circuit Find Gain V S 15V v i R 1 400K R 2 100K V i = 0.1 sin( t) R 3 7K C 1 10F Q 1 V O Gate + + Drain Mid-Frequency AC Model v gs - g m v gs v ds - Source Basic Electronics Special Lecture for TIPP

39 MOSFETs Linear Circuits (Continued) Example Amplifier (Cont.) AC Analysis V S 15V C 1 R 1 400K 10F R 3 7K Q 1 V O R 2 Equivalent Circuit at Mid-Frequency with Transistor Model v i 100K v i C 1 10F R 1 R 3 400K R 2 100K v gs Find v gs Node Equation: g m v gs [ v gs / R 1 ] + [ v gs / R 2 ] + [ (v gs v i ) / ( Z C1 ) ] = 0 Z C1 = 1 / ( j C 1 ) vgs [ 1/R1 + 1/R2 + (j w C1) ] = Vi (j w C1) v gs = v i (j w C 1 ) (R 1 R 2 ) R 1 + R 2 + ( j w C 1 R 1 R 2 ) i D 7K v o V i = 0.1 sin( t) Find v o Node Equation: [ v o / R 3 ] + i d = 0 [ v o / R 3 ] + g m v gs = 0 v gs = v i, g m = 2E-3 (from DC analysis) v o = - g m v i R 3 = (0.1) (2E3) = 1.4 v O = - g m R 3 = 14 v i v o (t) = sin ( t) v gs y v i Output is sum of DC + AC parts Basic Electronics Special Lecture for TIPP

40 Analog Switches MOSFETS Principle: Operate either in ohmic region, or at ID = 0 V CTRL I D N-Channel Device V DS = V GS V TH V GS = V TH + 4 V I V O V GS = V TH + 3 V GS = V TH + 2 V CTRL V GS = V TH + 1 V DS V GS = V TH I D = 0 Load line moves, depending on V DS But operate either on V GS = V GS,MAX or on V GS =V TH Basic Electronics Special Lecture for TIPP

41 MOSFETS Digital Logic CMOS Also operating either full on or full off, not in between I D V DS = V GS V TH V GS = V TH + 4 Consider an inverter V GS = V TH + 3 V CC P channel Off N channel On V GS = V TH + 2 V GS = V TH + 1 V GS = V TH I D = 0 P channel On N channel Off V CC V DS V I V O Only have current flow during switching (Approximate Off-to-On transition showing) Switching times: ~nsec psec When not switching No current Low power When V I = V CC, Q 2 ON, Q 1 OFF V O = 0V When V I = 0V, Q 2 OFF, Q 1 ON V O = V CC V IN L H V OUT H L Basic Electronics Special Lecture for TIPP

42 Motivation For many circuits (amplifiers, switches, digital logic), it is useful to have both N-channel and P-channel devices on the same substrate How is this done? P wells & N wells Basic Construction CMOS V GS V GS V V G D VS Drain Gate Source V V G S VD Source Gate Drain SiO 2 N P Substrate N Well P Basis for modern IC fabrication technologies Basic Electronics Special Lecture for TIPP

43 Bipolar Transistors Introduction Bipolar Junction Transistors (BJTs) are 3-terminal devices, where the current flow between two of the terminals (Collector & Emitter) is controlled by injecting charge into the third terminal (Base), which creates diffusion currents between the two active terminals. Current flow is achieved by diffusion currents between the two highly-doped active terminals (Collector & Emitter) Charge carriers are minority carriers Collector (p-type electrons, n-type holes) Current flow is bi-directional (both electrons and holes participate) Base Emitter Basic Electronics Special Lecture for TIPP

44 Bipolar Transistors Basic Construction NPN Transistor Conceptual construction N P N Emitter Collector Base-Emitter Forward Biased Base-Collector Reverse Biased Graphic courtesy of Wikipedia Base Looks like two back-to-back diodes Base-Emitter junction is forward-biased Base-Collector junction is reverse biased N P P N Emitter Collector Base Basic Electronics Special Lecture for TIPP

45 Bipolar Transistors Basic Construction NPN Transistor How does it work? Start by injecting a hole into the Base from external source Extra hole in Base attracts electrons from the Emitter As electrons enter Base from Emitter, they are swept through the base by the strong electric field seen by the reverse-biased Base-Collector junction Generally, N electrons are swept through from Emitter to Collector before hole in Base can migrate to Emitter Gives Current Gain = I C / I B Some holes in Base recombine in Base with electrons from Emitter Most holes make it to the Emitter Graphic courtesy of Wikipedia Typical Construction The unique construction of the junctions, along with the special doping levels, make this work Can have NPN, or PNP Transistors Graphic courtesy of Wikipedia Basic Electronics Special Lecture for TIPP

46 Bipolar Transistors Symbols NPN I B Collector I C PNP I B Emitter V BE I E IV Characteristics NPN Base V BE Emitter V CE I E PNP Base Collector V CE I C I C Saturation Resistive Linear Region I B6 I B5 I B4 I B3 I B2 I B Base- Emitter Junction Looks Like Diode! I C Everything is reversed! I B6 I B5 I B4 I B3 I B2 I B1 I B1 V CE,SAT V CE V BE V CE 0.7V Basic Electronics Special Lecture for TIPP

47 Model - NPN Model For Linear Region DC Model AC Models Hybrid Pi Mid Frequency High Frequency Base Emitter Base Emitter I B Base v be - + v be - i b V BE r r Bipolar Transistors I CE0 c c I C i b g m v be Collector Emitter DC I B I E r d r d i c i c + V CE - + v ce - + v ce - Collector Emitter Collector Emitter I B Base I C Collector V BE Emitter I C V CE IE Generally have a Load Line : DC Model establishes Q point I B6 I B5 I B4 I B3 I B2 I B1 V CE AC Model determines excursion g m v be = i b Basic Electronics Special Lecture for TIPP

48 Linear Circuits Bipolar Transistors Example: NPN Common Emitter Amplifier Data from Manufacturer V S 15V R 1 200K V C C 1 10 F Q 1 R 3 4K I C (ma) I CEO y 0 V BE = 0.7 V r = 23K DC = 70 o = 100 r d yh v i R 2 200K V i = 0.1 sin( t ) R 4 3.5K C 2 10 F V O Frequency of operation: 1 KHz 100 KHz A 25 A 20 A 15 A 10 A 5 A V CE I B Basic Electronics Special Lecture for TIPP

49 Bipolar Transistors Linear Circuits (Cont.) Example (Cont.): NPN Common Emitter Amplifier DC Analysis Find Q Point Remove all L s & C s > Capacitors open > Inductors short Remove all time-dependent sources > Voltage sources shorted > Current sources open Insert DC model Analyze circuit Find operating point V S 15V v i R 1 200K C 1 10 F Q 1 R 2 200K I C V B V C R 4 3.5K Collector VE R 3 4K C 2 10 F + I CEO y 0 V BE = 0.7 V r = 23K DC = 70 o = 100 r d yh V O I CE0 DC I B V CE DC Model for the NPN Transistor Base + - I E - V BE I B Basic Electronics Special Lecture for TIPP

50 Linear Circuits Example (Cont.): DC Analysis Find Q Point Bipolar Transistors V S 15V R 1 200K V B R 2 200K I B + - R 3 4K V BE 0.7V Ref Node V C DC I B V E R 4 3.5K I CEO y 0 V BE = 0.7 V DC = 70 V O Write node equation at V B : [ (V B V S ) / R 1 ] + [ V B / ( R 2 ) ] + I B = 0 At node V E : V E = (I B + DC I B ) R 4 = I B (1 + DC ) R 4 Then, noting that V B and V E are related: V E = V B V BE = V B 0.7 = I B (1 + DC ) R 4 I B = (V B 0.7) / [ (1 + DC ) R 4 ] Solving: V B [ 1/R1 / R 2 + 1/[(1 + DC ) R 4 ] = V S /R / [(1+ DC )R 4 ] Plugging in values, find: V B = 5.56V V E = V B 0.7 = 4.86V I B = = (V B 0.7) / [(1+ DC ) R 4 ] = 19.6 A V C = V S [ DC I B R 3 ] = 9.5V V CE = V C V E = 4.64V, I C = DC I B = 1.37 ma Basic Electronics Special Lecture for TIPP

51 Linear Circuits Example (Cont.) DC Analysis (Cont.) Check results Curve from Mfgr: Bipolar Transistors I C (ma) V S 15V v i 30 A 25 A 20 A 15 A 10 A 5 A R 1 200K R 2 200K R 3 4K C 1 10 F ma Q 5.56V V V CE I B R 4 3.5K 9.5V C 2 10 F V O Approximate operating point Good place to operate for a linear amplifier I CEO y 0 V BE = 0.7 V r = 23K DC = 70 o = 100 r d yh Basic Electronics Special Lecture for TIPP

52 Linear Circuits Example (Cont.): NPN Common Emitter Amplifier AC Analysis Find the Gain Remove all DC sources > Voltage sources short > Current sources open Insert AC model Analyze circuit Find Gain Bipolar Transistors V S 15V v i R 1 200K C 1 10 F Q 1 R 2 200K V B V C R 4 3.5K VE R 3 4K C 2 10 F I CEO y 0 V BE = 0.7 V r = 23K DC = 70 o = 100 r d yh V O V i = 0.1 sin( t ) 1 KHz 100 KHz i b i c Mid-Frequency AC Model for the NPN Transistor Base Emitter + v be - r i b r d + v ce - Collector Emitter Basic Electronics Special Lecture for TIPP

53 Linear Circuits Example (Cont.): AC Analysis (Continued) Bipolar Transistors V S 15V R 1 200K C 1 10 F Q 1 V B V C VE R 3 6K I CEO y 0 V BE = 0.7 V r = 23K DC = 70 o = 100 r d yh More complicated v i R 2 200K R 4 3.5K C 2 10 F V O But, for mid frequencies, it turns out that can treat C 1 & C 2 as short circuits Why?... Impedances are small compared to R 1, R 4 at frequencies > 1000 Hz Can Simplify v i C 1 10 F V i = 0.1 sin( t) R 1 R 3 200K R 2 200K i b r 23K base R 4 3.5K emitter collector Basic Electronics Special Lecture for TIPP C 2 10 F i c o i b 4K v o

54 Linear Circuits Example (Cont.): NPN Common Emitter Amplifier AC Analysis (Continued) Bipolar Transistors V S 15V R 1 200K C 1 10 F Q 1 V B V C VE R 3 4K I CEO y 0 V BE = 0.7 V r = 23K DC = 70 o = 100 r d yh Treating C 1 & C 2 as short circuits: v i R 2 200K R 4 3.5K C 2 10 F V O Much simpler Need only 1 node equation to solve! v i base collector o i b R 1 r R 3 R 2 200K 200K i b i c 23K 4K emitter V i = 0.1 sin( t) Equivalent Circuit at Mid-Frequency with Transistor Model v o Basic Electronics Special Lecture for TIPP

55 Linear Circuits Bipolar Transistors Example (Cont.): NPN Common Emitter Amplifier AC Analysis (Continued) v i base collector o i b R 1 r R 3 R 2 200K 200K v b i b i c 23K 4K emitter Ref Node v c v o I CEO y 0 V BE = 0.7 V r = 23K DC = 70 o = 100 r d yh i b = v i / r p v o = o i b R 3 = o R 3 v i / r p v O v i = o R 3 / r = o R 3 / r = 17.4 Valid over mid-frequencies ~1 KHz 100 KHz For: v i (t) = 0.1 sin( 2 10,000 t) v o (t) = sin( 2 10,000 t) Output is sum of DC + AC parts Basic Electronics Special Lecture for TIPP

56 CMOS Analog Circuits A Basic CMOS, Differential, 1-Stage Amplifier Uses P channel and N channel devices V DD No resistors! Simple circuit can have gains ~1000 ASICS Designer chooses transistor width and length of channel I BIAS V I1 M 3 M 1 M 2 M 4 V I2 M 6 V O Uses same principles introduced in this lecture M 8 M 5 M 7 Each transistor has a role Generally use SPICE to simulate, but first design pass uses hand calculations Basic Electronics Special Lecture for TIPP

57 Inverter CMOS Digital Circuits NOR NAND These are the basic building blocks for flip-flops, counters, registers Programmable Logic, Microprocessors,. Images from allaboutcircuits.com Basic Electronics Special Lecture for TIPP

58 Thank You for your Attention! I hope that you enjoyed the course and found it useful! Basic Electronics Special Lecture for TIPP