2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)
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1 1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2)
2 Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic characteristics ti of electronic circuits it (partially covered)
3 IC Technology
4 Outline 4 Anatomy of integrated circuits Full-Custom (VLSI) IC Technology Semi-Custom (ASIC) IC Technology Programmable Logic Device (PLD) IC Technology
5 MOS Transistor 5 Source, Drain Gate Diffusion area where electrons can flow Can be connected to metal contacts (via s) Polysilicon area where control voltage is applied Oxide Si O 2 Insulator so the gate voltage can t leak IC package IC
6 6 NMOS Transistor fabrication process(1) NMOS Transistor(NMOS FET) S i O 2 Silicon dioxide(0.6 micron) is grown all over the surface P type silicon Ultra-violet light Mask P type silicon Photo-resist material S i O 2 Photolithography S i O 2 Silicon dioxide( 산화막 )(about 0.6 micron) P type silicon
7 7 NMOS Transistor fabrication process(2) gate oxide(about 0.05 micron) is grown Polysilicon is deposited (Low Pressure Chemical Vapor Deposition) Diffuse A S (n type) Source, drain structures are formed n+ n+
8 8 NMOS Transistor fabrication process(3) n+ n+ SiO2 is grown deposit metal(aluminium) to make contact points n+ n+ Length unit --- λ (micron) 2λ λ
9 Four views 9 Logic Transistor Layout Physical
10 NAND 10 Metal layers for routing (~10) PMOS don t like 0 NMOS don t like 1 A stick diagram form the basis for mask sets (layout)
11 IC manufacturing steps 11 Structural t design from functional descriptions to the optimized i circuits at gate level Layout design from the gate level descriptions to the physical layout Tape out Send design to manufacturing Photolithography Drawing patterns by using photo-resist to form barriers for deposition Tape-out
12 Full Custom 12 Very Large Scale Integration ti (VLSI) Placement Placeandoienttansistosand orient transistors Routing Connect transistors Sizingi Make fat, fast wires or thin, slow wires May also need to size buffer Design Rules simple i l rules for correct circuit i function Metal/metal spacing, min poly width
13 Full Custom 13 Best size, power, performance Hand design Horrible time-to-market/flexibility/nre cost Reserve for the most important units in a processor ALU, Instruction fetch Physical design tools Less optimal, but faster Vdd
14 Semi-Custom 14 Gate Array Array of prefabricated gates place and route Higher density, faster time-to-market Does not integrate as well with full-custom Standard Cell A library of pre-designed cell Place and route Lower density, higher complexity Integrate great with full-custom
15 ASea-of-gatesgatearray array 15 f 1 x 1 x 2 x 3 The logic function f 1 = x 2 x 3 +x 1 x 3 in the gate array
16 A section of two rows in a 16 standard cell x 1 f 2 x 2 x 3 f 1 f 1 = x 1 x 2 +x 1 x 3 +x 1 x 2 x 3 f2 = x 1x 2+x 1x 2x 3+x 1x 3
17 Semi-Custom 17 Most popular design style Jack of all trade Good Power, time-to-market, performance, NRE cost, per-unit cost, area Master of none Standard-cell integrated with full custom for critical regions of design
18 Whatwillwelearninthischapter? we learn in this 18 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic characteristics ti of electronic circuits it (partially covered)
19 Programmable Logic Devices 19 Programmable Logic Device Programmable Logic Array, Programmable Array Logic, Field Programmable Gate Array All layers already exist Designers can purchase an IC To implement desired functionality Connections on the IC are either created or destroyed to implement Benefits Very low NRE costs Great Time to Market Drawbacks High unit cost, bad for large volume Power Except special PLA Slower 1600 usable gate, 7.5 ns $7 list price
20 Programmable Logic Devices 20 General purpose chip for implementing logic circuitry It can be customized in different ways Inputs (logic variables) Logic gates and programmable switches Outputs (logic functions)
21 Programmable Logic Array (PLA) 21 Pre-fabricated building block of many AND/OR gates personalized by making or breaking connections among the gates x 1 x 2 x n Input buffers and inverters x 1 x 1 x n x n Programmable array block diagram for sum of products form AND plane P 1 P k OR plane f 1 f m
22 Gate-level Diagram of a PLA 22 x 1 x 2 x 3 Programmable connections P 1 OR plane P2 P 3 P 4 Product terms AND plane f 1 f 2 Sum of Product terms f 1 and f 2??
23 Customary schematic 23 x 1 x 2 x 3 OR plane P 1 P 2 P 3 P 4 AND plane f 1 f 2
24 Programmable Array Logic (PAL) 24 x 1 x 2 x 3 Programmable P 1 Fixed Hardwired P 2 f 1 P 3 P 4 f 2 What is the difference? AND plane
25 Extra circuitry added to OR-gate 25 Select Enable Flip-flop f 1 Output pin D Q Clock Fed back to AND plane
26 A PLD programming unit (courtesy of Data IO Corp) 26 Figure A PLD programming unit (courtesy of Data IO Corp).
27 A PLCC package with socket 27 Printed circuit board
28 28 Structure of a complex programmable logic device (CPLD) /O block I PAL-like block PAL-like block I/O blo ock Interconnection wires I/O block PAL-like block PAL-like block I/O block Figure Structure of a complex programmable logic device (CPLD).
29 A section of the CPLD 29 PAL-like block (details not shown) Programmable switches PAL-like block macrocell D Q D Q D Q
30 CPLD packaging and 30 programming (a) CPLD in a Quad Flat Pack (QFP) package To computer Printed circuit board (b) JTAG programming
31 31 Field-Programmable Gate Arrays (FPGAs) FPGAs are programmable devices that t support relatively large circuits Macrocell of PLDs : 20 gates PAL : 8 macrocell (160 gates) CPLD : 500 macrocell (10,000 gates) Altera 40nm Stratix IV in 2008 Over 2.5 billion TRs, 8.1 M ASIC gate equivalent Different from CPLDs since they do not contain AND and OR planes Provide logic blocks for implementing the logic functions Three main types of resources Logic blocks I/O blocks Interconnection wires
32 Structure of an FPGA 32
33 Logic Blocks 33 Each block has a small number of inputs and one output Usually use lookup tables (LUT) Contains storage cells used to implement a small logic function Each storage cell can hold a 0 or a 1 Stored value is produced as the output of the storage cell
34 Atwo-input lookup table 34 x 1 0/1 x 2 0/1 f x 1 x 2 f 1 0/ / (a) Circuit for a two-input LUT (b) f 1 = x 1 x 2 + x 1 x 2 x 1 If x 1 = f 1 0 x 2 If x 2 =1 2 (c) Storage cell contents in the LUT
35 A three-input LUT 35 x 1 x 2 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 f x 3
36 36 Inclusion of a flip-flop in an FPGA logic block Select Flip-flop In 1 D Q Out In 2 In 3 LUT Clock
37 A section of a programmed 37 FPGA x 3 f f=x 1 x 2 +x 2 x 3 x 1 x 2 x 1 0 x f f 0 2 x 2 x f 1 f f
38 Whatwillwelearninthischapter? we learn in this 38 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic characteristics ti of electronic circuits it (partially covered)
39 NMOS transistor when turned off 39 V G = 0 V SiO 2 V S = 0 V V D Substrate (type p) Source (type n) Drain (type n) When V = 0 V, the transistor is off GS
40 NMOS transistor when turned on 40 V DD V S V G = 5 V V GS >V T SiO 2 I D Triode V GS V V T 0.2V DD Saturation S = 0 V V D = 0V V GS =5V V T Channel (type n) V GS =3V 0 V DS (b) When V = 5 V, the transistor ss is on GS
41 Dynamic Operation of Logic Gates 41 Parasitic capacitance in integrated circuits x N 1 N 2 A f (a) A NOT gate driving another NOT gate V DD parasitic or stray capacitance V DD V A V x V f C (b) The capacitive load at node A
42 Voltage waveforms for logic gates 42 V DD V x 50% 50% Gnd Propagation delay t t PLH Propagation delay t t PHL V DD 90% V A 50% Gnd 10% 90% 10% 50% t r t f
43 Power Dissipation Ec = dv i 0 VDD f 1 2 ( t) V f dt = C V f dt = C V f dv f = 2 CVDD dt Energy dissipated in NMOS and PMOS E = CV DD 2 Power : Energy/unit time P = fcv DD 2 I D E =CV DD2 /2 VDD V x E =CV DD2 /2 I D V f V f V x E =CV DD2 /2 (a) Current flow when input V x changes from 0 V to 5 V (b) Current flow when input V x changes from 5 V to 0 V
44 Fan-in and Fan-out Problems 44 Fan-in problem k input gate : k NMOS or k PMOS transistors in series propagation delays Increasing V OL decreasing V OH : reducing noise margin Fan-out problem x n gates are connected to an output t V f for n = 1 C n = n x C V f To inputs of n other inverters V DD V f for n = 4 C n Gnd 0 Time (c) Propagation times for different values of n
45 Buffers 45 To improve performance to drive a large capacitive load Non-inverting buffer Inverting buffer V DD V x V f + + W 2 W 1 (a) Implementation of a buffer L L (a) Small transistor (b) Larger transistor x f (b) Graphical symbol
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