2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)

Size: px
Start display at page:

Download "2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)"

Transcription

1 1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2)

2 Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic characteristics ti of electronic circuits it (partially covered)

3 IC Technology

4 Outline 4 Anatomy of integrated circuits Full-Custom (VLSI) IC Technology Semi-Custom (ASIC) IC Technology Programmable Logic Device (PLD) IC Technology

5 MOS Transistor 5 Source, Drain Gate Diffusion area where electrons can flow Can be connected to metal contacts (via s) Polysilicon area where control voltage is applied Oxide Si O 2 Insulator so the gate voltage can t leak IC package IC

6 6 NMOS Transistor fabrication process(1) NMOS Transistor(NMOS FET) S i O 2 Silicon dioxide(0.6 micron) is grown all over the surface P type silicon Ultra-violet light Mask P type silicon Photo-resist material S i O 2 Photolithography S i O 2 Silicon dioxide( 산화막 )(about 0.6 micron) P type silicon

7 7 NMOS Transistor fabrication process(2) gate oxide(about 0.05 micron) is grown Polysilicon is deposited (Low Pressure Chemical Vapor Deposition) Diffuse A S (n type) Source, drain structures are formed n+ n+

8 8 NMOS Transistor fabrication process(3) n+ n+ SiO2 is grown deposit metal(aluminium) to make contact points n+ n+ Length unit --- λ (micron) 2λ λ

9 Four views 9 Logic Transistor Layout Physical

10 NAND 10 Metal layers for routing (~10) PMOS don t like 0 NMOS don t like 1 A stick diagram form the basis for mask sets (layout)

11 IC manufacturing steps 11 Structural t design from functional descriptions to the optimized i circuits at gate level Layout design from the gate level descriptions to the physical layout Tape out Send design to manufacturing Photolithography Drawing patterns by using photo-resist to form barriers for deposition Tape-out

12 Full Custom 12 Very Large Scale Integration ti (VLSI) Placement Placeandoienttansistosand orient transistors Routing Connect transistors Sizingi Make fat, fast wires or thin, slow wires May also need to size buffer Design Rules simple i l rules for correct circuit i function Metal/metal spacing, min poly width

13 Full Custom 13 Best size, power, performance Hand design Horrible time-to-market/flexibility/nre cost Reserve for the most important units in a processor ALU, Instruction fetch Physical design tools Less optimal, but faster Vdd

14 Semi-Custom 14 Gate Array Array of prefabricated gates place and route Higher density, faster time-to-market Does not integrate as well with full-custom Standard Cell A library of pre-designed cell Place and route Lower density, higher complexity Integrate great with full-custom

15 ASea-of-gatesgatearray array 15 f 1 x 1 x 2 x 3 The logic function f 1 = x 2 x 3 +x 1 x 3 in the gate array

16 A section of two rows in a 16 standard cell x 1 f 2 x 2 x 3 f 1 f 1 = x 1 x 2 +x 1 x 3 +x 1 x 2 x 3 f2 = x 1x 2+x 1x 2x 3+x 1x 3

17 Semi-Custom 17 Most popular design style Jack of all trade Good Power, time-to-market, performance, NRE cost, per-unit cost, area Master of none Standard-cell integrated with full custom for critical regions of design

18 Whatwillwelearninthischapter? we learn in this 18 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic characteristics ti of electronic circuits it (partially covered)

19 Programmable Logic Devices 19 Programmable Logic Device Programmable Logic Array, Programmable Array Logic, Field Programmable Gate Array All layers already exist Designers can purchase an IC To implement desired functionality Connections on the IC are either created or destroyed to implement Benefits Very low NRE costs Great Time to Market Drawbacks High unit cost, bad for large volume Power Except special PLA Slower 1600 usable gate, 7.5 ns $7 list price

20 Programmable Logic Devices 20 General purpose chip for implementing logic circuitry It can be customized in different ways Inputs (logic variables) Logic gates and programmable switches Outputs (logic functions)

21 Programmable Logic Array (PLA) 21 Pre-fabricated building block of many AND/OR gates personalized by making or breaking connections among the gates x 1 x 2 x n Input buffers and inverters x 1 x 1 x n x n Programmable array block diagram for sum of products form AND plane P 1 P k OR plane f 1 f m

22 Gate-level Diagram of a PLA 22 x 1 x 2 x 3 Programmable connections P 1 OR plane P2 P 3 P 4 Product terms AND plane f 1 f 2 Sum of Product terms f 1 and f 2??

23 Customary schematic 23 x 1 x 2 x 3 OR plane P 1 P 2 P 3 P 4 AND plane f 1 f 2

24 Programmable Array Logic (PAL) 24 x 1 x 2 x 3 Programmable P 1 Fixed Hardwired P 2 f 1 P 3 P 4 f 2 What is the difference? AND plane

25 Extra circuitry added to OR-gate 25 Select Enable Flip-flop f 1 Output pin D Q Clock Fed back to AND plane

26 A PLD programming unit (courtesy of Data IO Corp) 26 Figure A PLD programming unit (courtesy of Data IO Corp).

27 A PLCC package with socket 27 Printed circuit board

28 28 Structure of a complex programmable logic device (CPLD) /O block I PAL-like block PAL-like block I/O blo ock Interconnection wires I/O block PAL-like block PAL-like block I/O block Figure Structure of a complex programmable logic device (CPLD).

29 A section of the CPLD 29 PAL-like block (details not shown) Programmable switches PAL-like block macrocell D Q D Q D Q

30 CPLD packaging and 30 programming (a) CPLD in a Quad Flat Pack (QFP) package To computer Printed circuit board (b) JTAG programming

31 31 Field-Programmable Gate Arrays (FPGAs) FPGAs are programmable devices that t support relatively large circuits Macrocell of PLDs : 20 gates PAL : 8 macrocell (160 gates) CPLD : 500 macrocell (10,000 gates) Altera 40nm Stratix IV in 2008 Over 2.5 billion TRs, 8.1 M ASIC gate equivalent Different from CPLDs since they do not contain AND and OR planes Provide logic blocks for implementing the logic functions Three main types of resources Logic blocks I/O blocks Interconnection wires

32 Structure of an FPGA 32

33 Logic Blocks 33 Each block has a small number of inputs and one output Usually use lookup tables (LUT) Contains storage cells used to implement a small logic function Each storage cell can hold a 0 or a 1 Stored value is produced as the output of the storage cell

34 Atwo-input lookup table 34 x 1 0/1 x 2 0/1 f x 1 x 2 f 1 0/ / (a) Circuit for a two-input LUT (b) f 1 = x 1 x 2 + x 1 x 2 x 1 If x 1 = f 1 0 x 2 If x 2 =1 2 (c) Storage cell contents in the LUT

35 A three-input LUT 35 x 1 x 2 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 f x 3

36 36 Inclusion of a flip-flop in an FPGA logic block Select Flip-flop In 1 D Q Out In 2 In 3 LUT Clock

37 A section of a programmed 37 FPGA x 3 f f=x 1 x 2 +x 2 x 3 x 1 x 2 x 1 0 x f f 0 2 x 2 x f 1 f f

38 Whatwillwelearninthischapter? we learn in this 38 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic characteristics ti of electronic circuits it (partially covered)

39 NMOS transistor when turned off 39 V G = 0 V SiO 2 V S = 0 V V D Substrate (type p) Source (type n) Drain (type n) When V = 0 V, the transistor is off GS

40 NMOS transistor when turned on 40 V DD V S V G = 5 V V GS >V T SiO 2 I D Triode V GS V V T 0.2V DD Saturation S = 0 V V D = 0V V GS =5V V T Channel (type n) V GS =3V 0 V DS (b) When V = 5 V, the transistor ss is on GS

41 Dynamic Operation of Logic Gates 41 Parasitic capacitance in integrated circuits x N 1 N 2 A f (a) A NOT gate driving another NOT gate V DD parasitic or stray capacitance V DD V A V x V f C (b) The capacitive load at node A

42 Voltage waveforms for logic gates 42 V DD V x 50% 50% Gnd Propagation delay t t PLH Propagation delay t t PHL V DD 90% V A 50% Gnd 10% 90% 10% 50% t r t f

43 Power Dissipation Ec = dv i 0 VDD f 1 2 ( t) V f dt = C V f dt = C V f dv f = 2 CVDD dt Energy dissipated in NMOS and PMOS E = CV DD 2 Power : Energy/unit time P = fcv DD 2 I D E =CV DD2 /2 VDD V x E =CV DD2 /2 I D V f V f V x E =CV DD2 /2 (a) Current flow when input V x changes from 0 V to 5 V (b) Current flow when input V x changes from 5 V to 0 V

44 Fan-in and Fan-out Problems 44 Fan-in problem k input gate : k NMOS or k PMOS transistors in series propagation delays Increasing V OL decreasing V OH : reducing noise margin Fan-out problem x n gates are connected to an output t V f for n = 1 C n = n x C V f To inputs of n other inverters V DD V f for n = 4 C n Gnd 0 Time (c) Propagation times for different values of n

45 Buffers 45 To improve performance to drive a large capacitive load Non-inverting buffer Inverting buffer V DD V x V f + + W 2 W 1 (a) Implementation of a buffer L L (a) Small transistor (b) Larger transistor x f (b) Graphical symbol

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: Digital Logic Circuits Chapter 3: Implementation Technology Curtis Nelson Chapter 3 Overview In this chapter you will learn about: How transistors are used as switches; Integrated circuit technology;

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE380 Digital Logic Implementation Technology: Standard Chips and Programmable Logic Devices Dr. D. J. Jackson Lecture 10-1 Standard chips A number of chips, each with a few logic gates, are commonly

More information

FPGA Based System Design

FPGA Based System Design FPGA Based System Design Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 Why VLSI? Integration improves the design: higher speed; lower power; physically smaller. Integration reduces

More information

CMOS Digital Logic Design with Verilog. Chapter1 Digital IC Design &Technology

CMOS Digital Logic Design with Verilog. Chapter1 Digital IC Design &Technology CMOS Digital Logic Design with Verilog Chapter1 Digital IC Design &Technology Chapter Overview: In this chapter we study the concept of digital hardware design & technology. This chapter deals the standard

More information

PE713 FPGA Based System Design

PE713 FPGA Based System Design PE713 FPGA Based System Design Why VLSI? Dept. of EEE, Amrita School of Engineering Why ICs? Dept. of EEE, Amrita School of Engineering IC Classification ANALOG (OR LINEAR) ICs produce, amplify, or respond

More information

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1 Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1. Introduction 2. Metal Oxide Semiconductor (MOS) logic 2.1. Enhancement and depletion mode 2.2. NMOS and PMOS inverter

More information

+1 (479)

+1 (479) Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable

More information

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-

More information

Topic 3. CMOS Fabrication Process

Topic 3. CMOS Fabrication Process Topic 3 CMOS Fabrication Process Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Lecture 3-1 Layout of a Inverter

More information

Basic Fabrication Steps

Basic Fabrication Steps Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor

More information

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018

TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018 TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018 Paper Setter Detail Name Designation Mobile No. E-mail ID Raina Modak Assistant Professor 6290025725 raina.modak@tib.edu.in

More information

Lecture 3, Handouts Page 1. Introduction. EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Simulation Techniques.

Lecture 3, Handouts Page 1. Introduction. EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Simulation Techniques. Introduction EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Techniques Cristian Grecu grecuc@ece.ubc.ca Course web site: http://courses.ece.ubc.ca/353/ What have you learned so far?

More information

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o. Layout of a Inverter Topic 3 CMOS Fabrication Process V DD Q p Peter Cheung Department of Electrical & Electronic Engineering Imperial College London v i v o Q n URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk

More information

Digital Design: An Embedded Systems Approach Using VHDL

Digital Design: An Embedded Systems Approach Using VHDL Digital Design: An Embedded Systems Approach Using Chapter 6 Implementation Fabrics Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using, by Peter J. Ashenden, published

More information

PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Integrated Circuit Layers MOSFETs CMOS Layers Designing FET Arrays EE 432 VLSI Modeling and Design 2 Integrated Circuit Layers

More information

2 MARK QUESTIONS & ANSWERS UNIT1-MOS TRANSISTOR PRINCIPLE

2 MARK QUESTIONS & ANSWERS UNIT1-MOS TRANSISTOR PRINCIPLE 2 MARK QUESTIONS & ANSWERS UNIT1-MOS TRANSISTOR PRINCIPLE 1.What are four generations of Integration Circuits? _ SSI (Small Scale Integration) _ MSI (Medium Scale Integration) _ LSI (Large Scale Integration)

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University.

EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University. EE 434 ASIC and Digital Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries VLSI Design System Specification Functional Design RTL

More information

Chapter 6 DIFFERENT TYPES OF LOGIC GATES

Chapter 6 DIFFERENT TYPES OF LOGIC GATES Chapter 6 DIFFERENT TYPES OF LOGIC GATES Lesson 8 NMOS gates Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline NMOS (n-channel based MOSFETs based circuit) NMOS Features

More information

Propagation Delay, Circuit Timing & Adder Design. ECE 152A Winter 2012

Propagation Delay, Circuit Timing & Adder Design. ECE 152A Winter 2012 Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis

More information

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 23 p. 1/16 EE 42/100 Lecture 23: CMOS Transistors and Logic Gates ELECTRONICS Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad University

More information

Propagation Delay, Circuit Timing & Adder Design

Propagation Delay, Circuit Timing & Adder Design Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis

More information

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 0 ELECTRONICS AND COMMUNICATION ENGINEERING TUTORIAL QUESTION BANK Name : VLSI Design Code : A0 Regulation : R5 Structure :

More information

Digital Electronics Part II - Circuits

Digital Electronics Part II - Circuits Digital Electronics Part II - Circuits Dr. I. J. Wassell Gates from Transistors 1 Introduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits

More information

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important!

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important! EE141 Fall 2005 Lecture 26 Memory (Cont.) Perspectives Administrative Stuff Homework 10 posted just for practice No need to turn in Office hours next week, schedule TBD. HKN review today. Your feedback

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 6 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Contents Array subsystems Gate arrays technology Sea-of-gates Standard cell Macrocell

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

Design cycle for MEMS

Design cycle for MEMS Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor

More information

Lecture 12 Memory Circuits. Memory Architecture: Decoders. Semiconductor Memory Classification. Array-Structured Memory Architecture RWM NVRWM ROM

Lecture 12 Memory Circuits. Memory Architecture: Decoders. Semiconductor Memory Classification. Array-Structured Memory Architecture RWM NVRWM ROM Semiconductor Memory Classification Lecture 12 Memory Circuits RWM NVRWM ROM Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Reading: Weste Ch 8.3.1-8.3.2, Rabaey

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE38 Digital Logic Optimized Implementation of Logic Functions: Karnaugh Maps and Minimum Sum-of-Product Forms Dr. D. J. Jackson Lecture 7- Karnaugh map The key to finding a minimum cost SOP or POS form

More information

Lecture Perspectives. Administrivia

Lecture Perspectives. Administrivia Lecture 29-30 Perspectives Administrivia Final on Friday May 18 12:30-3:30 pm» Location: 251 Hearst Gym Topics all what was covered in class. Review Session Time and Location TBA Lab and hw scores to be

More information

420 Intro to VLSI Design

420 Intro to VLSI Design Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem

More information

EC 1354-Principles of VLSI Design

EC 1354-Principles of VLSI Design EC 1354-Principles of VLSI Design UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY PART-A 1. What are the four generations of integrated circuits? 2. Give the advantages of IC. 3. Give the variety of

More information

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Design Methodologies December 10, 2002 L o g i c T r a n s i s t o r s p e r C h i p ( K ) 1 9 8 1 1

More information

Lecture 30. Perspectives. Digital Integrated Circuits Perspectives

Lecture 30. Perspectives. Digital Integrated Circuits Perspectives Lecture 30 Perspectives Administrivia Final on Friday December 15 8 am Location: 251 Hearst Gym Topics all what was covered in class. Precise reading information will be posted on the web-site Review Session

More information

Written Examination on. Wednesday October 17, 2007,

Written Examination on. Wednesday October 17, 2007, Written Examination on Wednesday October 17, 2007, 08.00-12.00 The textbook and a calculator are allowed on the examination 1. The following logical function is given Q= AB( CD+ CE) + F a. Draw the schematic

More information

EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations

EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies Mar 12, 2013 John Wawrzynek Spring 2013 EECS150 - Lec15-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)

More information

EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies

EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies Feb 14, 2012 John Wawrzynek Spring 2012 EECS150 - Lec09-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)

More information

BICMOS Technology and Fabrication

BICMOS Technology and Fabrication 12-1 BICMOS Technology and Fabrication 12-2 Combines Bipolar and CMOS transistors in a single integrated circuit By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with

More information

BASIC PHYSICAL DESIGN AN OVERVIEW The VLSI design flow for any IC design is as follows

BASIC PHYSICAL DESIGN AN OVERVIEW The VLSI design flow for any IC design is as follows Unit 3 BASIC PHYSICAL DESIGN AN OVERVIEW The VLSI design flow for any IC design is as follows 1.Specification (problem definition) 2.Schematic(gate level design) (equivalence check) 3.Layout (equivalence

More information

Chapter 6 DIFFERENT TYPES OF LOGIC GATES

Chapter 6 DIFFERENT TYPES OF LOGIC GATES Chapter 6 DIFFERENT TYPES OF LOGIC GATES Lesson 9 CMOS gates Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline CMOS (n-channel based MOSFETs based circuit) CMOS Features

More information

VLSI Design. Introduction

VLSI Design. Introduction VLSI Design Introduction Outline Introduction Silicon, pn-junctions and transistors A Brief History Operation of MOS Transistors CMOS circuits Fabrication steps for CMOS circuits Introduction Integrated

More information

VLSI Design. Introduction

VLSI Design. Introduction Tassadaq Hussain VLSI Design Introduction Outcome of this course Problem Aims Objectives Outcomes Data Collection Theoretical Model Mathematical Model Validate Development Analysis and Observation Pseudo

More information

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.

More information

EMT 251 Introduction to IC Design

EMT 251 Introduction to IC Design EMT 251 Introduction to IC Design (Pengantar Rekabentuk Litar Terkamir) Semester II 2011/2012 Introduction to IC design and Transistor Fundamental Some Keywords! Very-large-scale-integration (VLSI) is

More information

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2017 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!

More information

problem grade total

problem grade total Fall 2005 6.012 Microelectronic Devices and Circuits Prof. J. A. del Alamo Name: Recitation: November 16, 2005 Quiz #2 problem grade 1 2 3 4 total General guidelines (please read carefully before starting):

More information

Introduction to VLSI ASIC Design and Technology

Introduction to VLSI ASIC Design and Technology Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics

More information

UNIT-II LOW POWER VLSI DESIGN APPROACHES

UNIT-II LOW POWER VLSI DESIGN APPROACHES UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.

More information

Sticks Diagram & Layout. Part II

Sticks Diagram & Layout. Part II Sticks Diagram & Layout Part II Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped

More information

Microelectronics, BSc course

Microelectronics, BSc course Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT

More information

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203. DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING SUBJECT : EC6601 VLSI DESIGN QUESTION BANK SEM / YEAR: VI / IIIyear B.E. EC6601VLSI

More information

ECE/CoE 0132: FETs and Gates

ECE/CoE 0132: FETs and Gates ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will

More information

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor

More information

Topic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection

Topic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection NMOS Transistors in Series/Parallel Connection Topic 6 CMOS Static & Dynamic Logic Gates Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Transistors can be thought

More information

Digital Systems Laboratory

Digital Systems Laboratory 2012 Fall CSE140L Digital Systems Laboratory Lecture #2 by Dr. Choon Kim CSE Department, UCSD chk034@eng.ucsd.edu Lecture #2 1 Digital Technologies CPU(Central Processing Unit) GPU(Graphics Processing

More information

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits Faculty of Engineering ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits CMOS Technology Complementary MOS, or CMOS, needs both PMOS and NMOS FET devices for their logic gates to be realized

More information

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2016 Khanna Adapted from GATech ESE3060 Slides Lecture

More information

EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline

EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies Oct. 31, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy

More information

Device Technologies. Yau - 1

Device Technologies. Yau - 1 Device Technologies Yau - 1 Objectives After studying the material in this chapter, you will be able to: 1. Identify differences between analog and digital devices and passive and active components. Explain

More information

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Design Methodologies. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Design Methodologies December 10, 2002 L o g i c T r a n s i s t o r s p e r C h i p ( K ) 1 9 8 1 1

More information

Reference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering

Reference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering FPGA Fabrics Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 CPLD / FPGA CPLD Interconnection of several PLD blocks with Programmable interconnect on a single chip Logic blocks executes

More information

Architecture of Computers and Parallel Systems Part 9: Digital Circuits

Architecture of Computers and Parallel Systems Part 9: Digital Circuits Architecture of Computers and Parallel Systems Part 9: Digital Circuits Ing. Petr Olivka petr.olivka@vsb.cz Department of Computer Science FEI VSB-TUO Architecture of Computers and Parallel Systems Part

More information

Digital Design and System Implementation. Overview of Physical Implementations

Digital Design and System Implementation. Overview of Physical Implementations Digital Design and System Implementation Overview of Physical Implementations CMOS devices CMOS transistor circuit functional behavior Basic logic gates Transmission gates Tri-state buffers Flip-flops

More information

Quad 2-Input NAND Gate High-Voltage Silicon-Gate CMOS

Quad 2-Input NAND Gate High-Voltage Silicon-Gate CMOS TECHNICAL DATA Quad 2-Input NAND Gate High-oltage Silicon-Gate CMOS The NAND gates provide the system designer with direct emplementation of the NAND function. Operating oltage Range:.0 to 18 Maximum input

More information

ECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 5: Basic CMOS Inverter Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture

More information

Device Technology( Part 2 ): CMOS IC Technologies

Device Technology( Part 2 ): CMOS IC Technologies 1 Device Technology( Part 2 ): CMOS IC Technologies Chapter 3 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Saroj Kumar Patra, Department of Electronics and Telecommunication, Norwegian

More information

Digital Integrated CircuitDesign

Digital Integrated CircuitDesign Digital Integrated CircuitDesign Lecture 11 BiCMOS PMOS rray Q1 NMOS rray Y NMOS rray Q2 dib brishamifar EE Department IUST Contents Introduction BiCMOS Devices BiCMOS Inverters BiCMOS Gates BiCMOS Drivers

More information

Exam 1 ECE 410 Fall 2002

Exam 1 ECE 410 Fall 2002 NAME: Exa 1 ECE 410 Fall 2002 During this exa you are allowed to use a calculator and the equations sheet provided. You are not allowed to speak to or exchange books, papers, calculators, etc. with other

More information

Digital Integrated Circuits Perspectives. Administrivia

Digital Integrated Circuits Perspectives. Administrivia Lecture 30 Perspectives Administrivia Final on Friday December 14, 2001 8 am Location: 180 Tan Hall Topics all what was covered in class. Review Session - TBA Lab and hw scores to be posted on the web

More information

18nm FinFET. Lecture 30. Perspectives. Administrivia. Power Density. Power will be a problem. Transistor Count

18nm FinFET. Lecture 30. Perspectives. Administrivia. Power Density. Power will be a problem. Transistor Count 18nm FinFET Double-gate structure + raised source/drain Lecture 30 Perspectives Gate Silicon Fin Source BOX Gate X. Huang, et al, 1999 IEDM, p.67~70 Drain Si fin - Body! I d [ua/um] 400-1.50 V 350 300-1.25

More information

The Design and Realization of Basic nmos Digital Devices

The Design and Realization of Basic nmos Digital Devices Proceedings of The National Conference On Undergraduate Research (NCUR) 2004 Indiana University Purdue University Indianapolis, Indiana April 15-17, 2004 The Design and Realization of Basic nmos Digital

More information

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules Reference: Uyemura, John P. "Introduction to

More information

A Case Study of Nanoscale FPGA Programmable Switches with Low Power

A Case Study of Nanoscale FPGA Programmable Switches with Low Power A Case Study of Nanoscale FPGA Programmable Switches with Low Power V.Elamaran 1, Har Narayan Upadhyay 2 1 Assistant Professor, Department of ECE, School of EEE SASTRA University, Tamilnadu - 613401, India

More information

Lecture #29. Moore s Law

Lecture #29. Moore s Law Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday

More information

The entire range of digital ICs is fabricated using either bipolar devices or MOS devices or a combination of the two. Bipolar Family DIODE LOGIC

The entire range of digital ICs is fabricated using either bipolar devices or MOS devices or a combination of the two. Bipolar Family DIODE LOGIC Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 10 Lecture Title:

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 MOS Transistor Theory Study conducting channel between

More information

Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design

Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design Harris Introduction to CMOS VLSI Design (E158) Lecture 9: Cell Design David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158 Lecture

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC0 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC0 74HC/HCT/HCU/HCMOS Logic Package Information The IC0 74HC/HCT/HCU/HCMOS

More information

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation

More information

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation

More information

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience CMOS VLSI IC Design A decent understanding of all tasks required to design and fabricate a chip takes years of experience 1 Commonly used keywords INTEGRATED CIRCUIT (IC) many transistors on one chip VERY

More information

IC Logic Families. Wen-Hung Liao, Ph.D. 5/16/2001

IC Logic Families. Wen-Hung Liao, Ph.D. 5/16/2001 IC Logic Families Wen-Hung Liao, Ph.D. 5/16/2001 Digital IC Terminology Voltage Parameters: V IH (min): high-level input voltage, the minimum voltage level required for a logic 1 at an input. V IL (max):

More information

Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD?

Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD? Improved Inverter: Current-Source Pull-Up MOS Inverter with Current-Source Pull-Up What else could be connected between the drain and? Replace resistor with current source I SUP roc i D v IN v OUT Find

More information

Lecture 9: Cell Design Issues

Lecture 9: Cell Design Issues Lecture 9: Cell Design Issues MAH, AEN EE271 Lecture 9 1 Overview Reading W&E 6.3 to 6.3.6 - FPGA, Gate Array, and Std Cell design W&E 5.3 - Cell design Introduction This lecture will look at some of the

More information

Lecture 13: Interconnects in CMOS Technology

Lecture 13: Interconnects in CMOS Technology Lecture 13: Interconnects in CMOS Technology Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 10/18/18 VLSI-1 Class Notes Introduction Chips are mostly made of wires

More information

Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET

Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET Ch. 13 MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor : I D D-mode E-mode V g The gate oxide is made of dielectric SiO 2 with e = 3.9 Depletion-mode operation ( 공핍형 ): Using an input gate voltage

More information

Introduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Introduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.

More information

CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look

CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic CMOS Inverter: A First Look C L 9/11/26 VLSI

More information

Power and Energy. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

Power and Energy. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr. Power and Energy Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu The Chip is HOT Power consumption increases

More information

Microcontroller Systems. ELET 3232 Topic 13: Load Analysis

Microcontroller Systems. ELET 3232 Topic 13: Load Analysis Microcontroller Systems ELET 3232 Topic 13: Load Analysis 1 Objective To understand hardware constraints on embedded systems Define: Noise Margins Load Currents and Fanout Capacitive Loads Transmission

More information

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Variation. Variation. Process Corners.

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Variation. Variation. Process Corners. ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and Area Today Coping with Variation (from last time) Layout Transistors Gates Design rules Standard

More information

Switching (AC) Characteristics of MOS Inverters. Prof. MacDonald

Switching (AC) Characteristics of MOS Inverters. Prof. MacDonald Switching (AC) Characteristics of MOS Inverters Prof. MacDonald 1 MOS Inverters l Performance is inversely proportional to delay l Delay is time to raise (lower) voltage at nodes node voltage is changed

More information

Lecture 13 CMOS Power Dissipation

Lecture 13 CMOS Power Dissipation EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 13 CMOS Power Dissipation Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken,

More information

UNIT III VLSI CIRCUIT DESIGN PROCESSES. In this chapter we will be studying how to get the schematic into stick diagrams or layouts.

UNIT III VLSI CIRCUIT DESIGN PROCESSES. In this chapter we will be studying how to get the schematic into stick diagrams or layouts. UNIT III VLSI CIRCUIT DESIGN PROCESSES In this chapter we will be studying how to get the schematic into stick diagrams or layouts. MOS circuits are formed on four basic layers: N-diffusion P-diffusion

More information

Computer Architecture (TT 2012)

Computer Architecture (TT 2012) Computer Architecture (TT 212) Laws of Attraction aniel Kroening Oxford University, Computer Science epartment Version 1., 212 . Kroening: Computer Architecture (TT 212) 2 . Kroening: Computer Architecture

More information