EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1

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1 EE 330 Lecture 7 Design Rules IC Fabrication Technology Part 1

2 Review from Last Time Technology Files Provide Information About Process Process Flow (Fabrication Technology) Model Parameters Design Rules Serve as Interface Between Design Engineer and Process Engineer Insist on getting information that is deemed important for a design Limited information available in academia Foundries often sensitive to who gets access to information Customer success and satisfaction is critical to foundries

3 Design Rules Technology Files Process Flow (Fabrication Technology) (will discuss next ) Model Parameters (will discuss in substantially more detail after device operation and more advanced models are introduced) First A preview of what the technology files look like!

4 Typical Design Rules

5 Typical Design Rules (cont)

6 Typical Design Rules (cont)

7 Typical Design Rules (cont)

8 Typical Process Description

9 Typical Process Description (cont)

10 Typical Process Description (cont)

11 Typical Model Parameters

12 Typical Model Parameters (cont)

13 Typical Model Parameters (cont)

14 Typical Model Parameters (cont)

15 Typical Model Parameters (cont)

16 Typical Model Parameters (cont) 98 parameters in this BSIM Model!

17 Typical Model Parameters (cont)

18 Design Rules Technology Files Process Flow (Fabrication Technology) (will discuss next ) Model Parameters (will discuss in substantially more detail after device operation and more advanced models are introduced)

19 Design Rules Give minimum feature sizes, spacing, and other constraints that are acceptable in a process Very large number of devices can be reliably made with the design rules of a process Yield and performance unpredictable and often low if rules are violated Compatible with design rule checker in integrated toolsets

20 Design Rules and Layout consider transistors Layer Map Drain Drain n-well bulk CMOS Process Gate Gate p-active n-active Source Source Poly 1 Metal 1 n-well L W L W contact D G S D G S Layout Layout Layout always represented in a top view in two dimensions

21 Design Rules and Layout consider transistors Drain Drain Layer Map p-active Gate Gate n-active Poly 1 Metal 1 Source Source n-well contact L W L W D G Layout S D G Layout S Everything useful in channel region. All other features just overhead that degrades performance

22 Design Rules L W D G Design rules give minimum feature sizes and spacings S Designers generally do layouts to minimize size of circuit subject to design rule constraints (because yield, cost, and performance usually improve)

23 Design Rules and Layout consider transistors Drain Drain Layer Map p-active n-active Gate Gate Bulk Poly 1 Metal 1 Source Source n-well contact L W D G S B Bulk connection needed Single bulk connection can often be used for several (many) transistors D G S

24 Design Rules and Layout consider transistors Drain Drain Layer Map p-active Gate Gate Bulk n-active Poly 1 Source Source Metal 1 n-well contact D G S Bulk connection needed Single bulk connection can often be used for several (many) transistors if they share the same well B D G S

25 Design Rules and Layout (example) A Y Logic Circuit V DD A M 2 M 4 Y M 1 M 3 W=0.9u L=0.6u Circuit Schematic (Including Device Sizing) A Y Stick Diagram

26 Design Rules (example) A Y V DD Layer Map A Y p-active n-active Poly 1 Metal 1 V SS (GND) Layout n-well contact

27 Design Rules (example) Polygons merged in Geometric Description File (GDF) Separate rectangles generally more convenient to represent

28 Design Rules (example) Design rules must be satisfied throughout the design DRC runs incrementally during layout in most existing tools to flag most problems DRC can catch layout design rule errors but not circuit connection errors

29 Design Rules (example) What is wrong with this layout? Bulk connections missing!

30 Design Rules (example) G D G D B V DD S n-channel S S S A Y G G B D p-channel D Actually 4-terminal device V SS Note diffusions needed for bulk connections Note p-well connections increase area a significant amount Note p-wells are both connected to V DD in this circuit

31 Design Rules (example) Layout with shared p-well reduces area

32 Design Rules (example) Shared p-active can be combined to reduce area Shared n-active can be combined to reduce area

33 Design Rules Design rules can be given in absolute dimensions for every rule Design rules can be parameterized and given relative to a parameter Makes movement from one process to another more convenient Easier for designer to remember Some penalty in area efficiency Often termed λ-based design rules Typically λ is ½ the minimum feature size in a process

34 Design Rules See for design rules

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39 Design Rules See for design rules Some of these files are on class WEB site SCMOS Rules Updated Sept 2005.pdf Mosis Rules Pictorial.pdf

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53 Design Rules Technology Files Process Flow (Fabrication Technology) Model Parameters (will discuss in substantially more detail after device operation and more advanced models are introduced)

54 IC Fabrication Technology See Chapter 3 and a little of Chapter 1 of WH or Chapter 2 GAS for details

55 Back End Front End Generic Process Flow Wafer Fabrication Mask Fabrication Epitaxy Grow or Apply Photoresist Deposit or Implant Etch Strip Planarization Wafer Probe Wafer Dicing Die Attach Wire Attach (bonding) Package Test Ship

56 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Etching Diffusion Oxidation Epitaxy Polysilicon Contacts, Interconnect and Metalization Planarization

57 Review MOS Transistor A A Drain Gate Bulk Source Gate Drain Source n-type n+-type p-type p+-type n-channel MOSFET SiO 2 (insulator) POLY (conductor)

58 Review MOS Transistor A A Drain Gate Source Gate Drain Source Bulk n-type n+-type p-type p+-type SiO 2 (insulator) p-channel MOSFET POLY (conductor)

59 MOS Transistor Source Gate Drain n-channel MOS transistor in Bulk CMOS n-well process with bulk contact Bulk n-channel MOSFET Bulk Source Gate Drain p-substrate serves as the BULK for n- channel devices n-channel MOSFET

60 MOS Transistor Source Gate Drain Bulk p-channel MOS transistor in Bulk CMOS n-well process with bulk contact and well (tub) p-channel MOSFET Bulk Source Gate Drain n-well Serves as the BULK for p-channel device p-channel MOSFET

61 MOS Transistor Bulk Source Gate Drain n-channel MOSFET Single-crystalline silicon Serves as physical support member Lightly doped Vertical dimensions are not linearly depicted Often termed the Bulk

62 MOS Transistor Bulk Source Gate Drain n-channel MOSFET Single-crystalline silicon Serves as physical support member Lightly doped Vertical dimensions are not linearly depicted Often termed the BULK

63 MOS Transistor Conductor (usually polysilicon) Bulk Source Gate Drain Thin insulator (10A to 50A range) n-channel MOSFET Single-crystalline silicon Serves as physical support member Lightly doped (p-doping in the /cm 3 range, silicon in the 2.2x10 22 /cm 3 range) Vertical dimensions are not linearly depicted Often termed the BULK More heavily doped (10 17 /cm 3 range)

64 MOS Transistor Bulk Source Gate Drain p-channel MOSFET Lightly-doped n-type (5x10 16 /cm 3 range) Lightly doped p-type (10 15 /cm 3 range) More heavily-doped p-type (10 18 /cm 3 range)

65 Crystal Preparation Large crystal is grown (pulled) 12 inches (300mm) in diameter and 1 to 2 m long Sliced to 250μm to 500μm thick Prefer to be much thinner but thickness needed for mechanical integrity 4 to 8 cm/hr pull rate T=1430 o C Crystal is sliced to form wafers Cost for 12 wafer around $200 5 companies provide 90% of worlds wafers Somewhere around 400,000 12in wafers/month

66 Crystal Preparation 12in 1 to 2 m 250u tp 500u Some predict newer FABs to be at 450mm (18in) by 2020 but uncertain whether it will happen Lightly-doped silicon Excellent crystalline structure

67 Crystal Preparation From

68 Crystal Preparation Source: WEB

69 Crystal Preparation Source: WEB

70 Crystal Preparation Source: WEB

71 Crystal Preparation Source: WEB

72 Crystal Preparation Source: WEB

73 End of Lecture 7

EE 330 Lecture 7. Design Rules

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