EE70 - Intro. Electronics

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1 EE70 - Intro. Electronics Course website: ~/classes/ee70/fall05 Today s class agenda (November 28, 2005) review Serial/parallel resonant circuits Diode Field Effect Transistor (FET)

2 f 0 = Qs = Qs = 1 2π LC 2π f R 0 L 2 π f 1 0 CR ( ) 0 f = R 1 + jq Z s s f f 0 f f

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4 Series Resonant Circuit as a Bandpass Filter V V R s = 1 + jqs 1 ( f f f f ) 0 0

5 f f + H 0 B 2 f f L 0 B 2 B = f f H L f B = 0 Qs

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8 PARALLEL RESONANCE Z p = 1 ( 1 R ) + j 2 π fc j ( 1 2π fl ) f = 1 R 0 Q p 2π LC 2π f L = Qp = 2π f CR 0 0 Z p R = 1 + jq p ( f f f f ) 0 0

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15 Figure 3.36 Intrinsic silicon crystal.

16 Figure 3.37 Thermal energy can break a bond, creating a vacancy and a free electron, both of which can move freely through the crystal.

17 Figure 3.38 As electrons move to the left to fill a hole, the hole moves to the right.

18 Figure 3.39 n-type silicon is created by adding valence five impurity atoms.

19 Figure 3.40 p-type silicon is created by adding valence three impurity atoms.

20 Figure 3.42 If a pn junction could be formed by joining a p-type crystal to an n-type crystal, a sharp gradient of hole concentration and electron concentration would exist at the junction immediately after joining the crystals.

21 Figure 3.43a Diffusion of majority carriers into the opposite sides causes a depletion region to appear at the junction.

22 Figure 3.43b Diffusion of majority carriers into the opposite sides causes a depletion region to appear at the junction.

23 Figure 3.43c Diffusion of majority carriers into the opposite sides causes a depletion region to appear at the junction.

24 Figure 3.44 Under reverse bias, the depletion region becomes wider.

25 Figure 3.45 Carrier concentrations versus distance for a forward-biased pn junction.

26 Figure 3.46 Parallel-plate capacitor.

27 Figure 3.47 As the reverse bias voltage becomes greater, the charge stored in the depletion region increases.

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29 Shockley Equation i D v D = I s exp 1 nv T V T = V T kt q 26 mv k = J/K is Boltzmann s constant and q = C is the magnitude of the electrical charge of an electron. At a temperature of 300 K, we have

30 LOAD-LINE ANALYSIS OF DIODE CIRCUITS V = Ri + v SS D D

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36 C = I L V T r V V L m V r 2

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39 Peak Inverse Voltage An important aspect of rectifier circuits is the peak inverse voltage (PIV) across the diodes. The capacitance required for a full-wave rectifier is given by: C = I L T 2 V r

40 Field Effect Transistor MOSFET (Metal-Oxide-Semiconductor FET) - Enhancement Type (NMOS, PMOS) - Depletion Type (NMOS, PMOS) JFET (Junction FET) -N channel -P channel

41 NMOS Transistors The device terminals are the drain (D), gate (G), source (S), and body (B). Gate is insulated from the substrate by thin oxide. With a sufficiently large gate voltage n-type channel is induced under the gate which enables conduction between the drain and the source. n-channel enhancement MOSFET showing channel length L and channel width W.

42 Cutoff Region For the gate-source values V GS <V to there will be no channel formed under the gate area, hence drain body junction will be reverse biased and no current will flow. This region is called cutoff. For vgs < Vto the pn junction between drain and body is reverse biased and id=0.

43 Triode (Resistive) Region For gate source voltages V GS >V to and small V DS values the n-type channel formed from drain to source which behaves like resistor. Under this region, the current depends on V DS and excess gate voltage V GS -V to For vgs >Vto a channel of n-type material is induced in the region under the gate. As vgs increases, the channel becomes thicker. For small values of vds,id is proportional to vds. The device behaves as a resistor whose value depends on vgs.

44 Saturation Region As V DS increases, the channel pinches down at the drain end and I D increases more slowly. Finally for V DS > V GS -V to, I D becomes constant. This region of operation is called saturation. As vds increases, the channel pinches down at the drain end and id increases more slowly. Finally for vds> vgs -Vto, id becomes constant.

45 NMOS Characteristic Curves Characteristic curves for an NMOS transistor.

46 NMOS Amplifier The DC source biases the amplifier at a suitable operating point for amplification. Varying sinusoidal signal at the gate changes the drain current. Due to R D, this current would cause large voltage swing at the drain. Simple NMOS amplifier circuit.

47 Load Line Analysis Amplifier analysis has two steps: - Determine the Q-Point - Use small signal circuits to find the gain and impedances. Drain characteristics and load line for the circuit.

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