MOSFETS: Gain & non-linearity

Transcription

1 MOFET: ain & non-linearity source gate Polysilicon wire Heavily doped (n-type or p-type) diffusions W Inter-layer io 2 insulation Very thin (<20Å) high-quality io 2 insulating layer isolates gate from channel region. L drain Channel region: electric field from charges on gate locally inverts type of substrate to create a conducting channel between source and drain. bulk oped (p-type or n-type) silicon substrate MOFETs (metal-oxide-semiconductor field-effect transistors) are four-terminal voltage-controlled switches. Current flows between the diffusion terminals if the voltage on the gate terminal is large enough to create a conducting channel, otherwise the mosfet is off and the diffusion terminals are not connected. Why are MO devices King? L03 - CMO Technology 5

2 FETs as switches The four terminals of a Field Effect Transistor (gate, source, drain and bulk) connect to conducting surfaces that generate a complicated set of electric fields in the channel region which depend on the relative voltages of each terminal. gate inversion happens here n source E h drain n p E v bulk INVERION: A sufficiently strong vertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain. CONUCTION: If a channel exists, a horizontal field will cause a drift current from the drain to the source. L03 - CMO Technology 6

3 Linear operating region V > V TH 0 < V < V sat I L Why is this bigger here than on other side? Larger creates deeper channel which increases I I I proportional to µ 0 (W/L) Increasing Larger V increases drift current but also reduces vertical field component which in turn makes channel less deep. At some point, electrons are traveling as fast as possible through the channel ( velocity saturation ) and the current stops growing linearly. V L03 - CMO Technology 7

4 aturated operating region V > V TH V sat < V I L = L - δl δl V sat -V TH This looks just like a fet with a channel length of L < L. horter L implies greater I. As V increases, δl gets larger. V I = -V TH When V = -V TH the vertical field component is reduced and the channel is pinched-off. Electrons just keep traveling across depletion region Increasing V V L03 - CMO Technology 8

5 NFET ummary + n p n + V 0 Operating regions: - - cut-off: < V TH linear: V TH V < V sat 0.8V I linear saturation -V TH saturation: V TH V V sat V L03 - CMO Technology 9

6 FETs come in two flavors y embedding p-type source and drain in a n-type substrate, we can fabricate a complement to the N-FET: n p n p n p The use of both NFETs and PFETs complimentary transistor types is a key to CMO (complementary MO) logic families. L03 - CMO Technology 10

7 PFET ummary - p n p + V 0 Operating regions: - + cut-off: > V TH 0.8V -V linear: V TH V > V sat - saturation: V TH V V sat -V TH saturation linear -I L03 - CMO Technology 11

8 CMO Inverter = 0v I PU = 1v V in = power supply I PU V out = 2v = 3v = 4v I PU vs V OUT for PULLUP V OUT I P = 0V I P = 5v = 4v = 3v = 2v = 1v I P vs V OUT for PULLOWN V OUT L03 - CMO Technology 12

9 CMO Inverter VTC I pd V in = 0.5V I pu I pd teady state reached when V out reaches value where I pu = I pd. I pu Vout V out V OH V in = 3.5V I pd V in = 1.5V I pu I pd V out I pu V out V in = 4.5V V OL I pu V in = 2.5V V IL V IH V in I pd V out I pd I pu V out When both fets are saturated, small changes in V in produce large changes in V out L03 - CMO Technology 13

10 Think witches V pullup: make this connection when near 0 so that V OUT = V V OUT pulldown: make this connection when near V so that V OUT = 0 L H H L V IL V OUT V IH V IH V OUT V IL L03 - CMO Technology 14

11 tandard Cell Layout for Inverter W: scaled width used in Process-independent design m1/nwell contact m1 power bus m1/pdiff contact pfet Use two narrow mosfets in parallel instead of one wide mosfet m2/m1 via m1/poly contact poly wire m1 wire nfet m1/ndiff contact m1 ground bus m1/substrate contact Physical design of a CMO gate is represented by a mask layout showing where material on each layer (ndiff, pdiff, poly, m1, m2, ) should be placed on the silicon wafer. Each manufacturing process has a set of design rules that determine minimum widths, spacings, overlaps, etc. L03 - CMO Technology 21

12 eyond Inverters: Complementary pullups and pulldowns Now you know what the C in CMO stands for! We want complementary pullup and pulldown logic, i.e., the pulldown should be on when the pullup is off and vice versa. pullup pulldown F(A 1,,An) on off driven 1 off on driven 0 on on driven X off off no connection ince there s plenty of capacitance on the output node, when the output becomes disconnected it remembers its previous voltage -- at least for a while. The memory is the load capacitor s charge. Leakage currents will cause eventual decay of the charge (that s why RAMs need to be refreshed!). L03 - CMO Technology 22

13 What a nice V OH you have... CMO complements Thanks. It runs in the family... conducts when is high conducts when is low A A conducts when A is high and is high: A. conducts when A is low or is low: A+ = A. A A conducts when A is high or is high: A+ conducts when A is low and is low: A. = A+ L03 - CMO Technology 23

14 A pop quiz! What function does this gate compute? A A C NAN 1 0 L03 - CMO Technology 24

15 Here s another A What function does this gate compute? A C NOR 0 0 L03 - CMO Technology 25

16 eneral CMO gate recipe tep 1. Figure out pulldown network that does what you want, e.g., F = A*(+C) (What combination of inputs generates a low output) A C tep 2. Walk the hierarchy replacing nfets with pfets, series subnets with parallel subnets, and parallel subnets with series subnets tep 3. Combine pfet pullup network from tep 2 with nfet pulldown network from tep 1 to form fullycomplementary CMO gate. A A A C C C ut isn t it hard to wire it all up? L03 - CMO Technology 26

17 Emerging ig Issue: Power moves from L to H to L V V OUT moves from H to L to H C V OUT Energy dissipated = C V 2 per gate Power consumed = f n C V 2 per chip C discharges and then recharges where f = frequency of charge/discharge n = number of gates /chip L03 - CMO Technology 27

18 Unfortunately Modern chip (Ultraparc III, Power4, Itanium 2) dissipates from 80W to 150W with a Vdd 1.2V (Power supply current chip is 100 Amps) Ampacity is similar to a big double oven! Cooling challenge is like making the filament of a 100W incandescent lamp cool to the touch! Worse yet Little room left to reduce Vdd nc and f continue to grow L03 - CMO Technology 28

19 Emerging ig Issue: Wires V out R C Today (i.e., 100nm): τ RC 50ps/mm Implies 2ns to traverse a 20mm x 20mm chip This is a long time in a 2Hz processor L03 - CMO Technology 29

20 MOFET features ummary PN junctions provide electrical isolation witch-like behavior controlled by hrinking geometries improves performance CMO features CMO logic is naturally inverting: 1 inputs lead to 0 outputs ood noise margins because V OL = 0, V OH = V complementary logic has high gain No static power dissipation Next time: timing, converting functionality to logic L03 - CMO Technology 30