Problem: 4.6. Lay out an NMOS device with a length of 1 and width of 10. Label all four of the MOSFET s terminals.

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1 Meshack Appikatla Problem: 4.6. Lay out an NMOS device with a length of 1 and width of 10. Label all four of the MOSFET s terminals. Solution: A 10x10 box is drawn on ACTV and then it is surrounded by NSEL. This makes our drain and source. A path with width 1 and layer POLY1 is drawn. This is our gate. A box of PSEL is drawn by the side with ACTV box inside. This can be connected to metal which ensures the body is connected. Now the terminals are drawn with MET1 layer and contacts are made by CONT. Be sure that the DRC rules (for ex. the spacing between contact and metal, extension of poly over active etc.) are satisfied. Now the terminals are labeled with text layer as MET1. Now the layout is checked by going into system, LasiDRC, setup and then go. Check for flags and if there are any flags, go to layout and correct the errors.

2 EE 510 SPRING 2004 HOMEWORK CHAPTER 4 MAEZLIN J AVILA TAYLOR P4.7: Layout a PMOS device with a length of 1 and a width of 20. Label all four of the MOSFET s terminals.

3 4.10) Sketch the cross-sectional views at the line indicated in Fig. 4.xx. Problem 4.11 Sketch the cross sectional views across the lines shown in figure 4.xxx. Edward Kunz

4 Justin Wood Problem 5.5 Solution Due 3/1/04 EE4/ ) Estimate the areas and perimeters of the source/drain in the layout seen in Fig if the length of the device, L, is 2 and the width of a finger, W, is 20. Source: The source consists of three separate sections, which have been highlighted in red above. Based on the information given in the problem (L=2 and W=20), the three sections were estimated to be Wx2L each. Therfore, the total area of the source was estimated to be 3*(W*2L) = 3*(20*2(2)) = 240 units 2 The total source perimeter was estimated to be 3*(2W+2(2L)) = 3*(2*20+2(2*2))=144 units

5 Drain: The drain consists of two separate sections, which have been highlighted in red above. Based on the information given in the problem (L=2 and W=20), the two sections were also estimated to be Wx2L each. Therfore, the total area of the drain was estimated to be 2*(W*2L) = 2*(20*2(2)) = 160 units 2 The total drain perimeter was estimated to be 2*(2W+2(2L)) = 2*(2*20+2(2*2))=96 units

6 PROBLEM 6_1 Low-Pass RC Circuit 6.1 Plot the Magnitude and Phase of v out (AC) in the following circuit. Assume that the MOSFET was fabricated using the 50nm process and is operating in strong inversion. Verify your answer with SPICE. Since the source and drain of the MOSFET are connected to ground, the MOSFET operates as a capacitor. The problem assumes the MOSFET is operating in stronginversion which means V GS > V TH or V TH < 500mV, and fabricated using the 50nm, short-channel process. From Table 5.1, C' ox = 25 ff / µ m. The capacitance between the gate and the source/drain is: CTOT = C' ox W L = ( 25 ff / µ m)( 100µ m)( 100µ m) = 250 pf For the 1mV AC input: 1 j2πfc Vout = Vin R + 1 j2πfc TOT TOT 1 = Vin j2πfc TOT R j2πfc TOT = Vin ( j2πfctot ) Rj2πfCTOT This circuit is a low pass filter. To test it, compute Vout at F low =100Hz & F high = 10MHz. Maezlin J Avila Taylor

7 PROBLEM 6_1 Low-Pass RC Circuit The following is the result of performing an AC small signal analysis of the circuit spanning frequencies from 1Hz to 10MHz. The magnitude of Vout approaches zero as the frequency of Vin increases, as expected of a low-pass filter. Maezlin J Avila Taylor

8 PROBLEM 6_1 Low-Pass RC Circuit *** SPICE Circuit File *Problem 6.1 Low Pass NMOS Filter Header.control destroy all run plot mag(vout) plot ph(vout).endc **.AC LIN MEG.AC DEC MEG.options scale=50nm * MAIN LOW_PASS_NMOS M1 0 Vout 0 0 NMOS L=100 W=100 R1 vn2 Vout 250k VDD vn1 0 DC 500mv AC 0 0 Vin vn2 vn1 DC 0 AC 1mv 0 * 50nm BSIM4 models * * Don't forget the.options scale=50nm if using an Lmin of 1 * 1<Ldrawn<200 10<Wdrawn<10000 Vdd=1V * Change to level=54 when using HSPICE.model nmos nmos level = 14 *deleted a long list to save paper.end.end Maezlin J Avila Taylor

9 Problem 6.2 Rupa Balan If a MOSFET is used as a capacitor in the strong inversion region where the gate is one electrode and the source/drain is the other electrode, does the gate overlap of the source/drain change the capacitance? Why? What is the capacitance? Solution:- In the strong inversion region, the channel of electrons is formed below the gate oxide in case of NMOS shorting the drain and the source. Since source and drain of NMOS are shorted through channel of electrons, gate overlap of source/drain does not change the gate to source/drain capacitance. Capacitance between gate and source/drain =C ox =C ox. W. L. (scale) 2 where W=W drawn and L=L drawn. Problem 6.3 Krishna Duvvada Repeat problem 6.2 when the MOSFET is operating in the accumulation region. Keep in mind that the question is not asking for the capacitance from gate to substrate. Solution:- When the MOSFET operates in the accumulation region, the gate overlap capacitance affects the capacitance from gate to source/drain. Here the drain and source is separated by the substrate which is the resistance. So the gate to drain/source capacitance is the overlap capacitance. Cgs = C ox. Ldiff. W (scale) 2 Problem 6.4 Surendranath C Eruvuru If the oxide thickness of a MOSFET is 40 A o. What is C ox? Solution:- C ox = ε ox /T ox = (8.85 x 3.97 af/µm)/(40 x m) = ff/µm 2

10 KRISHNAMRAJU KURRA HOMEWORK#7 DATE:03/10/04 Problem 6.5. Repeat Ex: 6.5 to get a threshold voltage of 0.8V. Solution: Given V GS = V THN and V SB = 1V Then V S = - V fp + V SB Where V fp = -(KT/q) ln ( N A /n i ) = -26 mv* ln [10 15 (atoms/cm 3 ) / 1.45* (atoms/cm 3 ) ] = -290mV We have X d = [ 2 ε si 2V fp + VSB / qn A = F / µ m V / C / atom 10 atoms / cm cm /10 µ m [ ( ) ( ) ( ( )) ( )( )] 3 = 1.43 µ m We have Q bo = q N A X d ( 1 C ) 10 ( atoms / cm )( cm /10 µ m ) 1.43 µ m 19 =.6 10 ( / atom) = 229 ac/ µ 2 m PROBLEM 6.6 Indira Priyadarshini.Vemula Repeat Ex. 6.3 for a p-channel device with a well doping concentration of atoms/cm 3? Solution: Given N D =10 16 atom/cm 3 γ=(2q si N D ) 1/2 /C ox γ=(2*1.6*10-19 C/atom*11.7*8.85 af/um 2 *10 16 atom/cm 3 * cm 3 /10 12 um 2 ) 1/ ff/um 2 γ=0.328v 1/2

11 Problem 6.7 MESHACK P. APPIKATLA What is the electrostatic potential of the oxide-semiconductor interface when V GS =V THNO. Solution: It will be equal and opposite to the electrostatic potential of the substrate. Vs = -Vfp Where Vs is the electrostatic potential of the interface and Vfp is the electrostatic potential of the substrate. Problem 6.8 Edward Kunz Estimate the ion implant dose required to change the threshold voltage in Ex. 6.4 without Sodium contamination, to 0.8v. Solution: Using values from Ex. 6.4 qni VTHNO = 0.220v+ = 0.8v C' OX C' 1.75 ff OX = µ 2 m 19 q = 1.6*10 C atom *10 C * N 0.8v = 0.220v+ atom 1.75 ff 2 µ m 12 N 1.115*10 atoms I = 2 cm I