EXPERIMENT # 1: REVERSE ENGINEERING OF INTEGRATED CIRCUITS Week of 1/17/05

Transcription

1 EXPERIMENT # 1: REVERSE ENGINEERING OF INTEGRATED CIRCUITS Week of 1/17/5 Experiment #1: Reading: Reverse engineering of integrated circuits Jaeger 9.2: MOS transistor layout and design rules HP4145 basics: ece- The purpose of this experiment is to familiarize the students with actual circuits and the testing of such circuits using the HP4145 parameter analyzer. Circuits previously fabricated by students as well as commercial integrated circuits are examined using a reverse engineering approach. 1.1 You receive a processed wafer containing several single devices, test structures and circuits. Identify the aluminum metal, the field oxide, diffusion oxide and gate oxide. Write down the observed color for each oxide. Identify a transistor and draw a top and crosssectional view like the one in Fig. 9.1 e). Make a picture of the layout to your report. Draw a stick diagram as well as a circuit diagram. Identify the input(s), output(s), power supply and ground. Is it an analog or digital circuit? Can you identify the function of this circuit? 1.2 Set up a program on the parameter analyzer to measure the I-V characteristics of a pmos transistor. The intention is to obtain a set of characteristics as shown in figure 1. Keep in mind that we are measuring p-mos devices, so that all voltages and currents will be negative. Drain current (ma) Drain voltage (V) Figure 1: I-V characteristics of a n-mosfet Bart Van Zeghbroeck - 1/24/5 - LAB experiments ECEN page 3

2 Pick a transistor with 1 µm gate length and measure the W/L ratio. Apply initially a drain-source voltage from to -5 V (using VAR1) and step the gate-source voltage from to -5 V in steps of -1 V (using VAR2). Adjust the voltages if necessary to obtain reasonable I-V characteristics. Measure another transistor with identical layout and overlay the two I-V curves, using the STORE and RECALL feature of the instrument. (on the soft key menu) If the I-V curves differ substantially measure a third transistor. Add your initials to the plot as well as the W/L ratio by editing the comment line (COMMNT softkey). Measure the output conductance (g d = di D /dv DS ) in saturation (i.e. V DS < V GS - V T ). Plot the I-V curves using the PLOT button on the instrument: PLOT 2, 2, 8, 6 [EXECUTE]. You can save the program with the data on disk using SAVE Dxxx [EXECUTE], where D indicates that the data is stored with the program and xxx is a name of your choice. 1.3 Set up another program to measure the square root of the drain current as a function of the gatesource voltage (VAR1 ranging from to -5V, increase the range if necessary). As example is shown in Figure 2. (Drain Current) 1/2 (A 1/2 ) Gate Voltage (V) Figure 2: Square root of the drain current versus gate voltage Apply a large enough voltage at the drain to ensure that the transistor is in saturation. Fit a straight line to the measured curve using the CURSOR, SHORT MARKER and LINE softkeys on the extended (EXTN) softkey menus. (See also the HP4145 Basic commands file). Identify the threshold voltage of the device. Turn of the microscope light, measure the square root of I D again, fit aline to the curve and determine the threshold voltage of the device in the dark. Again add your initials and the W/L ratio of the transistor to the plot by editing the comment line. Bart Van Zeghbroeck - 1/24/5 - LAB experiments ECEN page 4

3 Plot the graph using the PLOT feature and save the program and the data. Additional experiment(s): 1.4 Modify the program of section 1.3 so that you vary the bulk-source voltage, V BS, (VAR2 ranging from to 1 V is steps of 2.5 V). An example is shown in Figure 3. (Drain Current) 1/2 (A 1/2 ) Gate Voltage (V) Figure 3: Square root of I D versus the gate-source voltage for different bulk souce voltage. Measure the threshold voltage at each bulk-source voltage as well as the slope. Since the slope is very similar, make sure you use the same procedure for each measurement. Add you initials and the W/L ratio on the comment line. Plot the graph and save the data. Bart Van Zeghbroeck - 1/24/5 - LAB experiments ECEN page 5

4 Report # 1: Due Week of 1/24/5. READ THIS BEFORE THE LAB AS WELL AS BEFORE LEAVING THE LAB TO ENSURE THAT YOU HAVE ALL DATA NEEDED TO COMPLETE THE REPORT The lab report consist of a brief summary, describing the experiment, its goal and purpose and the key results and conclusions. In addition answer the following questions in sequence. Place graphs, pictures and other material gathered during the lab period in the report with a caption. Do not attach it as an appendix. Report questions: a) List the color of all three oxides. Provide the top and cross-sectional view of the transistor you observed in the lab. Add a picture of the layout to your report. Draw a stick diagram as well as a circuit diagram. Identify the input(s), output(s), power supply and ground. Is it an analog or digital circuit? Can you identify the function of this circuit? b) What is the output conductance (g d = di D /dv DS ) of the transistor you measured? Indicate the gate voltage at which you measured the output conductance. Include the I-V curve plot in your report. Add a figure caption. c) What is the threshold voltage of that same transistor as obtained from the I D versus V GS curve? Attach the plot to your report. Fit the measured curve to the following expression: I D = β/2 V GS - V T and extract the parameter β (β = Κ = µ p C ox W/L). From the parameter β (= K) find the hole mobility µ p in the channel and compare it to the bulk hole mobility in the substrate. Assume the substrate is a 2 Ωcm phosphorous-doped wafer and an oxide thickness t ox = 8 nm. d) Obtain an expression for the transconductance when the transistor is in saturation. Use the data from part c) to find a numeric value for the transconductance at the same gate voltage you obtained the output conductance (part b). Calculate the ratio of the transconductance to the output conductance. This ratio equals the maximum voltage gain one can obtain with this transistor. e) Construct a PSPICE model for the transistor you measured. Use the model to plot the square root of I D versus V GS in saturation. Use LEVEL 1 and LEVEL 2 for the pmos model and compare the curves by overlaying them on the same graph. Which LEVEL reproduces most closely the experimental curves? Which LEVEL provides the most accurate model? Explain the difference between the two. Bart Van Zeghbroeck - 1/24/5 - LAB experiments ECEN page 6

5 Additional experiment(s) f) Plot the threshold voltage as a function of the bulk-source voltage and compare it to the expected value from equation (7.4.9) (webbook 7.4.2) by plotting both on a single graph. What is the substrate doping density which provides the best fit. Is this value consistent with the resistivity of the wafer (ρ = 2 Ωcm)? g) Plot the measured slope as a function of the bulk-source voltage. Is the quadratic model (webbook 7.3.2) adequate to describe the observed variation? Bart Van Zeghbroeck - 1/24/5 - LAB experiments ECEN page 7