1 10/12/2004 4_1 Device Structure and Physical Operation blank.doc 1/2 4.1 Device Structure and Physical Operation Reading Assignment: pp Chapter 4 covers Field Effect Transistors ( ) Specifically, Metal Oxide Semiconductor Field Effect Transistors ( ). : Each of these types can likewise be an n-channel MOSFET ( ), or a p-channel MOSFET ( ). A. NMOS Enhancement Structure Q: A: HO: The Structure of an NMOS Enhancement FET
2 10/12/2004 4_1 Device Structure and Physical Operation blank.doc 2/2 B. The Induced Channel HO: Creating a Channel for Current Flow C. The Modes of a MOSFET Transistor HO: Applying a Drain Voltage to an NMOS Device D. The p-channel Enhancement MOSFET HO: PMOS and CMOS
3 10/12/2004 The Structure of an NMOS Enhancement FET.doc 1/2 The Structure of an NMOS Enhancement FET An NMOS Enhancement FET is a FOUR terminal device! Moreover, each terminal has a specific name: 1. Source (S) 2. Drain (D) 3. Gate (G) 4. Body (B) Each terminal is associated with a metal electrode that is attached to the semiconductor device. * The Body electrode is connected directly to the p-type substrate.
4 10/12/2004 The Structure of an NMOS Enhancement FET.doc 2/2 * Two heavily doped n-type wells are implanted into the p- type substrate. The Source and Drain electrodes are each connected to one of these n + wells. * The region between these n + wells is called the channel. The channel has two important geometries channel width W, and channel length L. * Typical values for channel length L are 0.1 to 3 µm (1 µm is millimeter!), while channel width W is typically 0.2 to 100 µm. * The Gate electrode rests on top of the channel, but is not connected directly to it. Instead, the channel and gate electrode are separated by a thin (e.g., 2-5 nm) layer of Silicon Dioxide (SiO 2 ). * Silicon Dioxide is essentially glass! Glass is a very good insulator thus, no current can flow from the gate into the MOSFET device! * Thus, the Silicon Dioxide layer is sandwiched between the metal Gate electrode and the p-type channel. It is these three materials that give the MOSFET its name Metal (Gate electrode) Oxide (SiO 2 ) Semiconductor (p-type channel) FET.
5 10/12/2004 Creating a Channel for Current Flow.doc 1/5 Creating a Channel for Current Flow When we first look at an NMOS device, it appears that no current can flow from the Drain electrode to the Source electrode (or vice versa) as we must contend with two p-n junctions! * Current seemingly cannot flow into channel from the Drain, as this would require current flowing from an n-type (cathode) region into a p-type (anode) region. * Likewise, current cannot flow into channel from the Source, as this would require current flowing from an n-type (cathode) region into a p-type (anode) region. * Recall that we have previously determined that current cannot flow into (or out of) the channel from (into) the gate, as the SiO2 layer is a very good insulator!
6 10/12/2004 Creating a Channel for Current Flow.doc 2/5 Q: Pardon me, but this NMOS device does not appear to be particularly useful. I mean, what good is a device if no current can flow into it? A: An NMOS device would indeed be useless if no current could flow from drain to source. However, we can modify the channel so that this current can indeed flow! We must induce a channel that is, create a thin layer of n- type Si connecting the source and drain! To do this, we place a positive voltage at the gate electrode. This creates an electric field within the p-type substrate, which pushes the positively charged holes in the p-type substrate away from the gate electrode a depletion region is formed in the Silicon under the gate!
7 10/12/2004 Creating a Channel for Current Flow.doc 3/5 The electric field under the gate electrode will repel positively charged holes, but will attract negatively charged free electrons! Q: I see! The minority carriers in the p-type substrate (i.e., free electrons) are attracted to the gate electrode! A: True! But we also find that many of the free electrons attracted to the gate come from the heavily doped n + wells under the source and drain electrodes. * Of course, there is a Silicon Dioxide insulator separating the gate electrode and the Silicon substrate, so the freeelectrons attracted by the gate electrode simply pile up at the top of the Silicon substrate, just under the SiO 2 layer. * The result is an inversion layer A thin layer in the p- type silicon where the majority carriers are actually free electrons! * This inversion layer forms a n-type conducting channel connecting the n+ Silicon well under the drain to the n+ Silicon well under the source. By applying a positive voltage to the gate, we have induced a conducting channel! In other words, current flowing from drain to source no longer encounters any p-n junctions!
8 10/12/2004 Creating a Channel for Current Flow.doc 4/5 Q: So, will any positive gate voltage suffice for inducing a channel, or must this gate voltage be somehow sufficiently large? A: The later. The gate voltage must be sufficiently large to create an inversion layer it must be sufficiently large to induce a conducting channel. In fact, the voltage value must exceed some threshold. First some definitions: v G = The gate electrode potential with respect to ground. v S = The source electrode potential with respect to ground. v GS = v G -v S = The gate electrode potential with respect to the source. We find that for a channel to be induced with in an NMOS device, the voltage v GS must exceed a threshold voltage: v GS > V t to induce an NMOS channel
9 10/12/2004 Creating a Channel for Current Flow.doc 5/5 Moreover, we find that the amount by which v GS exceeds the threshold voltage is a very important parameter for determining NMOS behavior. We call this value the excess gate voltage this value is very important! v GS V t excess gate voltage Thus, we can say: v GS V > 0 to induce an NMOS channel t
10 10/12/2004 Applying a Drain Voltage to an NMOS Device.doc 1/10 Applying a Drain Voltage to an NMOS Device Say we apply a voltage at the gate of an NMOS device that is sufficiently large to induce a conducting channel (i.e., v V > 0). GS t Now, say that we additionally place a voltage at the NMOS drain electrode, such that: v DS > 0 where: v = v v Drain-to-Source Voltage DS D S Now guess what happens current begins to flow through the induced channel! Q: Current! I thought current could not flow because of the two p-n junctions in the NMOS device! A: Remember, that was before we applied a sufficient gate voltage. With this voltage applied, an n-type channel is induced, forming a conducting channel from drain to source!
11 10/12/2004 Applying a Drain Voltage to an NMOS Device.doc 2/10 Recall that because of the SiO 2 layer, the gate current is zero (i.e., i G = 0 ). Thus, all current entering the drain will exit the source. We therefore conclude that: i = i S D As a result, we refer to the channel current for NMOS devices as simply the drain current i D. Q: So, I see that you have now defined current i D and voltages v GS and v DS. Just how are these parameters related? A: First, we find that an increasing v GS or, more specifically, an increasing excess gate voltage v GS -V t will result in a higher channel conductivity (in other words, a lower channel resistivity). Thus, we find that the drain current i D will increase as a positive excess gate voltage v GS -V t increases (assuming that v DS >0). This process, of increasing the induced channel conductivity by increasing the excess gate voltage, is otherwise known as channel enhancement. This is where the enhancement MOSFET gets its name!
12 10/12/2004 Applying a Drain Voltage to an NMOS Device.doc 3/10 Q: OK, but what about the relationship between drain current i D and voltage v DS? A: This relationship is a little complicated! Generally speaking, however, a positive v DS results in a positive i D, and the larger the v DS, the larger the drain current i D. i D v DS More specifically, we find that when v DS is small (we ll see how small later), the drain current will be directly proportional to the voltage drain to source v DS. i D v if DS v DS small In other words, if v DS is zero, the drain current i D is zero. Or, if the voltage v DS increases by 10%, the drain current will likewise increase by 10%. Note this is just like a resistor! v i = i v R Thus, if (and only if!) v DS is small, the induced channel behaves like a resistor the current through the channel (i D ) is directly proportional to the voltage across it (v DS ).
13 10/12/2004 Applying a Drain Voltage to an NMOS Device.doc 4/10 In other words, we can (for small values of v DS ), define a channel resistance r DS : vds Since id vds, rds ( if v DS small) i D Note that this resistance value depends on the conductivity of the induced channel which in turn is dependent on the excess gate voltage! In other words, the channel behaves like a voltage controlled resistor (provided v DS is small): ( ) small r = f v V if v DS GS t DS Thus, if we were to plot drain current i D versus v DS for various excess gate voltages, we would see something like this:
14 10/12/2004 Applying a Drain Voltage to an NMOS Device.doc 5/10 Q: Yawn! It is apparent that an NMOS transistor is so simple that virtually any intergalactic traveler should be able to understand it. It s just a voltage controlled resistor right? A: WRONG! Remember, channel resistance r DS only has meaning if v DS is small and most often v DS will not be small! As v DS increases from our presumably small value, we find that strange things start to happen in our channel! Recall that primarily, the free-electrons in our inversion layer (the induced channel) were attracted to the gate from the heavily doped n+ Silicon regions under the drain and source.
15 10/12/2004 Applying a Drain Voltage to an NMOS Device.doc 6/10 But the gate now has competition in attracting these free electrons! It was easy to attract free electrons to the gate when the gate electrode voltage was much larger than both the drain and source voltage (i.e., when v GS v DS ). But as the drain voltage increases, it begins to attract free electrons of its own! Recall that positive current entering the drain will actually consist mainly of free electrons exiting the drain! As a result, the concentration of free-electrons in our inversion layer will begin to decrease in the vicinity of the drain. In other words, increasing v DS will result in decreasing channel conductivity!
16 10/12/2004 Applying a Drain Voltage to an NMOS Device.doc 7/10 Thus, increasing the v DS will have two effects on the NMOS device: 1. Increasing v DS will increase the potential difference (voltage) across the conducting channel, an effect that works to increase the drain current i D 2. Increasing v DS will decrease the conductivity of the induced channel, and effect that works to decrease the drain current i D. For small values of v DS, the second effect is tiny, so that the increase in drain current is directly proportional to the increase in voltage v DS (hence, we can define channel resistance r DS ). For example, a 10% increase in v DS will result in a 10% increase in drain current. i D i D directly proportional to small v DS v DS However, as v DS increases, the second effect will become more and more pronounced. We find then that the drain current will no longer be directly proportional to the voltage v DS. The reduction in channel conductivity will begin to counteract the increase in potential across the channel. For example, a 10% increase in v DS may result in only a 9% increase in i D. Likewise, if we increase v DS another 10%, the drain current may then increase only 8% (and so on).
17 10/12/2004 Applying a Drain Voltage to an NMOS Device.doc 8/10 Eventually, we find that the an increase in v DS will result in no further increase drain current i D!! Effect 2 will completely counteract effect 1, so that there is no more increase in drain current as v DS increases. i D i D directly proportional to small v DS increasing v DS reduces channel conductivity v DS When this occurs, we say that we have pinched-off the induced channel in other words the channel is in pinch off. Q: So, if we continue to increase v DS after the channel is pinched off, does the drain current actually begin to decrease? A: NO! A interesting thing happens when the channel is in pinch off. As we further increase v DS, the drain current i D will remain unchanged (approximately)! That is, the drain current will be a constant (approximately) with respect to v DS. i D pinch-off point i D is constant with v DS i D directly proportional to small v DS increasing v DS reduces channel conductivity v DS
18 10/12/2004 Applying a Drain Voltage to an NMOS Device.doc 9/10 Note that there are three distinct channel conditions in for NMOS operation. * Depending on the value of v GS, we can have an induced channel, or no conducting channel at all! * Then if we have an induced channel (i.e., vgs Vt > 0), (depending on the value of v DS ) the channel can be either be pinched-off or not! Each of these three possibilities has a name they are the names of our NMOS transistor modes! 1. Cutoff - When vgs Vt < 0, no channel is induced (no inversion layer is created), and so i D =0. We call this mode CUTOFF. 2. Triode - When an induced channel is present (i.e., vgs Vt > 0), but the value of v DS is not large enough to pinch-off this channel, the NMOS is said to be in TRIODE mode. GS t 3. Saturation - When an induced channel is present (i.e., v V > 0), and the value of v DS is large enough to pinchoff this channel, the NMOS is said to be in SATURATION mode.
19 10/12/2004 Applying a Drain Voltage to an NMOS Device.doc 10/10 We can summarize these modes in a table: MODE INDUCED CHANNEL? CHANNEL PINCH-OFF? CUTOFF NO N/A TRIODE YES NO SATURATION YES YES i D pinch-off point Triode Region Saturation Region v DS
20 10/12/2004 PMOS and CMOS.doc 1/3 PMOS and CMOS In addition to an n-channel MOSFET device (i.e., NMOS), we can build p-channel MOSFET (i.e., PMOS) device. The structure of a PMOS device is essentially the same as an NMOS transistor, except that wherever there was n-type Silicon there is now p-type Silicon and wherever there was p-type Silicon there is now n-type Silicon! Specifically, the PMOS channel is part of a n-type substrate lying between two heavily doped p+ wells beneath the source and drain electrodes. Generally speaking, a PMOS transistor is only constructed in consort with an NMOS transistor. This pair of NMOS and PMOS transistors is known as Complementary MOSFETs CMOS for short!
21 10/12/2004 PMOS and CMOS.doc 2/3 The operation of a PMOS transistor is in many ways similar to that of the NMOS device, but in many ways they are also quite different! For example, for a PMOS device we find: * To create an inversion layer in the n-type substrate, we must attract holes to the gate electrode. * As a result, a p-type channel will be induced, connecting the p+ wells at the drain and the source. * However, to attract holes toward the gate, the voltage v GS must be sufficiently negative! The threshold voltage V t is thus a negative value, so that a channel is induced only if v GS < V t (i.e., v GS is more negative than V I t ). * As a result, a channel is induced in a PMOS device only if the excess gate voltage v GS V t is negative (i.e., v V < 0 ). GS t * Likewise, we find that we typically get current to flow through this channel by making the voltage v DS negative. If we make the voltage v DS sufficiently negative, the p- type induced channel will pinch off. * Note that when v DS is negative, the drain current will flow from the PMOS source, to the PMOS drain (i.e., exactly opposite that of the NMOS device with a positive v DS ).
22 10/12/2004 PMOS and CMOS.doc 3/3 * Thus, for a PMOS device, we define current flowing from source to drain as positive current((i.e., exactly opposite that of the NMOS device). pinch-off point i D Saturation Region Triode Region v DS The PMOS i D vs. v DS Curve
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