PMOS-based Integrated Charge Pumps with Extended Voltage Range in Standard CMOS Technology

Transcription

1 PMOS-based Integrated Charge Pumps with Extended Voltage Range in Standard CMOS Technology by Jingqi Liu A Thesis presented to The University of Guelph In partial fulfillment of requirements for the degree of Master of Applied Science in Engineering Guelph, Ontario, Canada c Jingqi Liu, July 2012

2 Abstract PMOS-based Integrated Charge Pumps with Extended Voltage Range in Standard CMOS Technology Jingqi Liu University of Guelph, 2012 Advisor: Dr. Stefano Gregori This thesis presents the design and implementation of PMOS-based integrated charge pumps with extended voltage range and their regulation circuits in a standard process. The performance of charge pumps are evaluated by their output resistances and power conversion efficiencies. Formulas which describe the charge pump characteristics are developed and presented. Existing charge pumps are analyzed and studied to understand their limitations in generating high voltages and achieving high performance. The proposed charge pump structures are designed to use PMOS switches to alleviate the high voltage stresses across transistors by biasing their bulk independently. The voltages across transistors and capacitors are kept within the suggested voltage rating ( ) regardless of how high the output voltage is, thus the maximum voltage range is extended and no longer limited by the breakdown voltages of the devices. The charge pump circuits only need low-voltage devices and standard processes, and can be easily integrated in a digital or mixed-signal design. The proposed charge pump regulation circuits include a voltage divider, a voltage controlled ring oscillator and a feedback operational amplifier. The regulation circuits are able to adjust the clock frequency to regulate the charge pump to a steady output voltage (set by the reference voltage) under a large range of current loads. A test chip including the proposed charge pumps and regulation circuits was fabricated in a 0.18 µm digital CMOS process provided by Taiwan Semiconductor Manufacturing Company (TSMC). The proposed charge pumps were tested and demonstrated the reliable generation of output voltages up to V using only low-voltage devices. The simulation and measurement results have been presented and compared, demonstrating the functionality and performance of the proposed circuits.

3 Contents Abstract ii List of Figures List of Tables vii xii 1 Introduction Motivations Objectives and methods Contributions Thesis organization Background and Literature Review Dickson charge pump Umezawa bootstrapped single branch charge pump Voltage-doubler charge pump with latched switches Voltage-doubler charge pump with bootstrapped switches Cockcroft-Walton charge pumps Regulation of charge pumps Device breakdown voltage limitations in integrated charge pumps Charge Pump Analysis Charge pump characteristics Method of analysis Characteristics of the Dickson and voltage-doubler charge pumps Characteristics of the Umezawa charge pump Cockcroft-Walton charge pump Optimization of the CW Charge Pump Characteristics of CW charge pump with parasitics Charge pumps for high voltage generations Summary iii

4 Table of Contents iv 4 Proposed Designs Introduction Clocks generation PMOS switches Clock-boosting circuit Proposed single-branch charge pump with bootstrapped PMOS switches Proposed voltage-doubler charge pump with bootstrapped PMOS switches Proposed double-ladder charge pump with bootstrapped PMOS switches Charge pump regulation circuits Summary Simulation Results Introduction Steady state simulations Unregulated 2-stage single branch PMOS charge pump Unregulated 2-stage voltage-doubler PMOS charge pump stage regulated PMOS charge pumps stage and 6-stage double-ladder PMOS charge pumps Transient simulations stage unregulated PMOS charge pumps stage regulated PMOS charge pumps stage and 6-stage double-ladder PMOS charge pumps Conclusion Fabrication and Testing of the Proposed Circuits Tools and design flow Fabrication technology of the proposed circuits Layout MOS switch layout and consideration NMOS capacitor layout and consideration Other considerations Package Test board design Bench test setup Measurement Results Introduction Steady state measurements Unregulated 2-stage single-branch PMOS charge pump Unregulated 2-stage voltage-doubler PMOS charge pump Regulated 2-stage PMOS charge pumps stage and 6-stage double-ladder PMOS charge pumps Transient Measurements

5 Table of Contents v stage unregulated PMOS charge pumps stage regulated PMOS charge pumps stage and 6-stage double-ladder PMOS charge pumps Conclusion Conclusion 89 A Testing 91 A.1 Introduction A.2 Chip layout and pad arrangements A.3 Package bonding diagram A.4 Test board and input/output connections A.5 Pin and signal descriptions A.6 Test setup for CP A.7 Test setup for CP A.8 Test setup for CP A.9 Test setup for CP A.10 Test setup for CP A.11 Test setup for CP B Schematics 102 B.1 Schematic of the V+ Voltage Generation Circuit B.2 Schematic of the phase generator B.3 Schematic of the clock boosting circuit B.4 Schematic of the 2-stage single branch charge pump B.5 Schematic of the 2-stage voltage-doubler charge pump B.6 Schematic of the 4-stage doubler-ladder Charge pump B.7 Schematic of the 6-stage doubler-ladder charge pump B.8 Schematic of the voltage controlled ring oscillator B.9 Schematic of the op-amp and voltage divider C Layout 111 C.1 Layout of the V+ voltage generation circuit C.2 Layout of the phase generator and clock boosting Circuit C.3 Layout of the 2-stage single branch charge pump C.4 Layout of the 2-stage voltage-doubler charge pump C.5 Layout of the 4-stage doubler-ladder charge pump C.6 Layout of the 6-stage doubler-ladder charge pump C.7 Layout of the voltage controlled ring oscillator C.8 Layout of the op-amp and voltage divider C.9 Layout of the regulated 2-stage single branch charge pump C.10 Layout of the regulated 2-stage voltage-doubler charge pump

6 Table of Contents vi D Published Papers 120 D.1 Peer reviewed publications Bibliography 121

7 List of Figures 2.1 Conventional 2-stage Dickson charge pump and its clock scheme Bootstrapped NMOS single branch charge pump Clock scheme used in the bootstrapped NMOS single branch charge pump Bootstrapped PMOS single branch charge pump Voltage-doubler charge pump with latched MOS transistors Voltage-doubler charge pump with bootstrapped MOS transistors stage Cockroft-Walton Charge pump The two phases of operation in a 2-stage CW charge pump The conventional regulation scheme for a Dickson charge pump Voltage-controlled ring oscillator The regulation scheme using a VCO and an op-amp for a Dickson charge pump Types of breakdown in a PMOS transistor Ideal output characteristics and power conversion efficiencies of the 2- stage Dickson and Umezawa charge pumps with parasitics, calculated using above equations Optimized stage capacitors in a 4-stage CW charge pump A capacitor network in series including parasitics, where C eq is the equivalent capacitance of the boxed capacitor network and also the actual parasitic capacitance of C s Efficiency of a 3-stage CW charge pump calculated based on simulation and equation, f = 10 MHz and C T = 300 pf Efficiency of a 4-stage CW charge pump calculated based on simulation and equation, f = 10 MHz and C T = 500 pf Efficiency of a 4-stage CW charge pump calculated based on simulation and equation, f = 10 MHz and C T = 500 pf Efficiency of a 4-stage CW charge pump calculated based on simulation and equation, f = 20 MHz and C T = 320 pf Efficiency of a 4-stage CW charge pump calculated based on simulation and equation, f = 20 MHz, C T = 320 pf, and β = 1.8% vii

8 List of Figures viii 3.9 Normalized output resistance (R O fc T ) as a function of the number of stages (N) for the following circuits: voltage-doubler charge pump with increased t ox (VD thick-ox), voltage-doubler charge pump with series capacitors (VD series-cap), and CW charge pump Block diagram of a charge pump Block diagram of a regulated charge pump Schematic of the non-overlapping phase generation circuit Schematic of the voltage controlled delay element Schematic of the V c generation circuit Simulation of the phase generator with a 10 MHz input clock Drain and source voltages across the PMOS switches in case Drain and source voltages across the PMOS switches in case Drain and source voltages across the PMOS switches in case Proposed clock boosting circuit Simulation of clock boosting circuit Schematic of the proposed single-branch charge pump with bootstrapped PMOS switches The clock signals in the proposed single-branch charge pump Proposed 2-stage voltage-doubler charge pump Proposed 4-stage double-ladder charge pump The block diagram of transconductance amplifier used to adjust the VCO frequency Proposed VCO Frequency and controlling voltage relationship of proposed VCO Hysteresis mode operation of VCO under a pulse train Proposed operational amplifier Simulation and theoretical output voltage characteristics and conversion efficiencies of the unregulated 2-stage single branch PMOS charge pump, with f = 1 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Simulation and theoretical output voltage characteristics and conversion efficiencies of the unregulated 2-stage single branch PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Simulation and theoretical output voltage characteristics and conversion efficiencies of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 1 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Simulation and theoretical output voltage characteristics and conversion efficiencies of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Theoretical output voltage characteristics and conversion efficiencies of a 2-stage charge pump under different frequencies, f = 1, 2, 3, 4, 5, 6 MHz, C T = 500 pf, α = 1.5% and β = 1.2%

9 List of Figures ix 5.6 Simulation output voltage characteristics and conversion efficiencies of the regulated 2-stage single branch charge pump, with V ref = 0.7 V, C T = 500 pf, α = 1.5% and β = 1.2% Simulation output voltage characteristics and conversion efficiencies of the regulated 2-stage voltage-doubler charge pump, with V ref = 0.7 V, C T = 500 pf, α = 1.5% and β = 1.2% Simulation and theoretical output voltage characteristics and conversion efficiencies of the 4-stage double-ladder PMOS charge pump, with f = 1 MHz, C T = 450 pf, α = 1.5% and β = 1.2% Simulation and theoretical output voltage characteristics and conversion efficiencies of the 4-stage double-ladder PMOS charge pump, with f = 10 MHz, C T = 450 pf, α = 1.5% and β = 1.2% Simulation and theoretical output voltage characteristics and conversion efficiencies of the 6-stage double-ladder PMOS charge pump, with, f = 1 MHz, C T = 630 pf, α = 1.5% and β = 1.2% Simulation and theoretical output voltage characteristics and conversion efficiencies of the 6-stage double-ladder PMOS charge pump, with, f = 10 MHz, C T = 630 pf, α = 1.5% and β = 1.2% Start-up transient of the unregulated 2-stage single branch PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Start-up transient of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Start-up transient of the regulated 2-stage single branch PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2% Start-up transient of the regulated 2-stage voltage-doubler PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2% Output voltage, internal clock and VCO control voltage of the regulated 2-stage single branch PMOS charge pump under a load current change, with C T = 500 pf, α = 1.5% and β = 1.2% Output voltage, internal clock and VCO control voltage of the regulated 2-stage voltage-doubler PMOS charge pump under a load current change, with C T = 500 pf, α = 1.5% and β = 1.2% Start-up transient of the 4-stage double-ladder PMOS charge pump, with f = 10 MHz, C T = 630 pf, α = 1.5% and β = 1.2% Start-up transient of the 6-stage double-ladder PMOS charge pump, with f = 10 MHz, C T = 450 pf, α = 1.5% and β = 1.2% Analog IC design flow used in this project Layout of a PMOS transistor Layout of the bootstrapped switch in the single-branch PMOS charge pump Layout of the bootstrapped switch in the voltage-doubler and CW charge pumps Vertical structure of the NMOS capacitor Layout of a NMOS capacitor

10 List of Figures x 6.7 Chip floorplan Technical drawing of the 24-pin CFP package, Spectrum Semiconductor Materials, Inc Layout of the PCB The fabricated PCB board with test chip and auxiliary circuits Block diagram of the characterization setup Measurement and simulation output voltage characteristics and conversion efficiencies of the unregulated 2-stage single-branch PMOS charge pump, with f = 1 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Measurement and simulation output voltage characteristics and conversion efficiencies of the unregulated 2-stage single-branch PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Measurement and simulation output voltage characteristics and conversion efficiencies of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 1 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Measurement and simulation output voltage characteristics and conversion efficiencies of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Measurement and simulation output voltage characteristics and conversion efficiencies of the regulated 2-stage single-branch PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2% Measurement and simulation output voltage characteristics and conversion efficiencies of the regulated 2-stage voltage-doubler PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2% Measurement and simulation output voltage characteristics and conversion efficiencies of the 4-stage double-ladder PMOS charge pump, with, f = 1 MHz, C T = 450 pf, α = 1.5% and β = 1.2% Measurement and simulation output voltage characteristics and conversion efficiencies of the 4-stage double-ladder PMOS charge pump, with, f = 10 MHz, C T = 450 pf, α = 1.5% and β = 1.2% Measurement and simulation output voltage characteristics and conversion efficiencies of the 6-stage double-ladder PMOS charge pump, with, f = 1 MHz, C T = 630 pf, α = 1.5% and β = 1.2% Measurement and simulation output voltage characteristics and conversion efficiencies of the 6-stage double-ladder PMOS charge pump, with, f = 10 MHz, C T = 630 pf, α = 1.5% and β = 1.2% Start-up transient of the unregulated 2-stage single-branch PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Start-up transients of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Start-up transient of the regulated 2-stage single-branch PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2%

11 List of Figures xi 7.14 Start-up transient of the regulated 2-stage voltage-doubler PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2% Start-up transient of the 4-stage double-ladder PMOS charge pump, with f = 10 MHz, C T = 630 pf, α = 1.5% and β = 1.2% Start-up transient of the 6-stage double-ladder PMOS charge pump, with f = 10 MHz, C T = 450 pf, α = 1.5% and β = 1.2% Start-up transient of the 6-stage double-ladder PMOS charge pump, with = 2.4 V, f = 10 MHz, C T = 450 pf, α = 1.5% and β = 1.2% A.1 Chip layout and pad arrangements A.2 Package bonding diagram A.3 PCB connections B.1 Schematic of the V+ voltage generation circuit to adjust non-overlapping time of the phase generator B.2 Schematic of the phase generator B.3 Schematic of the clock boosting circuit B.4 Schematic of the 2-stage single branch charge pump B.5 Schematic of the 2-stage voltage-doubler charge pump B.6 Schematic of the 4-stage double-ladder charge pump B.7 Schematic of the 6-stage double-ladder charge pump B.8 Schematic of the voltage controlled ring oscillator B.9 Schematic of the op-amp and voltage divider C.1 Layout of the V+ voltage generation circuit to adjust non-overlapping time of the phase generator C.2 Layout of the phase generator and clock boosting circuit C.3 Layout of the 2-stage single branch charge pump C.4 Layout of the 2-stage voltage-doubler charge pump C.5 Layout of the 4-stage double-ladder charge pump C.6 Layout of the 6-stage double-ladder charge pump C.7 Layout of the voltage-controlled ring oscillator C.8 Layout of the op-amp and voltage divider C.9 Layout of the regulated 2-stage single branch charge pump C.10 Layout of the regulated 2-stage voltage-doubler charge pump

12 List of Tables 2.1 Operation of the bootstrapped PMOS charge pump CW charge pump output resistance with parasitics Output resistances based on equation 3.18 and simulations Operation of the proposed PMOS charge pump Design specifications of the proposed circuits Key performance parameters of the unregulated 2-stage single branch PMOS charge pump Key performance parameters of the unregulated 2-stage voltage-doubler PMOS charge pump Key performance parameters of the unregulated double-ladder PMOS charge pump Key performance parameters of the unregulated 2-stage single-branch PMOS charge pump from measurement Key performance parameters of the unregulated 2-stage voltage-doubler pmos charge pump from measurement Key performance parameters of the unregulated double-ladder PMOS charge pump from measurement A.1 Pin descriptions A.2 Pin assignments for static test of CP A.3 Pin assignments for transient test of CP A.4 Pin connections for static test of CP A.5 Pin connections for transient test of CP A.6 Pin connections for static test of CP A.7 Pin connections for transient test of CP A.8 Pin connections for static test of CP A.9 Pin connections for static test of CP A.10 Pin connections for static test of CP A.11 Pin connections for static test of CP A.12 Pin connections for static test of CP A.13 Pin connections for transient test of CP xii

13 Chapter 1 Introduction 1.1 Motivations Charge pumps are used as voltage converters to generate higher or lower DC voltages from a DC power supply. They utilize capacitors to transfer electric charge from one stage to the next, pumping the output voltage to a higher or lower potential. The charge transfer between capacitors is controlled by switches or diodes. The first charge pumps were built with bulky discrete components to realize very high voltages (kv) for particle accelerations. Modern integrated charge pumps with on-chip capacitors and transistors are commonly implemented to perform voltage conversions in many of today s electronic devices. As the channel length and gate oxide thickness of transistors continue to be scaled down, integrated circuits can only be accompanied by low voltage power supplies (e.g. 1.2 V or 1.8 V). However, a number of circuit implementations such as Flash memories, DRAMs and drivers of speakers and displays [1] require higher voltages to function correctly. Integrated charge pumps are very much suitable to generate high voltages on chip, since the capacitors and transistor switches can be easily realized and integrated in widely used planar technology. They can be integrated on the same chip with the rest of digital and analog circuits to achieve less area and lower cost. In comparison, other DC-DC converters, such as buck and boost converters, require more area and cost because they utilize inductors which are not easiliy integratable in CMOS technology. 1

14 Chapter 1. Introduction 2 As the dimension and oxide thickness of semiconductor devices keep shrinking, the breakdown voltages of these transistors and capacitors become lower and lower. This limits the maximum output voltage a charge pump can reliably generate. The voltage range can be extended by using high-voltage devices and triple-well technology, but it is costly and may be unavailable to designers. Thus, it is beneficial to find a way to alleviate the voltage stress across the transistor switches and the capacitors, so the charge pumps can be used to generate high voltages in a standard process. In an unregulated charge pump, the output voltage changes under different load currents, however many applications require a steady voltage under a wide range of load currents. Thus, a charge pump regulator needs to be designed to achieve such a requirement. Finally, the output resistance and power conversion efficiency of the charge pumps should be optimized as much as possible. A low output resistance is desired since the it will improve the charge pump driving ability as a voltage source. The power conversion efficiency needs to be maximized to reduce power loss. As a result, high power conversion efficiency increases the battery life and reduces the cost of packages for dissipating excessive heat. 1.2 Objectives and methods The first objective of the research is to explore techniques which can be used to extend the output voltage range of a charge pump using only low-voltage devices. The performances of the charge pump should be optimized as well. The second objective is to develop a regulation scheme which can keep the charge pump output at a steady voltage level under a wide range of load currents. The regulation circuit should be stable and have a fast transient response. Finally, the circuits should be fabricated and characterized to evaluate their functionality and performance. We need to apply proper methods and tools to successfully design and implement the proposed circuits. First, theoretical models are established in Matlab and used as design guidelines. Cadence Composer and Spectre circuit simulator are used for schematic designs and simulations. After optimizing the schematic design and meeting the specification, the chip layout was drafted using Cadence Virtuoso. Mentor s Calibre is used with the layout editor for physical verification purposes. Finally, a printed circuit board (PCB) is designed for characterizing the chip with other test equipment.

15 Chapter 1. Introduction Contributions The objective of the research is to design charge pumps which can generate extended voltage range without using high voltage devices. The designs utilize only PMOS switches to eliminate the body effect and junction breakdown risks that NMOS transistors face. The proposed charge pump structure keeps the voltage stresses across the transistors and capacitors within the recommended voltage rating of the technology ( ), thus standard low-voltage devices can be used to generate a high output voltage. The newly designed single branch and voltage-doubler charge pumps with proposed bootstrapping circuits and clock boosting circuit have improved performances and output voltage range against to the conventional designs. The proposed double-ladder charge pump is a complete solution to generate high DC voltage in a standard digital process. A regulation scheme suitable for charge pumps is also proposed. The design of regulation circuits consists of a voltage controlled oscillator (VCO) and an operational amplifier (op-amp), which can adjust the clock frequency to regulate the charge pump output voltage. The charge pump under regulation has a fast recovery response under a sudden load current change. A test chip with the proposed charge pumps and regulation circuits is implemented in TSMC 0.18µm technology and tested. 1.4 Thesis organization The thesis is organized in such a way to present the analyses, designs, implementations, tests and results of the proposed circuits in a logical order. Chapter 2 presents the background and literature review that are related to the proposed charge pumps. Chapter 3 shows the analysis methods to evaluate and optimize the performance of charge pumps. Chapter 4 examines the design limitations and provides the detailed designs of proposed circuits. Chapter 5 presents the implementations of the circuits in TSMC 0.18µm CMOS technology and the test setup to measure the fabricated test chip. Chapter 6 shows the simulation and experimental results. The thesis concludes in Chapter 7.

16 Chapter 2 Background and Literature Review 2.1 Dickson charge pump The first commonly used monolithic charge pump is the Dickson charge pump [2]. The structure uses a single chain of capacitors and two non-overlapping clock signals to generate an output voltage at the load capacitor. The Non-overlapping clocks are used to reduce the crowbar current in CMOS drivers with two non-overlapping time slots in each clock period. The switching between the capacitors is controlled by diodes, which are turned on when the anode voltage is higher. In an integrated implementation, the diodes can be realized with MOS transistors. A 2-stage conventional Dickson charge pump and its clock scheme are shown in Fig The output voltage in an N-stage conventional Dickson charge pump with no load current can be expressed below. V OUT = (1 + N)( V t ). (2.1) V t is the threshold voltage of the diode-connected NMOS transistors and can be as large as 0.5 V to 0.7 V, introducing a substantial voltage drop per stage. As the voltage supply is reduced to 1.8 V and lower, a large number of stages need to be implemented to reach the desired high voltage. Moreover, the NMOS devices suffer from body effect especially in the stages next to the output. The threshold voltage of the transistors with body effect can be expressed below. 4

17 Chapter 2. Background and Literature Review 5 Vout C s C s Φ1 Φ2 Φ2 Φ1 (a) Conventional Dickson charge pump with diodes. Vout C s C s Φ1 Φ2 Φ2 Φ1 (b) Conventional Dickson charge pump with diode connected NMOS transistors. Φ1 Φ2 Φ1 Φ2 (c) Conventional non-overlapping clocks and their complementary signals. Figure 2.1: Conventional 2-stage Dickson charge pump and its clock scheme. ( V t = V t0 + γ 2φf V BS ) 2φ f (2.2) where V BS is the bulk-to-source voltage, V t0 is the threshold voltage for V BS = 0, γ is a fabrication parameter, and φ f is a physical parameter with 2φ f typically 0.6 V [3]. Since the bulk of the NMOS in a standard process is grounded, the V BS becomes more negative

18 Chapter 2. Background and Literature Review 6 in the stages where high voltage are present, causing the threshold voltage to increase. This further decreases the output voltage that can be achieved in a charge pump with N stages. Furthermore, the NMOS transistors face breakdown risks because of the high V BS. 2.2 Umezawa bootstrapped single branch charge pump To eliminate the threshold voltage drops in Dickson charge pumps, bootstrapped MOS transistor switches are introduced [4], shown in Fig The charge pump utilizes four non-overlapping clocks, which are shown in Fig The NMOS transistor switches are turned on in triode region to achieve very low on resistance to achieve minimum resistive loss. To effectively turn on the transistors, bootstrapping transistors and capacitors are needed to boost the voltages at the gate terminals of the main switches. The charge pump also uses four non-overlapping clock phases to prevent short circuit current for better performances. However, in a standard process, the NMOS transistors suffer from body effect, which increases the on resistance of the transistors as their threshold voltage rises. Moreover, the last stage of the configuration still uses a diode-connected NMOS transistor, thus introduces one threshold voltage drop. Φ3 Φ4 C b C b Vout C s C s C load Φ1 Φ2 Φ2 Φ1 Figure 2.2: Bootstrapped NMOS single branch charge pump. The body effect can be avoided by using only PMOS transistors in a standard process [5], since their body terminals can be biased independently instead of connecting to a fixed potential. The 2-stage bootstrapped PMOS single branch charge pump is shown in Fig.

19 Chapter 2. Background and Literature Review 7 Φ1 Φ2 Φ3 Φ4 t0 t1 t2 t3 t4 t5 t6 t7 t8 Figure 2.3: Clock scheme used in the bootstrapped NMOS single branch charge pump. Φ3 C b Φ2 Φ4 C b G1 G2 H1 H2 Vout S1 S2 S3 C s C s C load Φ1 Φ2 Φ2 Φ1 Figure 2.4: Bootstrapped PMOS single branch charge pump. 2.4 and uses the same clock scheme shown in 2.3. The operation of the charge pump is shown in Table 2.1 [6],. Table 2.1: Operation of the bootstrapped PMOS charge pump Time S1 S2 S3 G1 G2 G3 H1 H2 V out t0 off on off V t t1 off off off V t t2 off off off V t t3 off off off V t t4 on off on V t t5 off off off V t t6 off off off V t t7 off off off V t t8 off on off V t

20 Chapter 2. Background and Literature Review 8 By observing the clock phases and the voltages at different nodes, it is obvious to see that the bootstrapping capacitors driven by φ 3 and φ 4 are being charged and discharged in every clock cycle, contributing to the top plate parasitics of the transfer capacitors. The additional parasitic capacitances will degrade the charge pumps performances. Also, during φ 1 and φ 2, the main PMOS transistors will experience maximum voltages of 2, so high-voltage devices are needed. To ensure the operation of the charge pump, the four non-overlapping clocks create six time slots, two of which are allocated to prevent short-circuit current (t2 to t3 and t5 to t6) and the other four time slots are used to boost the voltages of the bootstrapping circuit. The additional time slots reduce the effective on time of the switches. As the clock frequency increases, the on time will eventually disappear, causing the charge pump to shut down. Thus, the maximum operating frequency of the Umezawa bootstrapped single branch charge pump is reduced compared to the conventional Dickson charge pump which uses only two non-overlapping clocks. 2.3 Voltage-doubler charge pump with latched switches Φ1 Φ2 Φ1 Φ2 C s C s Vout C s C s Φ2 Φ1 Φ2 Φ1 Figure 2.5: Voltage-doubler charge pump with latched MOS transistors.

21 Chapter 2. Background and Literature Review 9 The voltage-doubler charge pump in Fig. 2.5 consists of two branches of capacitors which alternately transfer the charges towards the load capacitor at the output. It uses the conventional clock scheme shown in Fig. 2.1c. This voltage doubler uses a pair of latched CMOS transistors and the complementary voltage swings of the internal nodes in each stage to control the switches of opposite branches [7]. The voltage doubler has several positive characteristics. First, the output voltage ripple is reduced, since there are two branches charge the output alternately. Second, the voltages across any transistor switch never exceeds, thus there is no need to use high-voltage transistors. Moreover, the threshold voltage loss at the last stage is eliminated. The circuit also has some drawbacks. The NMOS transistors still experience body effects and are subject to breakdown if very high output voltage is generated. Furthermore, the transistor overdrive voltages decrease with high load current, causing the on resistance of switches to rise. The higher on resistance results in more resistive power losses, reduces power efficiency and driving capability [8]. Moreover, a short-circuit current from higher voltage nodes to lower voltage nodes exists when the complementary voltage transitions of internal nodes occur simultaneously during switching. The short-circuit current causes charge loss and reduces the charge pump efficiency and voltage gain. 2.4 Voltage-doubler charge pump with bootstrapped switches To eliminate the short-circuit current and improve the output driving ability, a voltage doubler using bootstrapped CMOS switches is proposed [8]. The charge pump is shown in Fig. 2.6 and utilizes the conventional clock scheme shown in Fig. 2.1c. This voltage doubler is able to maintain necessary overdrive voltages with high load current for the switches to be fully turned on to minimize the on resistances. The reduction of the short-circuit current improves the start-up transient and the charge pump performance.

22 Chapter 2. Background and Literature Review 10 Φ1 Φ2 Φ1 Φ2 C s C s Φ1 Φ2 Φ1 Φ2 Vout Φ2 Φ1 Φ2 Φ1 C s C s Φ2 Φ1 Φ2 Φ1 Figure 2.6: Voltage-doubler charge pump with bootstrapped MOS transistors. 2.5 Cockcroft-Walton charge pumps The Cockcroft-Walton (CW) voltage multiplier is another charge pump that converts DC electrical power from a low voltage level to a higher level [9]. It is made of a ladder network of capacitors and switches to generate high voltages, shown in Fig C 1 C V out C Load 2 C 1 ' C 2 ' Figure 2.7: 2-stage Cockroft-Walton Charge pump.

23 Chapter 2. Background and Literature Review 11 The CW charge pump transfers charge back and forth between the two capacitor branches and uses the conventional non-overlapping clock scheme in Fig. 2.1c, the two phases of charge pump operation are shown in Fig The biggest advantage of this configuration is to allow the voltages across the transistors and stage capacitors not exceed one [10]. Thus, it is able to use low-voltage devices to generate very high output voltage. This is beneficial for implementing charge pumps in an integrated technology, since high voltage devices usually take large areas and need special processes. C 1 C 2 C 1 C 2 V out V out C Load C 1 ' C 2 ' C Load C 1 ' C 2 ' (a) Phase 1 in a 2-stage CW charge pump (b) Phase 2 in a 2-stage CW charge pump Figure 2.8: The two phases of operation in a 2-stage CW charge pump. 2.6 Regulation of charge pumps In a charge pump, the output voltage has a linear dependence with respect to the load current, exhibiting an equivalent output resistance. In most applications, the output voltage should be kept constant under different load current. To achieve this, the regulated charge pump was proposed [11] and the schematic of the conventional regulation scheme is shown in Fig The regulation circuit uses a comparator to compare a fraction of the output voltage against a reference voltage. It employs a clock-blocking scheme to disable to input clock when the output voltage is higher than the desired voltage. By using this regulation scheme, a constant output voltage level can be achieved under different load currents. However, the circuit has to use an external clock and has a large ripple with high load currents [12]. An internal clock can be generated by using a voltage-controlled oscillator (VCO) instead of using an external clock. A common choice to implement a VCO is to use a current starved voltage-controlled oscillator (CSVCO) [13] shown in Fig The CSVCO is

24 Chapter 2. Background and Literature Review 12 Vout Iout C s C s C load V ref Figure 2.9: The conventional regulation scheme for a Dickson charge pump. V p V p V p V p V p V p Clock V n V bias V n V n V n V n V n Figure 2.10: Voltage-controlled ring oscillator. able to generate a clock signal with variable frequencies by adjusting the bias voltage. The frequency exhibits a linear relationship with respect to the bias voltage [14]. An operational amplifier is used instead of a comparator to generate the bias voltage. After the output voltage is detected, a bias voltage generation block compares a fraction of the output voltage with the reference voltage and adjusts the bias voltage for the CSVCO to produce the desired clock frequency. The regulation scheme with a conventional Dickson charge pump is shown in Fig This circuit can achieve a well regulated voltage in steady state, however the output voltage will exhibit a long settling time and slow response if there is a sudden load current change, because the bias op-amp needs time to generate a new steady bias voltage for the VCO.

25 Chapter 2. Background and Literature Review 13 Vout Iout C s C s C load VCO Differential Amplifier V ref Figure 2.11: The regulation scheme using a VCO and an op-amp for a Dickson charge pump. 2.7 Device breakdown voltage limitations in integrated charge pumps The maximum voltage a charge pump can generate is limited by the devices breakdown voltages, since the transistors and capacitors have to sustain high voltages especially at later stages of the charge pump. Figure 2.12: Types of breakdown in a PMOS transistor. The basic types of breakdown in a MOS transistor structure are shown in Fig [3]. Punch-through occurs in devices with relatively short channel when the source-drain

26 Chapter 2. Background and Literature Review 14 voltage increases to the point that the depletion region surrounding the drain extends to the source. Gate oxide breakdown happens at an electric field across the gate of about V/m to V/m. The source-gate breakdown voltage is independent of the channel length and can be increased only with a thicker oxide. Junction breakdown between n-doped and p-doped regions, such as between n-well and p + diffusions and between n-well and p-substrate, can be caused by Zener effect (in heavily doped junctions) and avalanche breakdown (in lightly doped junctions). Punch-through, oxide breakdown, and well-diffusion junction breakdown (Zener) happen at lower voltages than the well-substrate junction breakdown (avalanche). Therefore, the main voltage limitations in MOS devices concern the maximum source-gate voltage (due to oxide breakdown, typically being the dominant limitation), the maximum source-drain voltage (due to punchthrough), and the maximum well-drain and well-source voltages (due to junction breakdown). The maximum well-substrate voltage is a less stringent limitation because of the lighter doping levels. We must keep the source-gate, source-drain, welldrain and well-source voltages of the transistors within the breakdown limitations for the charge pump to operate properly. In the fabrication technology to implement the test chip, the oxide and the well-diffusion junction breakdown voltages are about 5-6 V. If conventional charge pump designs are used, the maximum output voltages will be limited at 5-6 V, since higher voltages will damage the devices and stop the charge pump from working.

27 Chapter 3 Charge Pump Analysis 3.1 Charge pump characteristics Charge pump characteristics can be evaluated by the output resistance and power conversion efficiency. The output resistance determines the voltage drop due to the load current. The power conversion efficiency determines how power efficient the charge pump is at different load currents. Both of the parameters have to be optimized for charge pumps to achieve high performances. The open circuit output voltage of a charge pump can be expressed as V O = A, (3.1) where A is the gain of the charge pump and is defined as the ratio between the maximum open circuit output voltage and the input voltage. In an N-stage charge pump, the gain is A = N + 1. (3.2) The output voltage of a charge pump has a dependence on the load current, exhibiting an equivalent output resistance R O. The output voltage with the presence of R O and load current I O can be expressed as 15

28 Chapter 3. Charge Pump Analysis 16 V O = A R O I O. (3.3) The charge pump efficiency η is defined as the ratio between the output power and input power, where V O and I O are the output voltage and current in steady state, V I and I I are the input voltage and current in steady state, η = V OI O V I I I (3.4) In order to design charge pumps with optimized output resistance and power conversion efficiency to meet the specification, theoretical analysis need to be conducted to determine design parameters such as the transfer capacitance and switching frequency. The method of analysis is described in the next section. 3.2 Method of analysis The theoretical analyses on charge pumps can be done using the method proposed in [15]. The method can be used to analyze circuits containing switches, capacitors, and voltage sources. The operation of the charge pump can be described effectively by means of switching matrices, a capacitance matrix, and a voltage source matrix. The switching matrix describes the arrangement of the switches in one phase of operation, a different switching matrix is obtained in a different phase. The capacitance matrix describes the capacitances associated with different nodes, and the voltage source matrix presents any constant voltage source at different nodes. The capacitance matrix and voltage source matrix do not change in different phases of operation. In this method, the switches are considered to be ideal and slow switching conditions are assumed, where the switching period is much longer than time constants due to any capacitances and resistances. The circuit is analyzed in steady-state conditions, where the capacitor voltages are periodic steadystate waveforms. In each phase, the matrices can construct a set of KVL equations and charge conservation equations which can be used to solve for the nodal voltages and charge transferred in this phase of operation. Thus, the output resistance, gain and power conversion efficiencies can be derived based on this method.

29 Chapter 3. Charge Pump Analysis 17 The characteristics of charge pumps are greatly affected by parasitic capacitances associated with the transfer capacitors. The parasitics can be expressed by the technological parameters α and β, which give the stray parasitic capacitances α C (between bottom plate and substrate) and β C (between top plate and substrate) of an integrated capacitor C. The value of α and β are determined by process, type, and layout of the integrated capacitors used. To assess the impact of parasitic capacitances on the charge pump characteristics, their values are included in the capacitance matrix by modelling the additional capacitance connected to a node as α C or β C when applying the method above. 3.3 Characteristics of the Dickson and voltage-doubler charge pumps Dickson and voltage-doubler charge pumps have been analyzed using the method described above with parasitic capacitances taken into account [16]. The characteristics of an N-stage Dickson or voltage-doubler charge pump are presented below. The gain of the charge pump is The output resistance is A = R O = N 1 + β + 1. (3.5) N 2 fc T (1 + β), (3.6) where f is the switching frequency and C T is the total transfer capacitance defined as the sum of all stage capacitors C T = N C i. (3.7) i=1 The power conversion efficiency is η = P O P O + P LD + P LI = A I O R O I 2 O A I O + G I V 2 DD, (3.8)

30 Chapter 3. Charge Pump Analysis 18 G I = fc T α + β + αβ 1 + β. (3.9) The above equations can be used to calculate the output voltage characteristics and power conversion efficiencies of Dickson and voltage-doubler charge pumps for given switching frequency, total transfer capacitance, and parasitic capacitances. 3.4 Characteristics of the Umezawa charge pump In the Umezawa bootstrapped charge pump [4], the bootstrapping capacitances contribute additional top plate parasitics, because they are charged and discharged in every clock cycle. The total equivalent top plate parasitic β t is increased to β t = β + C b C s. (3.10) The increase in top plate parasitic will affect the output resistance and power efficiency of the charge pump. By substituting β t into the above equations, we can calculate and compare the characteristics against the Dickson and voltage-doubler charge pumps with ideal switches. The results are shown in Fig. 3.1 with α = 1.5%, β = 1.2%, C b = 1.6 pf, C s = 100 pf and f = 1 MHz. The Umezawa charge pump shows a similar output resistance to the Dickson and voltagedoubler charge pumps. However, the increased β causes the efficiency to drop by 2% to 10% in the load current range of interest due to the additional parastics contributed by the bootstrapping capacitors.

31 Chapter 3. Charge Pump Analysis 19 Figure 3.1: Ideal output characteristics and power conversion efficiencies of the 2-stage Dickson and Umezawa charge pumps with parasitics, calculated using above equations. 3.5 Cockcroft-Walton charge pump The equations presented above are applicable to Dickson and voltage-doubler charge pumps, which have optimal output resistances with equally sized stage capacitors. For a Cockcroft-Walton (CW) charge pump in a double-ladder configuration [17], it is not the case since the stage capacitors are not driven independently. The stage capacitors in the CW charge pump have to be scaled accordingly to optimize the output resistance.

32 Chapter 3. Charge Pump Analysis Optimization of the CW Charge Pump In a two-phase charge pump, the output resistance is given by [18] R O = 1 f s N i=1 (a ci ) 2 C i. (3.11) where a ci = q i /q X is the charge multiplier factor, which is the ratio of the charge q i, transferred by capacitor C i, and the charge q X delivered to the load. The charge multiplier factors can be calculated by applying the method in section 3.2 in steady state, where each capacitor receives and delivers the same charge in each of the two phases. Since a ci is determined only by the charge pump topology, we can calculate a ci using equal sized stage capacitors. The charge multiplier factor of the CW charge pump can be expressed as a ci = N + 1 i, (3.12) By combining (3.11) and (3.12), the output resistance of the CW charge pump can be expressed as R O = 1 f s N i=1 (N + 1 i) 2 C i. (3.13) To minimize R O for a constant total capacitance C T, we combine (3.13) and the constraint C T = 2 n i=1 C i, and set the partials with respect to C i equal to zero. We can obtain the optimized stage capacitors and the corresponding optimized output resistance is C i = N + 1 i N (N + 1) C T, (3.14) R O = N 2 (N + 1) 2 4 f C T, (3.15)

33 Chapter 3. Charge Pump Analysis 21 where C 1 indicates the two capacitors of the first stage (i.e. next to the input) and C N indicates the two capacitors of the last stage (i.e. next to the output). The stage capacitors in an optimized 4-stage CW charge pump are shown in Fig Input C 1 C 2 C 3 C 4 Output C 1 C 2 C 3 C 4 Figure 3.2: Optimized stage capacitors in a 4-stage CW charge pump Characteristics of CW charge pump with parasitics To obtain a more realistic model of the CW charge pump characteristics, we should include the parasitic capacitances of optimized stage capacitors into the analyses. To do this, the method in section 3.2 can be used by constructing the capacitance matrices with the addition of α C i and β C i at different nodes. Table 3.1 shows the output resistances for CW charge pumps with different number of stages. Table 3.1: CW charge pump output resistance with parasitics. N R o 1 1 fc T (1+β), 1 3(6+α+αβ) 2 fc T 2+α+5α+αβ+2β 2 1 6(36+2α α(9+5β)+β(42+11β)) fc T 6+2α 2 +β(27+β(25+6β))+α(9+β(18+7β)) As the number of stages increases, the complexity of the matrices increases and the expression of output resistance become impractical for hand calculations. It is only viable to use the matrices to calculate the output resistance expression with a large number of stages with a computer program.. A closed-form expression is desired to quickly estimate the output resistance. To derive such equations, we consider equation (3.11), where the overall output resistance can be expressed as the sum of output resistances of individual stages. We can take parastic capacitances into account based on equation (3.6) and come up with the expression below.

34 Chapter 3. Charge Pump Analysis 22 R O = N(N + 1) 2fC T N i=1 N + 1 i (1 + β N+1 i ) (3.16) where β i is the equivalent β of each stage. In the CW charge pump, the transfer capacitors in either ladder are connected in series, so the total top plate parasitic capacitance at the stage i equals the equivalent capacitance of the rest of the capacitor network looking from the top plate of stage i towards the output, as shown in Fig C s1 C eq C s2 C s3 C s4 C α1 C β1 C α2 C β2 C α3 C β3 C α4 C β4 Figure 3.3: A capacitor network in series including parasitics, where C eq is the equivalent capacitance of the boxed capacitor network and also the actual parasitic capacitance of C s1. by considering α and β to be sufficiently small, the equivalent parasitic capacitance at top plate of stage i can be expressed as β i = β (N + 1 i)(n + 2 i) 2 + α (N + 1 i)(n i), (3.17) 2 However, the actual equivalent parasitics in CW charge pumps are more complex, since the two branches of capacitors are connected to each other in different configurations in both phases of operation as shown in Fig The expression of equivalent top parasitics is modified and the output resistance of an N-stage CW charge pump is then derived empirically by comparing with simulation results. R O = N(N + 1) 2fC T N i=1 N + 1 i ( ) (N+1 i) (3.18) β 1 + i (N+1 i)k 1 The results calculated using the above equation are compared with several charge pump simulations to verify the accuracy of the formula, where β = 1%, α = 1.5%, and k 1 = 1.5.

35 Chapter 3. Charge Pump Analysis 23 Table 3.2: Output resistances based on equation 3.18 and simulations N f C T Simulation R out Equation R out % error 2 10 MHz 300 pf 2924 Ω Ω 0.36% 3 10 MHz 300 pf Ω Ω 0.2% 4 10 MHz 500 pf Ω Ω 0.06% 5 10 MHz 750 pf Ω Ω -0.17% 6 10 MHz 1050 pf Ω Ω -0.51% The results are very close to the simulations and can be used to quickly estimate the output resistance and choose design parameters. We can use similar strategies to derive the input conductance empirically, by expressing G I as the sum of the input conductances of individual stages. The input conductance can be expressed as G I = 2fC T N(N + 1) N (N + 1 i) α + k 2 (1 + i=1 β ) (N+1 i) β i (N+1 i)k 2 (3.19) in a similar manner, the open circuit voltage of CW charge pump can be expressed as V O = N i=1 1 + V i 1 β i, V 0 = (3.20) (N+1 i)k 3 and the gain is A = V O. (3.21) To verify the accuracies of the above empirical expressions, we can calculate the efficiencies of the charge pumps, which include all three parameters (R o,g I, A) into consideration. The results are then compared with the simulations in Fig. 3.4 and Fig In both calculations and simulations, we use α = 1.5%, β = 1%, k 1 = k 2 = 1.5, and k 3 = 1. Based on the Fig. 3.4 and Fig. 3.5, we can conclude that the equations can produce close approximations of charge pump characteristics instead of solving the time consuming KVL and charge transfer matrices. The empirical equations show some deviations from

36 Chapter 3. Charge Pump Analysis 24 Figure 3.4: Efficiency of a 3-stage CW charge pump calculated based on simulation and equation, f = 10 MHz and C T = 300 pf. Figure 3.5: Efficiency of a 4-stage CW charge pump calculated based on simulation and equation, f = 10 MHz and C T = 500 pf. the simulation, however the inaccuracies are small. The equations can also be calibrated by adjusting the parameters k 1, k 2, and k 3. The calibration requires fitting the equations to two operation points in simulation to get the exact output resistance, gain and input

37 Chapter 3. Charge Pump Analysis 25 inductance. Then the equations can be used calculate the charge pumps characteristics with different switching frequencies and transfer capacitances without running more simulations. k 1, k 2 and k 3 are adjusted by fitting the equation to the simulation results with load current of 0 A and 20 µa. The parameters are k 1 = 1.466, k 2 = and k 3 = The efficiencies from the equations and simulations at different load currents are shown in Fig. 3.6 with f = 10 MHz and C T = 500 pf. Figure 3.6: Efficiency of a 4-stage CW charge pump calculated based on simulation and equation, f = 10 MHz and C T = 500 pf. With k 1, k 2 and k 3 unchanged, the charge pump is simulated with f = 20 MHz and C T = 320 pf, and the efficiency comparison is shown in Fig With f, C T, k 1, k 2 and k 3 unchanged, the top plate parasitic β is changed to 1.8%, and the efficiency comparison is shown in Fig For a different number of stages, the values of k 1, k 2 and k 3 can be adjusted for more precise results. Once k 1, k 2 and k 3 are determined, the equations can give close results to simulations for different f, C T, α and β.

38 Chapter 3. Charge Pump Analysis 26 Figure 3.7: Efficiency of a 4-stage CW charge pump calculated based on simulation and equation, f = 20 MHz and C T = 320 pf. Figure 3.8: Efficiency of a 4-stage CW charge pump calculated based on simulation and equation, f = 20 MHz, C T = 320 pf, and β = 1.8%.

39 Chapter 3. Charge Pump Analysis Charge pumps for high voltage generations As stated in the previous chapters, the maximum output voltages of charge pumps are limited by the breakdown voltages of the integrated transistors and capacitors. In Dickson and voltage-doubler charge pumps, high-voltage devices can be used to increase the breakdown voltage limitations, however they require special processes and extra areas. In a CW double-ladder charge pump, low-voltage capacitors can be used, but the charge pump output resistance is worse than the Dickson and voltage-doubler charge pumps if same f and C T are applied for N > 1. Since the transfer capacitors occupy most of the area in an integrated charge pump, the capacitor area is usually the most important design constraint. Thus, to evaluate the performances of different charge pumps for high voltage generations, we compare the output resistance of different charge pumps when capacitor area is kept the same as a design constraint. In Dickson and voltage-doubler charge pumps, the total capacitance that can be built within a given area S A using low-voltage MOS capacitors is where ε ox is the permittivity of silicon dioxide. C T = ε ox t ox S A, (3.22) The capacitors of a charge pump with N stages have to sustain a maximum voltage of N. If t ox is the oxide thickness suitable for sustaining in low-voltage devices, we can assume that the oxide thickness required for a charge pump with N stages has to be increased by a factor of N (i.e. using appropriate high-voltage devices). In this case, the capacitance in the same area is at most C T = ε ox S A = C T N t ox N (3.23) and the corresponding charge pump output resistance, R O = N 3 f C T, (3.24) grows with N 3 (i.e. the area is kept constant at S A = C T t ox /ε ox ). To avoid the use of high-voltage devices, the capacitors can also be realized with standard low-voltage MOS devices in series to reduce the voltage across each element. For example,

40 Chapter 3. Charge Pump Analysis 28 Figure 3.9: Normalized output resistance (R O fc T ) as a function of the number of stages (N) for the following circuits: voltage-doubler charge pump with increased t ox (VD thick-ox), voltage-doubler charge pump with series capacitors (VD series-cap), and CW charge pump. the i-th stage must use i 2 unit capacitors to sustain a voltage i with a capacitance equal to the other stages, consequently the total number of capacitors is n i=1 i2. In this case, the charge pump output resistance is when the area is kept constant at S A = C T t ox /ε ox. R O = N 2 (2N 2 + 3N + 1) 6 f C T, (3.25) As shown in Fig. 3.9, the output resistance of the voltage-doubler charge pump is lower when t ox is scaled with N, as R O grows with N 3 according to (3.24). However, the highvoltage devices come at an extra fabrication cost. In this case, the CW charge pump based on low-voltage devices is an attractive solution, if the designer only wants to use low-voltage devices to generate high output voltages.

41 Chapter 3. Charge Pump Analysis Summary In this Chapter, the analysis method and equations describing the characteristics of Dickson, voltage-doubler and CW double-ladder charge pumps are presented. Empirical equations for calculating the characteristics of CW double-ladder charge pump are developed. The empirical equations allow the designers to quickly estimate the charge pump performances and choose design parameters. The charge pumps are also analyzed when high voltage capacitors have to be utilized for high output voltage generation. The Dickson and voltage-doubler charge pumps require high-voltage capacitors to achieve high output voltage, while the CW double-ladder charge pump only uses low-voltage devices. The use of only low-voltage devices reduces the complexity of design process and allows the charge pump to be compatible with standard digital process.

42 Chapter 4 Proposed Designs 4.1 Introduction There are several aspects concerning the design of integrated charge pumps. First, the two major components, switches and capacitors have to be carefully chosen and sized to maximize the performance of the charge pump while meeting the design and layout constrains. The clock signals, which control the switches, need to have sufficient voltage swings (overdrive voltages) and non-overlapping phases to ensure correct operation of the charge pump. The overdrive voltage applied on transistors would determine their on resistances and drain-to-source voltage drops which affect charge pump efficiency and voltage gain. The non-overlapping time slots should be long enough to prevent short-circuit currents while maintaining the desired maximum operating frequency, since they reduce the effective on time of a clock cycle. The clocks also drive the stage capacitors which usually have large capacitances, thus properly sized drivers are needed to provide enough driving strength and minimize the power consumption and area. The block diagram of the charge pump can be seen in Fig Charge pump input power supply ( ) Clock Phase Generator Drivers Charge Pump Output Figure 4.1: Block diagram of a charge pump. 30

43 Chapter 4. Proposed Designs 31 Moreover, the charge pump regulation circuit should be able to adjust the clock frequency according to the difference between the output voltage and reference voltage to keep output voltage stable across different load currents. The transient response should be as fast as possible in an event of a sudden load current change. The block diagram of the regulated charge pump is shown in Fig Charge pump input power supply ( ) Phase Generator Drivers Charge Pump Output Clock Regulation circuits power supply VCO V C Differential Amplifier V ref Figure 4.2: Block diagram of a regulated charge pump. In this chapter, three types of PMOS-based charge pumps are presented. The bootstrapped PMOS single-branch charge pump is designed to alleviate the voltage stress of the switches to use only low-voltage transistors, while in the conventional bootstrapped PMOS charge pump, high-voltage transistors have to be utilized. The charge pump is able to utilize only two non-overlapping phases with the help of the proposed clock boosting circuit. Compared to the conventional bootstrapped PMOS charge pump which uses four non-overlapping clock phases, the proposed design reduces the complexity of the phase generator, eliminates the charge loss through bootstrapping capacitors to improve efficiency and has an extended maximum operating frequency. The improvements over the conventional designs are achieved at the expenses of additional devices and area. The bootstrapped PMOS voltage-doubler charge pump uses cascode PMOS switches to replace the NMOS transistors in the conventional CMOS voltage doubler design. The use of PMOS switches prevents the body effect and high voltage stress of NMOS transistors in a standard technology. As a result, the maximum output voltage range is extended. The voltage doubler also uses only two non-overlapping clocks and the same clock boosting circuit. It has the same advantages over the conventional bootstrapped PMOS charge pump as the proposed single-branch charge pump.

44 Chapter 4. Proposed Designs 32 The bootstrapped PMOS double-ladder charge pump structure makes it possible to generate a high output voltage in a standard process with low-voltage devices only. The same cascode PMOS switches are used to replace the NMOS transistors to extend the output voltage range. The maximum output voltage is only limited by the n-well to substrate breakdown voltage which is as high as 20 V. The proposed double-ladder structure provides a cost-effective way to integrate charge pumps with standard low-voltage CMOS digital process to generate high voltages. Finally, a charge pump regulation scheme, consisting of a VCO, an op-amp and a voltage divider, is proposed. The newly proposed VCO differs from the traditional current starved ring oscillator and can work both in hysteresis and continuous mode. The overall regulation scheme is able to maintain a steady output voltage over a wide current range and achieve a fast transient response in a sudden change of load currents. 4.2 Clocks generation The clock signal is used to drive the stage capacitors and switches. An adjustable external clock is used in our designs for the ease of testing the charge pumps under different frequencies. The external clock is not used directly to drive the capacitors and switches but as an input to produce the non-overlapping clocks, which are necessary for preventing short circuit current. The generation of non-overlapping clocks can be realized by the circuit shown in Fig Clock Delay V en Φ1 Φ1 Φ2 Delay Φ2 V en Figure 4.3: Schematic of the non-overlapping phase generation circuit. The phase generator consists of only inverters, NAND gates and delay elements. Each delay element in Fig. 4.4 is constructed by an inverter and a voltage-controlled RC network

45 Chapter 4. Proposed Designs 33 made of a transmission gate and an NMOS capacitor. The non-overlapping time can be adjusted by changing the RC time constant of the delay elements, where an external DC voltage can be applied to control the on resistance of the transmission gate. V en is an enable signal to turn on and off the phase generator. Input V c V c Output Figure 4.4: Schematic of the voltage controlled delay element. Since the transmission gate consists of both PMOS and NMOS, V c can not be used to control both types of pass transistors. An additional voltage V c should be used and satisfy V c + V c = 1.8 V. V c can be generated using a simple circuit shown in Fig Large resistors should be used to reduce the current consumption. The non-overlapping time slots should be long enough to prevent the short-circuit currents, at the same time they also pose an upper limit of the maximum operating frequency for charge pumps, because as the frequency increases and the semi-clock period eventually equals the non-overlapping time, the output signals of the phase generator will become flat. Thus, the phase generator should be carefully designed to prevent short circuit current and satisfy the maximum operating frequency requirement. The transmission gate and NMOS capacitors are sized to produce a 5 ns non-overlapping time with V c = V c = 0.9 V. The simulation waveforms are shown in Fig. 4.6, where φ 1 and φ 2 are outputs of the phase generator.

46 Chapter 4. Proposed Designs 34 V c R R V c Figure 4.5: Schematic of the V c generation circuit. Figure 4.6: Simulation of the phase generator with a 10 MHz input clock. The generated non-overlapping clocks need to drive the corresponding stage capacitors and bootstrapping switches. Depending on different capacitive loads, the drivers have to be chosen appropriately to provide enough driving strength and minimize the power consumption. A common technique is to use a tapered inverter chain whose sizes increase progressively by a scaling factor of 4 to minimize the power delay product. In each inverter, PMOS are sized 2-3 times larger than the NMOS [19] to have equal rise and fall

47 Chapter 4. Proposed Designs 35 time delay. 4.3 PMOS switches. The switches in charge pumps are implemented with transistors operating in triode region. The transistors should satisfy a number of design requirements. First, they should have very low on resistances to minimize voltage drops. Second, the switches have to stay in the triode region under large load currents. Third, to allow the voltage at each stage to settle to the maximum voltage level during the clock on period, the transistor on resistance has to satisfy the following relationship [20], R ON C i << T ON (4.1) where C i is stage capacitor and T ON is the on time in a clock period. Since C i is determined by the area constrain and usually can be large, very low R ON is desired. To realize low on resistance and large current driving ability, we can choose large W/L ratios for the transistors according to (4.2) [3], where k p is PMOS process transconductance parameter, W and L are the width and length of the transistor, and V t is the threshold voltage. R ON = 1 k p W L V GS V t. (4.2) However, increasing transistor sizes beyond necessary will degrade the charge pump performance, since they add parasitic capacitances which decrease the charge pump gain and power efficiency. Larger transistors also need larger drivers, which increase the dynamic power consumption, further reducing the efficiency. We can also use a large negative V GS to reduce the on resistance. However, V GS is limited since it should not exceed the gate oxide breakdown voltage, which is usually defined as the recommended voltage rating of the technology. In our design, the voltage rating is = 1.8 V. To effectively turn on and off the PMOS transistors in triode region, the overdrive voltage (V GS ) must be sufficient. V GS must satisfy the following relationships, where V t is the threshold voltage of PMOS transistors and is negative.

48 Chapter 4. Proposed Designs 36 V GS < V t, V DS > V GS V t. (4.3) In a charge pump, there are three possible drain and source voltage combinations for the PMOS switches, which require different gate voltages to be turned on and off. V G V G N N + N N (a) PMOS switch is off (b) PMOS switch is on Figure 4.7: Drain and source voltages across the PMOS switches in case 1. V G V G N - N + N N (a) PMOS switch is off (b) PMOS switch is on Figure 4.8: Drain and source voltages across the PMOS switches in case 2. V G V G N N + N + N + (a) PMOS switch is off (b) PMOS switch is on Figure 4.9: Drain and source voltages across the PMOS switches in case 3. The first case is shown in Fig To turn off the transistor, we must have V G > (N + 1) + V T, we can choose V GH = (N + 1). To turn on the transistor, we must have V G < N + V T, we can choose V GL = (N 1), which means it is necessary to have a V G which has 2 swing for the switch to function (i.e. V GH V GL = 2 ). The second case is shown in Fig By using similar approaches, we can conclude that V G also needs to have 2 swing in this case. The third case is shown in Fig To turn on the transistor, we only need V GL = N, and to turn off the transistor, we should have V GH = (N + 1), which means V G with one swing is sufficient (i.e. V GH V GL = )..

49 Chapter 4. Proposed Designs 37 From Figs. 4.7, 4.8, 4.9, we can see that it is necessary to generate gate voltages with 2 swing to turn on and off the switches in case 1 and 2. This can be achieved by using a 4-phase clock scheme which is utilized in the Umezawa charge pump [4]. However, the 4-phase clock scheme reduces the charge pump efficiency and maximum operating frequency. To overcome such disadvantages, we proposed a circuit to generate 2 clocks with 2 voltage swing and are in phase with the original non-overlapping clocks. With properly designed bootstrapping circuits, the proposed circuit can prevent the charging and discharging of the bootstrapping capacitors and effectively turn on and off the switches. 4.4 Clock-boosting circuit The 2 clocks can be generated by the clock boosting circuit in Fig The supply voltage of the clock boosting circuit is provided by the 2 voltage at node M1, The dimensions of G3 and G4 are chosen such that node T is at half the voltage of M1. G3 and G4 are designed to have small W/L ratios to minimize current consumption. In the clock boosting circuit, voltages across any transistors are never higher than, thus low voltage transistors can be used. M1 G1 G2 G5 G7 Φ2 O1 O2 Φ1 G3 T G6 G8 G4 Figure 4.10: Proposed clock boosting circuit. The operation of the circuit is described as follows. When φ 1 is low and φ 2 is high, G5 is on (V gs = ) and G6 is off (V gs = 0), at the same time, G7 is off (V gs = 0) and G8 is on (V gs = ), so O1 is high (2 ) and O2 is low (0 V). O2 is high (2 ) and O1

50 Chapter 4. Proposed Designs 38 is low (0 V) when φ 1 goes high and φ 2 goes low. The input and output waveforms of the circuit are shown in Fig Figure 4.11: Simulation of clock boosting circuit. The 2 voltage at M1 can be supplied by an intermediate stage in the charge pump. This supply voltage varies with the output load current, meaning that when the output current of the charge pump is zero, the voltage at M1 is 2. Otherwise, the voltage at M 1 decreases as the load current rises, reducing the gate voltage stress on transistors at high current load. The intermediate stage also reduces the drain-to-source voltage stress across transistor switches, so low-voltage devices can be used. The entire charge pump design, with the clock boosting circuit, is shown in the following sections. 4.5 Proposed single-branch charge pump with bootstrapped PMOS switches The proposed 2-stage single-branch bootstrapped PMOS charge pump is presented in Fig An intermediate voltage cell is added between stage 1 and stage 2 to provide a stable 2 voltage to generate clocks with 2 swing and reduce the voltage stress of the

51 Chapter 4. Proposed Designs 39 PMOS switches. The capacitor used in the intermediate voltage cell is small and only 8% of the stage capacitor. The intermediate voltage cell adds parasitic capacitance (although very small) and slows down the start-up transient since the additional capacitor needs to be charged. Finally, in a charge pump with N stages, (N 1) number of intermediate voltage cells are needed to keep the voltage stress across the switches, within thus increasing the area overhead. O1 Φ2 O2 Φ1 C b C b C b G3 H1 M1 H2 S1 S2 S3 S4 Vout C i C s C s C L Intermediate Clock O2 V Voltage Cell DD boosting circuit O1 Φ1 Φ2 Φ1 Φ2 Φ2 Φ1 Figure 4.12: Schematic of the proposed single-branch charge pump with bootstrapped PMOS switches. The bootstrapped switch circuits are controlled by the non-overlapping signals (Fig. 4.13) with 2 and voltage swings. Φ1 Φ2 O1 2 O2 2 t0 t1 t2 t3 t4 Figure 4.13: The clock signals in the proposed single-branch charge pump. The boosting capacitors need to be sized properly to supply the required overdrive voltage, since the boosted voltage at the gate of the pass transistor is reduced because of the

52 Chapter 4. Proposed Designs 40 loading capacitance C gate which is the gate oxide capacitance of the main transistor switch. The boosted voltage V B at each stage can be expressed as C b V B = V i 1 +. (4.4) C b + C gate In our design, the bootstrapping capacitor C B are sized approximately 10 times larger than C gate to ensure the required overdrive voltages. The bootstrapping capacitors do not contribute to additional parasitics, since the 2 non-overlapping clocks do not provide additional time slots to allow charging and discharging of the bootstrapping capacitors. The operation of the 2-stage charge pump in steady state is described in Table 4.1. None of the transistors sustain voltages higher than, so low-voltage devices can be used. It has to be noted that since the clock signals have finite rise and fall time, and are not perfectly in phase with each other. During the clock transitions, when the bootstrapping transistors are not fully turned off, it induces charge loss from the bootstrapping capacitors through the bootstrapping transistors. The charge loss causes the over-drive voltages at the gates of pass transistors to be less sufficient than expected. This phenomenon reduces the efficiency and voltage gain of the charge pump. Moreover, the degraded overdrive voltages are more prominent when the 2 clocks are not fully boosted during charge pump start-up, this causes short circuit current that possibly slows down the start-up transient. Table 4.1: Operation of the proposed PMOS charge pump Time S1 S2 S3 S4 H1 M1 G3 H2 V out t0 off on on off t1 off off off off t2 on off off on t3 off off off off t4 off on on off

53 Chapter 4. Proposed Designs Proposed voltage-doubler charge pump with bootstrapped PMOS switches The proposed 2-stage voltage-doubler charge pump is shown in Fig A CMOS-based cell is chosen for better reliability in the first stage. NMOS transistors do not sustain high voltages and the body effect is negligible. The rest of the charge pump consists of all-pmos cells which are driven by the same clock scheme shown in Fig In a voltage-doubler charge pump, the voltage level after each stage is stable [21], so the intermediate voltage cell is not used. Same clock boosting circuit is used to drive the bootstrapped capacitors and transistors. Φ1 Φ2 CMOS stage PMOS stage Φ1 Φ2 C s S1 C s S3 S5 S6 S9 Φ1 Φ2 M1 O1 Φ2 Vout Φ2 Φ1 Clock boosting circuit O2 O1 O2 S7 Φ1 S8 S10 C s Φ1 Φ2 S2 C s S4 Φ1 Φ2 Φ1 Φ2 Figure 4.14: Proposed 2-stage voltage-doubler charge pump. The proposed PMOS stage consists of 4 main PMOS pass transistors (S1, S2, S3, S4) and six boosting PMOS transistors (S5, S6, S7, S8, S9, S10). The operation of the PMOS cell can be described as follows. From t0 to t1, S1 and S4 are off, while S2 is on and the bottom transfer capacitor is charged from the previous stage. S3 is on and connects the top capacitor to the next stage. S5 and S6 are on while S7 and S8 are off. S9 is off and S10 is on.

54 Chapter 4. Proposed Designs 42 From t1 to t2, all the transistors are off to prevent short circuit currents through drivers and switches. S5 and S7 are still on, however S6 and S8 are off to avoid any unwanted charge transfer. From t2 to t3 and t3 to t4, the charge pump works in a similar manner as in the previous time slots. Same as the proposed single-branch charge pump charging and discharging of the bootstrapping capacitors in steady stage are prevented, thus reducing equivalent parasitic capacitances compared to the bootstrapped PMOS Dickson charge pump [4]. Furthermore, the bootstrapping transistors S5 and S6, S7 and S8 are cascoded to reduce any charge loss caused by the finite rise/fall time and delay of the clocks signals. It is expected that the proposed voltage-doubler should have better static and transient performances compared to the single-branch charge pump. 4.7 Proposed double-ladder charge pump with bootstrapped PMOS switches The proposed double-ladder charge pump has similar structures as the CW charge pump, but utilizes PMOS transistors as switches instead of diodes. The charge pump consists of two symmetrical capacitor branches, sized to achieve optimal output resistance. The PMOS switches are the same as in the proposed voltage-doubler charge pump. The stage capacitors are connected in series and only the first stage is connected to the drivers. The behaviour of the phases is the same in every stage. The clock boosting circuit is connected at M1 to generate the 2 clocks for driving the bootstrapped circuits. The bootstrapping capacitors are also connected in series to avoid high voltage stress. The proposed 4-stage double-ladder charge pump is shown in Fig The charge pump uses low-voltage transistors and capacitors to generate an output voltage of 5, which is much higher than the transistor voltage rating (1.8 V). The double-ladder structure allows the charge pump to generate a high output voltage without using any high-voltage devices, which require additional cost and extra fabrication steps, or are not available to designers.

55 Chapter 4. Proposed Designs 43 VDD Φ2 Φ1 Φ2 VDD Φ1 O1 Vout M1 Φ2 O2 Φ1 VDD Φ2 Φ1 Figure 4.15: Proposed 4-stage double-ladder charge pump. 4.8 Charge pump regulation circuits A regulation scheme suitable for charge pumps is proposed, it consists of a voltage controlled oscillator (VCO) and an operational amplifier (op-amp). Ring oscillator is chosen because it is easily integratable and occupies a small area. Usually, a current starving ring oscillator is used, the frequency of which can be controlled by an external voltage. The controlling voltage is often provided by a transconductance amplifier to control the current going in or coming out of a capacitor, thus creating a voltage V C by comparing the feedback voltage and the reference voltage Fig To have a stable V C, the load capacitor must be large, which makes V C response slowly if there is a sudden change of the feedback voltage (due to load current change). This can cause the charge pump output voltage to dip or overshoot until it settles down. The proposed ring oscillator is shown in Fig Its frequency can be adjusted by controlling the on-resistance of the PMOS pass transistor to change the RC time delay. The frequency characteristic is shown in Fig From 0 V to 0.6 V, the output frequency is linearly dependent to V C, when the pass transistors are in triode region. As V C increases, the pass transistors enter saturation region and eventually turned off. Thus the frequency is not linear and becomes zero at the end. Fig shows the operation of the VCO in continuous mode, which requires a stable V C to control the frequency.

56 Chapter 4. Proposed Designs 44 Reference voltage Feedback from charge pump output gm I in I out V C Current Starved VCO Figure 4.16: The block diagram of transconductance amplifier used to adjust the VCO frequency. V c V c V c V c V c V c CLK V c V c V c V c Figure 4.17: Proposed VCO. It poses same design obstacles for the transconductance amplifier as the current starved VCO does and has voltage disturbances under a sudden change of load current. To resolve the above issue, the proposed VCO is used in hysteresis mode, where a pulse train signal can be used to control the frequency due to the fact that the VCO maintains the previous voltage level when the PMOS pass transistor is shut off. The operation in hysteresis mode is shown in Fig and can be explained as follows. The ring oscillator is turned on for just enough time to make one transition (low-to-high or high-to-low), then it is turned off while maintaining the previous voltage level. The pulse width of the pulse signal has to equal to n i=1 τ i to allow exactly one transition, where n is the number of delay elements (including inverters) and τ i is the delay of that element.

57 Chapter 4. Proposed Designs 45 Figure 4.18: Frequency and controlling voltage relationship of proposed VCO. Figure 4.19: Hysteresis mode operation of VCO under a pulse train. However, when implementing the regulation circuit, it is not necessary to provide a precise pulse train signal. Since we are going to use an op-amp to generate V C shown in Fig.

58 Chapter 4. Proposed Designs , we just have to make sure the op-amp can swing from low-to-high or high-to-low fast enough to allow one transition for the VCO. An open-loop high gain amplifier can be implemented for such a requirement. Charge pump output V C R2 R1 V ref R3 Figure 4.20: Proposed operational amplifier. The feedback from the charge pump output can be realized by a resistive divider. The resistive divider consists of large resistors to minimize current consumption. The large resistance, along with the capacitance can potentially create a pole at feedback node and affect the stability of the regulation system. Thus, the sizes of the input pair transistors of the op-amp have to be limited to reduce the capacitance associated with that node and ensure the stability of the regulation system. The op-amp must have a large open loop gain, so the output can swing fast enough for the VCO to operation as expected. The op-amp consumes very little power and only draws 25 µa of current. The simulation results of using the proposed regulation circuit with a 2-stage charge pump are shown in Chapter Summary In this chapter, we have analyzed and discussed the proposed designs of integrated charge pumps with only PMOS transistors. The proposed charge pumps utilize a clock boosting

59 Chapter 4. Proposed Designs 47 circuit with only 2 non-overlapping clocks to eliminate the additional parasitic capacitances due to the boosting capacitors, which are present in the conventional 4-phase PMOS charge pump. As a result, the proposed charge pumps have better efficiencies and extend operating frequency range than the conventional PMOS-based charge pump. The proposed designs are able to alleviate the high voltage stress across the transistors to generate high output voltages without using high-voltage transistors nor triple-well processes. The CW charge pump is a complete solution of generating high voltage with only low-voltage devices (transistors and capacitors). The proposed regulation scheme consists of a proposed VCO and a simple high gain op-amp, it consumes very little power and is able to achieve a fast transient when a sudden charge of load current is present. The simulation and measurement data of the proposed circuits will be presented in Chapter 6.

60 Chapter 5 Simulation Results 5.1 Introduction This chapter presents the simulation results of the proposed charge pumps. Six different circuits are simulated and tested to evaluate their steady stage and transient behaviour. The key design specifications of the circuits are listed in Table 5.1. The purpose of implementing the 2-stage single branch and voltage-doubler charge pumps is to evaluate the functionality and effectiveness of the proposed bootstrapped PMOS switches and to compare the performances between the two charge pump configurations. The 4-stage and 6-stage double-ladder charge pumps are implemented to verify if the proposed structure can generate high output voltages with using only low-voltage transistors and capacitors. Two regulated charge pumps are implemented to evaluate the performance of the proposed regulation scheme. The simulations are conducted using the nominal device models in the TSMC 0.18 µm analog library. The simulation results are compared with the theoretical analysis results to verify the functionalities and performances of the proposed bootstrapped PMOS charge pumps and regulation circuits. Parasitic capacitances of the bootstrapping and stage capacitors are included in the schematics to achieve realistic simulation results that can be also be used to provide functional and performance references for the fabricated chip. The detailed schematics used in the simulations are presented in Appendix B. 48

61 Chapter 5. Simulation Results 49 Table 5.1: Design specifications of the proposed circuits Name Stages Type Regulation C T f α β CP1 2 single branch no 1.8 V 500 pf 1-10 MHz 1.5% 1.2% CP2 6 double-ladder no 1.8 V 630 pf 1-10 MHz 1.5% 1.2% CP3 2 single branch yes 1.8 V 500 pf N/A 1.5% 1.2% CP4 2 voltage-doubler no 1.8 V 500 pf 1-10 MHz 1.5% 1.2% CP5 4 double-ladder no 1.8 V 450 pf 1-10 MHz 1.5% 1.2% CP6 2 voltage-doubler yes 1.8 V 500 pf N/A 1.5% 1.2% 5.2 Steady state simulations Output voltage characteristics and conversion efficiencies are evaluated in steady-state conditions as functions of the load currents. The simulation results are compared to the theoretical models with parasitic capacitances taken into account Unregulated 2-stage single branch PMOS charge pump The unregulated 2-stage single branch PMOS charge pump is simulated to evaluate its steady state characteristics. Fig. 5.1 and Fig. 5.2 show the simulation and theoretical output characteristics and conversion efficiencies as functions of the load currents at 1 MHz and 10 MHz at room temperature with nominal device models. The currents and voltages are both measured in steady state. Table 5.2: Key performance parameters of the unregulated 2-stage single branch PMOS charge pump f Type Maximum V O R O Peak η 1 MHz Theoretical 5.36 V 7905 Ω 80.4% 1 MHz Simulation 5.34 V Ω 78.1% 10 MHz Theoretical 5.34 V Ω 80.4% 10 MHz Simulation 5.35 V Ω 79.5% The key performance parameters of the simulation and theoretical results are summarized in Table The simulation shows the charge pump is able to generate a maximum voltage of about 5.3 V reliably. The voltages across the transistors are also checked and verified that they do not exceed under different load currents. The charge pump performances are very close to the theoretical results, implying the proposed bootstrapped

62 Chapter 5. Simulation Results 50 circuits and clock scheme works very well. The small deviations from the theoretical analysis are due to the additional parasitic capacitances from the transistors, other secondary and non-ideal effects. In addition, the non-ideal (finite rise/fall time and edge misalignment) clock signals cause charge loss through the bootstrapping transistors and from the bootstrapping capacitors, thus the simulation conversion efficiency is lowered. Nevertheless, the deviation from the theoretical analysis is small. The simulation peak efficiency is only 1-2% lower than the theoretical result, while the theoretical best peak efficiency of the Umezawa PMOS charge pump is 6-7% lower due to charging and discharging of the bootstrapping capacitors. The simulation results indicate that the proposed charge pumps can successfully eliminate the charging and discharging of the bootstrapping capacitors and have better efficiencies than the conventional bootstrapped PMOS charge pumps. Figure 5.1: Simulation and theoretical output voltage characteristics and conversion efficiencies of the unregulated 2-stage single branch PMOS charge pump, with f = 1 MHz, C T = 500 pf, α = 1.5% and β = 1.2%.

63 Chapter 5. Simulation Results 51 Figure 5.2: Simulation and theoretical output voltage characteristics and conversion efficiencies of the unregulated 2-stage single branch PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2% Unregulated 2-stage voltage-doubler PMOS charge pump The unregulated 2-stage voltage-doubler PMOS charge pump is simulated to evaluate its steady state characteristics. Fig. 5.3 and Fig. 5.4 show the simulation and theoretical output voltage characteristics and conversion efficiencies as functions of the load currents at 1 MHz and 10 MHz at room temperature with nominal device models. The currents and voltages are both measured in steady state. Table 5.3: Key performance parameters of the unregulated 2-stage voltage-doubler PMOS charge pump f Type Maximum V O R O Peak η 1 MHz Theoretical 5.36 V 7905 Ω 80.4% 1 MHz Simulation 5.34 V Ω 79.4% 10 MHz Theoretical 5.36 V Ω 80.4% 10 MHz Simulation 5.35 V Ω 80.1% The key performance parameters of the simulation and theoretical results are summarized in Table 5.3. The simulation results are also very close to the theoretical analyses. The output resistances and conversion efficiencies are slightly better than the proposed single

64 Chapter 5. Simulation Results 52 Figure 5.3: Simulation and theoretical output voltage characteristics and conversion efficiencies of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 1 MHz, C T = 500 pf, α = 1.5% and β = 1.2%. Figure 5.4: Simulation and theoretical output voltage characteristics and conversion efficiencies of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2%.

65 Chapter 5. Simulation Results 53 branch charge pump. The improvements in the voltage-doubler charge pump is because the PMOS bootstrapping switches use cascoded transistors which reduce the charge loss through the bootstrapping path. Thus, the voltage-doubler PMOS charge pump has better static performances than the single branch PMOS charge pump at the cost of more complex bootstrapping circuit design. Also, the simulation peak efficiency is only less than 1% lower than the theoretical result, indicating there is no charging or discharging of the bootstrapping capacitors stage regulated PMOS charge pumps This section presents the steady state simulation results of the regulated 2-stage single branch and voltage-doubler charge pumps, which are designed to maintain a constant output voltage of 4.2 V with a reference voltage of 0.7 V. The charge pumps are controlled by the internal clocks with varying frequencies at different load current. Figure 5.5: Theoretical output voltage characteristics and conversion efficiencies of a 2-stage charge pump under different frequencies, f = 1, 2, 3, 4, 5, 6 MHz, C T = 500 pf, α = 1.5% and β = 1.2%. The theoretical concept can be explained in Fig. 5.5, which shows the theoretical static characteristics of a 2-stage charge pump under different frequencies. The output voltage

66 Chapter 5. Simulation Results 54 is kept to be 4.2 V for different frequencies, and is represented by the red line. The conversion efficiencies can be found by projecting the cross points of the red line and the output voltage curves on the corresponding efficiency plots. The conversion efficiencies for different frequencies thus can be are represented by the green line, which is also constant. We can conclude, for an ideal regulated charge pump, the output voltage and conversion efficiency should both be constant over a range of load current of interested. In our case, the output voltage should be 4.2 V and the conversion efficiency should be 74.32%. Fig. 5.6 and Fig. 5.7 present the simulation output voltage characteristics and conversion efficiencies of the proposed regulated 2-stage single branch and voltage-doubler charge pumps under different load currents. For both charge pumps, the output voltages are regulated at around 4.2 V up to 1.7 ma load current. The output voltages and conversion efficiencies both start to drop when load current is greater than 1.7 ma. It is because the internal VCO is only able to generate a clock signal with a maximum frequency of 13 MHz. At current beyond 1.7 ma, the clock frequency is at maximum and does not increase anymore to provide enough amount of load current, thus both the output voltage and efficiency rolls down. The voltage doubler Figure 5.6: Simulation output voltage characteristics and conversion efficiencies of the regulated 2-stage single branch charge pump, with V ref = 0.7 V, C T = 500 pf, α = 1.5% and β = 1.2%.

67 Chapter 5. Simulation Results 55 Figure 5.7: Simulation output voltage characteristics and conversion efficiencies of the regulated 2-stage voltage-doubler charge pump, with V ref = 0.7 V, C T = 500 pf, α = 1.5% and β = 1.2%. has better efficiencies than the single branch charge pump, which is consistent with the results observed from the unregulated charge pumps stage and 6-stage double-ladder PMOS charge pumps The double-ladder PMOS charge pumps are designed to generate high output voltages with using only low-voltage devices. The proposed circuits have 4 and 6 stages to generate maximum output voltages of 9 V and 12.6 V. Figs. 5.10, 5.11, 5.8, and 5.9 present the simulation and theoretical output voltage characteristics and conversion efficiencies of the 2 charge pumps as functions of the load currents at 1 MHz and 10 MHz at room temperature with nominal device models. The currents and voltages are both measured in steady state. The simulation shows the charge pumps are able to generate maximum voltages of 8.36 V and 10.8 V reliably. The voltages across the transistors are checked and verified that they do not exceed under different load currents. The simulation output voltage characteristics are close to the theoretical results with slightly better output resistances.

68 Chapter 5. Simulation Results 56 Figure 5.8: Simulation and theoretical output voltage characteristics and conversion efficiencies of the 4-stage double-ladder PMOS charge pump, with f = 1 MHz, C T = 450 pf, α = 1.5% and β = 1.2%. Figure 5.9: Simulation and theoretical output voltage characteristics and conversion efficiencies of the 4-stage double-ladder PMOS charge pump, with f = 10 MHz, C T = 450 pf, α = 1.5% and β = 1.2%.

69 Chapter 5. Simulation Results 57 Figure 5.10: Simulation and theoretical output voltage characteristics and conversion efficiencies of the 6-stage double-ladder PMOS charge pump, with, f = 1 MHz, C T = 630 pf, α = 1.5% and β = 1.2%. Figure 5.11: Simulation and theoretical output voltage characteristics and conversion efficiencies of the 6-stage double-ladder PMOS charge pump, with, f = 10 MHz, C T = 630 pf, α = 1.5% and β = 1.2%.

70 Chapter 5. Simulation Results 58 Table 5.4: Key performance parameters of the unregulated double-ladder PMOS charge pump N f Type Maximum V O R O Peak η 4 1 MHz Theoretical 8.36 V kω 52.71% 4 1 MHz Simulation 8.34 V kω 47.25% 4 10 MHz Theoretical 8.36 V kω 52.71% 4 10 MHz Simulation 8.36 V kω 48.8% 6 1 MHz Theoretical 10.8 V kω 38.66% 6 1 MHz Simulation V kω 35.77% 6 10 MHz Theoretical 10.8 V kω 38.66% 6 10 MHz Simulation 10.8 V kω 35.01% The peak conversion efficiencies from the simulations are 3-5% lower than the theoretical analyses results. The primary reason for the simulation results to deviate from the theoretical results is the additional parasitic capacitances contributed by other devices (transistors and capacitors). In the double-ladder charge pumps, the stage capacitors are smaller due to the area constraint and the large number of stages, thus the parasitic capacitances from the transistor switches (large W/L) has a big percentage fraction over the stage capacitors, resulting bigger α and β, which reduce the output resistances and conversion efficiencies. However, the simulation results shows the maximum output voltage can reach 8.36 V and 10.8 V for the 4-stage and 6-stage charge pump, which shows the double-ladder charge pumps can generate high voltages beyond the transistor gate oxide and junction breakdown voltage limitations. 5.3 Transient simulations Another two important parameters are how fast the charge pump can reach the maximum voltage level from 0 V and how much energy it consumes during the start-up time. In this section, we show the simulation waveforms of the start-up transients of the proposed charge pumps. For the regulated charge pumps, we also present the internal clock signals and output voltages under a sudden change of load current to show how the regulation circuits work. These simulation waveforms can be used as references when testing the fabricated circuits. The load capacitors are 1 nf and their initial conditions are 0 V.

71 Chapter 5. Simulation Results stage unregulated PMOS charge pumps The start-up transients of the 2-stage unregulated single branch and voltage-doubler PMOS charge pump with 10 MHz input clock are shown in Fig and Fig Figure 5.12: Start-up transient of the unregulated 2-stage single branch PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2%. Figure 5.13: Start-up transient of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2%.

72 Chapter 5. Simulation Results 60 The output voltage of the single branch PMOS charge pump reaches 90% of its maximum voltage at 2.5 µs, and the output voltage of the voltage-doubler charge pump reaches 90% of its maximum voltage at about 2.4 µs. Although the start-up time of the two proposed 2-stage charge pumps has no significant differences, the voltage doubler is slightly faster, thanks to the cascoded bootstrapping transistors that reduce charge losses during clock transitions. The 2-stage single branch charge pump consumes nj of energy during start-up, and the 2-stage voltage-doubler charge pump consumes nj of energy during start-up stage regulated PMOS charge pumps The start-up transients of the proposed regulated single branch and voltage-doubler charge pumps are shown in Fig and Fig respectively. During start-up the internal clock is at its maximum frequency (13 MHz) to charge pump the output, because the output level is below the reference voltage. The internal clock is disabled as soon as the output voltage exceeds the target voltage and maintains at that level if there is no load current present. Figure 5.14: Start-up transient of the regulated 2-stage single branch PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2%. Fig and Fig show the output voltage, internal clock signal and the VCO control voltage of both regulated charge pumps when a sudden change of load current is applied

73 Chapter 5. Simulation Results 61 Figure 5.15: Start-up transient of the regulated 2-stage voltage-doubler PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2%. Figure 5.16: Output voltage, internal clock and VCO control voltage of the regulated 2-stage single branch PMOS charge pump under a load current change, with C T = 500 pf, α = 1.5% and β = 1.2%. at the output (100 µa to 1 ma). The output voltage is kept at the target voltage (4.2 V) without any oscillation or instability. The clock frequency generated by the VCO is increased in order to compensate the increased load current. The VCO control voltage

74 Chapter 5. Simulation Results 62 Figure 5.17: Output voltage, internal clock and VCO control voltage of the regulated 2-stage voltage-doubler PMOS charge pump under a load current change, with C T = 500 pf, α = 1.5% and β = 1.2%. also swings more frequently. The clock pulse width in the single branch charge pump is narrow and seems not to change with the frequency, it is because the output voltage increases only at the falling edge of the clock and the op-amp also reacts at the same time. During the rising edge of the clock, the output is still discharging, thus regulation circuit has to quickly generate a high-to-low transition to pump the output again, which makes the clock pulse width narrow. In the voltage-doubler charge pump, the output voltage is charged up at both the falling and rising edges, and the regulation also reacts at both clock edges to generate a clock signal with more uniformly distributed clock edges. The voltage doubler also has less output voltage ripple stage and 6-stage double-ladder PMOS charge pumps The start-up transients of the 4-stage and 6-stage double-ladder PMOS charge pumps at 10 MHz are shown in Fig and Fig The output voltage of the 4-stage double-ladder PMOS charge pump reaches 90% of its maximum voltage in 40 µs, and 6-stage double-ladder PMOS charge pump reaches 90% of its maximum voltage in about 120 µs. The start-up time of the double-ladder

75 Chapter 5. Simulation Results 63 Figure 5.18: Start-up transient of the 4-stage double-ladder PMOS charge pump, with f = 10 MHz, C T = 630 pf, α = 1.5% and β = 1.2%. Figure 5.19: Start-up transient of the 6-stage double-ladder PMOS charge pump, with f = 10 MHz, C T = 450 pf, α = 1.5% and β = 1.2%. PMOS charge pumps are slow due to the circuit topology; however the purpose of the double-ladder structure is to generate high output voltages. The start-up time can be improved by increasing the operating frequency or the total transfer capacitance. The

76 Chapter 5. Simulation Results 64 4-stage double-ladder charge pump consumes 80.1 nj of energy during start-up, and the 6-stage double-ladder charge pump consumes nj of energy during start-up. 5.4 Conclusion This chapter presents the simulation results of the proposed circuits. The proposed circuits have been optimized in the their schematic designs, so their simulation performances are close to the theoretical models. The proposed unregulated 2-stage single branch and voltage-doubler charge pumps work successfully with the clock boosting circuit and bootstrapped PMOS switches. The voltage doubler has a better static characteristics and less output ripple than the single branch charge pump at the expense of more complicated bootstrapping circuit design. The regulated charge pumps can successfully regulate the output voltage to a constant voltage level under a wide range of load currents. To increase the current driving capability, we can increase the VCO maximum frequency or the size of the stage capacitors. The transient simulations show that the regulated charge pumps have very fast responses and the output voltage levels do not dip or overshoot during a sudden load current change. The double-ladder charge pumps can successfully generate voltages as high as 10.8 V beyond the breakdown voltage limitations of the low-voltage devices. The voltages across the transistors and capacitors are also verified to be within, so the low-voltage devices operate under the suggested voltage rating in very reliable conditions. This makes the double-ladder charge pump a suitable implementation to be integrated with the standard digital CMOS circuits without using neither high-voltage devices nor triplewell processes.

77 Chapter 6 Fabrication and Testing of the Proposed Circuits 6.1 Tools and design flow To ensure the functionality and guarantee good performance of the proposed designs, transistor level simulations are conducted using Cadence Composer and Spectre circuit simulator. After completing the schematics design, the chip layout was drafted using Cadence Virtuoso. Mentor s Calibre tool is used with the layout editor for physical verification purposes. Design rule check (DRC) is performed to meet all design rules. Layout Versus Schematic (LVS) is to ensure that the layout implementation matches the schematics. At last, a post-layout simulation is conducted to verify the circuit functionality with the parasitics extracted from the layout. The design flow followed in this project is shown in Fig Fabrication technology of the proposed circuits The proposed charge pumps and regulation circuits are fabricated in a TSMC 0.18 µm standard digital CMOS process. The technology provides a single poly layer, 6 metal layers, MIM capacitor and deep N-well layer. It also provides two types of transistors with nominal voltages of 1.8 V and 3.3 V respectively. The 3.3 V device has a thicker oxide 65

78 Chapter 6. Fabrication and Testing of the Proposed Circuits 66 Theoretical Models Redesign Electrical Design (Schematic) Successful Product Pass Simulation Fail Test to Theoretical Models Fail Compare with Theoretical Models Redesign Fabrication Redesign Pass Physical Design (Layout) Fail Pass Compare with Theoretical Models Design Rule Check (DRC) Simulation Fail Layout Versus Schematic (LVS) Parasitic Extraction Pass Figure 6.1: Analog IC design flow used in this project. layer with a higher breakdown voltage and can be used for implementing high-voltage MOS capacitors, which are needed for Dickson and voltage-doubler charge pumps. The specific capacitance of the 3.3 V NMOS capacitors is approximately 5.4 ff/µm 2 with α = and β = (based on technological parameters). In our design, we use both of the 1.8 V and 3.3 V transistors operating with 1.8 V power supply. The high-voltage devices are used for better yield and reliability, although the transistors only experience voltages lower or equal to 1.8 V. The technology also provides a HRI poly layer which has a high resistance per area for implementing resistors. The total chip area is 1.3 mm 2 mm (2.6 mm 2 ), most of which is occupied by integrated capacitors, which poses a design constraint on the total transfer capacitances of each charge pump.

79 Chapter 6. Fabrication and Testing of the Proposed Circuits Layout Layout is a very important step for implementing high performance mixed signal circuits, such as charge pumps. In our design, careful layout is needed for matching of the devices (transistors, resistors and capacitors), reducing the parasitics, and minimizing the RC delays of the signal paths. Other layout issues, such as power routing, latch-up, signal coupling should be considered as well. The layout of the proposed circuits and design issues are presented in this section MOS switch layout and consideration The PMOS switches used in the proposed charge pumps have large W/L ratios. The transistors are laid out in multiple fingers instead of a single poly line to reduce the parasitic capacitance and resistance. The transistors are surrounded by N-well contacts (guard rings) to prevent latch-up. A PMOS transistor layout is shown in Fig Figure 6.2: Layout of a PMOS transistor. The bootstrapping capacitor and transistor are placed right next to the main PMOS switch to minimize any parasitic capacitance and resistance, so the boosted voltage can achieve its maximum as quickly as possible. The connections to the transfer capacitors and other stages of the charge pump use wide metal lines and many contacts in order to sustain large currents and reduce the RC delays. The layouts of the bootstrapped PMOS switches in the proposed charge pumps are shown in Fig. 6.3 and Fig NMOS capacitor layout and consideration The NMOS capacitors are constructed using silicon dioxide as the dielectric between the polysilicon layer and diffusion layer shown in Fig The thickness of the oxide layer is

80 Chapter 6. Fabrication and Testing of the Proposed Circuits 68 Figure 6.3: Layout of the bootstrapped switch in the single-branch PMOS charge pump. Figure 6.4: Layout of the bootstrapped switch in the voltage-doubler and CW charge pumps. 4.1 nm and can achieve a capacitance per unit area of 5.4 ff/µm 2. The diffusion layer is negatively doped and is different than a NMOS transistor which has a p-well. This ensures that the capacitor operates in the inversion mode and its capacitance does not have a large voltage dependence [3]. The top and bottom plate parasitic capacitances of the NMOS capacitor are contributed by the capacitances between n-well and substrate, and between the polysilicon layer and the substrate. The polysilicon and n-well also contribute undesired parasitic resistances, which can be minimized by connecting multiple capacitors in parallel. Large integrated capacitors are usually constructed with a group of optimized unit capacitors to minimize the parasitic resistances. For precise capacitance matching,

81 Chapter 6. Fabrication and Testing of the Proposed Circuits 69 Poly Gate S i O 2 n + n-well n + p-substrate Figure 6.5: Vertical structure of the NMOS capacitor. unit size dummy capacitors should be placed around the capacitors of interest. In our design, we are interested in maximizing the capacitance per area, so dummy capacitors are not used. Fig. 6.6 shows the layout of a NMOS capacitor, consisting a number of unit capacitors in parallel. Figure 6.6: Layout of a NMOS capacitor Other considerations There are many layout techniques to be considered to improve the circuit performance and yield, the details can be found in [22]. We list a few below that are important in our design. For the digital circuits (phase generator and ring oscillator), transistors with minimum length are used to minimize the area, the interconnections use wide metal lines to reduce the RC delay. The wire capacitance is dominated by its sidewall capacitance, so increasing the wire width decreases the resistance and the RC product. The power routing should also use wide wires to avoid electromigration for high load currents. The digital signals, such as the clocks, should be far from each other and any long wires

82 Chapter 6. Fabrication and Testing of the Proposed Circuits 70 carrying DC voltages to reduce any single coupling and parasitic capacitance. The opamp and resistive divider in the regulation circuit require good matching; the transistors and resistors should be laid out in a interdigitated manner with dummies to minimize any process variation. Finally, correct I/O pads should be chosen for different I/O connections. The entire chip layout is shown in Fig stage single branch charge pump 6-stage CW charge pump Regulated 2-stage single branch charge pump CP1 CP2 CP3 CP4 CP5 CP6 4-stage CW charge pump 2-stage voltage-doubler charge pump Regulated 2-stage voltagedoubler charge pump Figure 6.7: Chip floorplan. 6.4 Package After submitting the layout to the manufacturer, the chip is fabricated and packaged in a 24-pin Ceramic Flat Package. The choice of package is determined by the number of I/O pins and the geometry of the chip. 24 pins are enough to allocate the inputs, outputs, and power connections for the proposed circuits. The dimension of the package also impacts

83 Chapter 6. Fabrication and Testing of the Proposed Circuits 71 of the design of the test board. The technical drawing of the package is shown in Fig Figure 6.8: Technical drawing of the 24-pin CFP package, Spectrum Semiconductor Materials, Inc. 6.5 Test board design To test the package chip, a printed circuit board (PCB) needs to be designed to mount the chip and connect it to the testing equipment. The design of the testing board should consider the types of measurements to be performed and all the necessary connections

84 Chapter 6. Fabrication and Testing of the Proposed Circuits 72 to the equipment. The board was designed using EAGLE PCB-Design, considering the exact dimensions of the package and off-chip components to perform the desired tests. The layout of the PCB board is shown in Fig Figure 6.9: Layout of the PCB. A one layer FR4 dielectric test board was fabricated and shown in Fig The input clock and power supplies are connected through SMA (SubMiniature version A) connectors for better measurement results and stability. Test points are soldered to the through holes for easily placing and connecting wires and capacitors. A Schmitt trigger circuit is mounted to sharpen the clock edges for a better clock generation, and a clock divider circuit is used to generate low frequency pulses for transient tests. The packaged chip was placed in a central recess and clamped using a translucent plastic clamp. Figure 6.10: The fabricated PCB board with test chip and auxiliary circuits.

85 Chapter 6. Fabrication and Testing of the Proposed Circuits Bench test setup The bench test setup is shown in Fig A BK Precision 4040A function generator generates the external clock signal for the charge pumps. The power supply for the phase generator, drivers and charge pump is provided by a Keithley 2602 source meter, which can generate a very precise DC voltage while measuring the supplied current. The charge pump outputs are also connected the source meter to measure the output voltages under different load currents. Test scripts are developed to automate the operations of the Keithley 2602 source meter. The transient behaviours of the charge pumps can be captured by a Tektronix DPO7104 digital oscilloscope. Two Agilent E3630A DC power supplies are used to generate reference voltages and provide power for the auxiliary circuits (VCO, op-amp, Schmitt trigger and clock divider). Data analysis Charge pump input Clock Charge pump output Keithley Source Meter Test Board Reference voltage and power supply for auxiliary circuits Function Generator Oscilloscope DC Power Supply Figure 6.11: Block diagram of the characterization setup.

86 Chapter 7 Measurement Results 7.1 Introduction The circuits simulated in Chapter 5 are implemented on silicon. Bench tests are conducted on the fabricated chip using the test setup described in chapter 6. Both of the steady state and transient performances are measured and compared with the simulation results. 7.2 Steady state measurements Output voltage characteristics and conversion efficiencies are measured in steady-state conditions. The measurements are compared with the simulation results Unregulated 2-stage single-branch PMOS charge pump The unregulated 2-stage single-branch PMOS charge pump is tested to evaluate its steady state characteristics. Fig. 7.1 and Fig. 7.2 present the simulation and measurement output voltage characteristics and conversion efficiencies as a function of load current at 1 MHz and 10 MHz at room temperature. 74

87 Chapter 7. Measurement Results 75 Figure 7.1: Measurement and simulation output voltage characteristics and conversion efficiencies of the unregulated 2-stage single-branch PMOS charge pump, with f = 1 MHz, C T = 500 pf, α = 1.5% and β = 1.2%. Figure 7.2: Measurement and simulation output voltage characteristics and conversion efficiencies of the unregulated 2-stage single-branch PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2%.

88 Chapter 7. Measurement Results 76 Table 7.1: Key performance parameters of the unregulated 2-stage single-branch PMOS charge pump from measurement f Type Maximum V O R O Peak η 1 MHz Simulation 5.34 V Ω 78.1% 1 MHz Measurement 5.31 V Ω 77.9% 10 MHz Simulation 5.35 V Ω 79.5% 10 MHz Measurement 5.31 V Ω 77.3% The key performance parameters of the simulation and theoretical results are summarized in Table 7.1. The measurement results are in good agreement with the simulation results. The charge pump can generate a maximum output voltage of 5.31 V. Compared to the conventional bootstrapped PMOS charge pump which has a theoretically best peak efficiency of 75%, the proposed designs have better efficiencies, where the peak is at 78%. This result is as expected since the proposed clock scheme eliminates the charge loss through the bootstrapping capacitors Unregulated 2-stage voltage-doubler PMOS charge pump The unregulated 2-stage voltage-doubler PMOS charge pump is tested to evaluate its steady state performance. Fig. 7.3 and Fig. 7.4 present the simulation and measurement output voltage characteristics and conversion efficiencies as a function of load current at 1 MHz and 10 MHz at room temperature. Table 7.2: Key performance parameters of the unregulated 2-stage voltage-doubler pmos charge pump from measurement f Type Maximum V O R O Peak η 1 MHz Simulation 5.34 V Ω 78.1% 1 MHz Measurement 5.36 V 7956 Ω 78.3% 10 MHz Simulation 5.35 V Ω 79.5% 10 MHz Measurement 5.36 V Ω 79.2% The key performance parameters of the simulation and theoretical results are summarized in Table 7.2. The measurement results are very close to the simulations. The charge pump can generate a maximum output voltage of 5.36 V.

89 Chapter 7. Measurement Results 77 Figure 7.3: Measurement and simulation output voltage characteristics and conversion efficiencies of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 1 MHz, C T = 500 pf, α = 1.5% and β = 1.2%. Figure 7.4: Measurement and simulation output voltage characteristics and conversion efficiencies of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2%.

90 Chapter 7. Measurement Results Regulated 2-stage PMOS charge pumps This section presents the steady state measurement results of the regulated 2-stage singlebranch and voltage-doubler charge pumps in Fig. 7.5 and Fig The measurement results are consistent with the simulation results. The output voltages of both charge pumps start to drop when load current is about 1.7 ma, which matches with the simulations. Figure 7.5: Measurement and simulation output voltage characteristics and conversion efficiencies of the regulated 2-stage single-branch PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2%.

91 Chapter 7. Measurement Results 79 Figure 7.6: Measurement and simulation output voltage characteristics and conversion efficiencies of the regulated 2-stage voltage-doubler PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2% stage and 6-stage double-ladder PMOS charge pumps The steady state performance of the charge pumps from measurements are compared with the simulation results and shown in Figs. 7.7, 7.8, 7.9, and The key charge pump performance parameters are summarized in the table below. The output resistance are calculated before the switches start to introduce additional voltage loss. The output resistances extracted from measurement results are slightly better than the simulations possibly due to the bigger β after fabrication. The charge pumps are able to generate maximum output voltages of 8.66 V and V for the 4-stage and 6-stage charge pump. Only low-voltage devices are used in the CW charge pumps, the maximum output voltages are much higher than the oxide and junction breakdown voltages (5 to 6 V).

92 Chapter 7. Measurement Results 80 Table 7.3: Key performance parameters of the unregulated double-ladder PMOS charge pump from measurement N f Type Maximum V O R O Peak η 4 1 MHz Simulation 8.34 V KΩ 47.3% 4 1 MHz Measurement 8.59 V 178 KΩ 50.2% 4 10 MHz Simulation 8.36 V 20.2 KΩ 48.8% 4 10 MHz Measurement 8.66 V 17.4 KΩ 52.0% 6 1 MHz Simulation V KΩ 35.8% 6 1 MHz Measurement V KΩ 34.9% 6 10 MHz Simulation 10.8 V 57.9 KΩ 35.0% 6 10 MHz Measurement V 52.6 KΩ 35.4% Figure 7.7: Measurement and simulation output voltage characteristics and conversion efficiencies of the 4-stage double-ladder PMOS charge pump, with, f = 1 MHz, C T = 450 pf, α = 1.5% and β = 1.2%. From the presented plots, we can at once observe that the output voltages and conversion efficiencies from measurements rolls off earlier than the simulation results. The drops in output voltages indicate larger output resistances, because the transistor switches are not fully turned on and cause voltage loss. The primary reason is that the bootstrapping capacitors are connected in series, there is a voltage loss at each stage due to the parasitic capacitances. Although we have included the parasitic capacitances of the transistors and capacitors in the simulations, the fabrication introduces process variations and larger parasitics, thus the boosting voltages at last few stages may not have sufficient voltage for

93 Chapter 7. Measurement Results 81 Figure 7.8: Measurement and simulation output voltage characteristics and conversion efficiencies of the 4-stage double-ladder PMOS charge pump, with, f = 10 MHz, C T = 450 pf, α = 1.5% and β = 1.2%. Figure 7.9: Measurement and simulation output voltage characteristics and conversion efficiencies of the 6-stage double-ladder PMOS charge pump, with, f = 1 MHz, C T = 630 pf, α = 1.5% and β = 1.2%.

94 Chapter 7. Measurement Results 82 Figure 7.10: Measurement and simulation output voltage characteristics and conversion efficiencies of the 6-stage double-ladder PMOS charge pump, with, f = 10 MHz, C T = 630 pf, α = 1.5% and β = 1.2%. the switches to turn on, which causes the output voltage to drop. Because the CW charge pumps have high number of stages, they are more sensitive to the parasitic variations. The larger output resistance degrades the conversion efficiency due to the increased resistive loss. Moreover, we can see that the maximum voltages are higher than the simulations, one possible reason is that the channel charge of the transistors are injected to the stage capacitors to cause a voltage rise, and since the stage capacitors in the double-ladder charge pumps are much smaller and the switch sizes are relatively large, the channel charge injection causes the voltage to rise more significantly compared to the singlebranch and the voltage-doubler charge pumps, where the stage capacitors are much larger. This channel charge injection also causes the conversion efficiency to be better than the simulations. 7.3 Transient Measurements The start-up transients of the circuits are measured and shown in this section. The load capacitors are 1 nf and their initial conditions are set to be close to 0 V. The start-up

95 Chapter 7. Measurement Results 83 operations of the charge pumps are controlled by the enable signal. When the enable signal is on, the charge pumps output reaches its maximum with no load current, when the enable signal is off, charge pump stops working and the load capacitor is pulled closed to 0 V by a current sink. The output voltage is not completely 0 V, because the input power supply and the current sink are connected by parasitic diodes when enable signal is off. The start-up waveforms of the charge pumps are shown in this section stage unregulated PMOS charge pumps The start-up transients of the unregulated 2-stage single-branch and voltage-doubler PMOS charge pumps with 10 MHz input clock are shown in Fig and Fig The major vertical grid is 2 V per division and the horizontal grid is 2 µs per division. Figure 7.11: Start-up transient of the unregulated 2-stage single-branch PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2%.

96 Chapter 7. Measurement Results 84 Figure 7.12: Start-up transients of the unregulated 2-stage voltage-doubler PMOS charge pump, with f = 10 MHz, C T = 500 pf, α = 1.5% and β = 1.2%. The output voltage of the single-branch PMOS charge pump reaches 90% of its maximum voltage in 2.8 µs, and the output voltage of the voltage-doubler charge pump reaches 90% of its maximum voltage in about 2.6 µs. The measured start-up time of the two proposed 2-stage charge pumps are slower than the simulations due to the additional capacitances of the pads, testing board and equipment stage regulated PMOS charge pumps The start-up transients of the proposed regulated single-branch and voltage-doubler charge pumps are shown in Fig and Fig respectively. The single-branch and voltage-doubler charge pumps reach 4.2 V in 1.4 µs and 1.3 µs respectively, compared to 1.21 µs and 1.2 µs in the simulation. The major vertical grid is 2 V per division and the horizontal grid is 1 µs per division.

97 Chapter 7. Measurement Results 85 Figure 7.13: Start-up transient of the regulated 2-stage single-branch PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2%. Figure 7.14: Start-up transient of the regulated 2-stage voltage-doubler PMOS charge pump, with C T = 500 pf, α = 1.5% and β = 1.2%.

98 Chapter 7. Measurement Results stage and 6-stage double-ladder PMOS charge pumps The start-up transient of the 4-stage double-ladder PMOS charge pump under 10 MHz is shown in Fig The major vertical grid is 2 V per division and the horizontal grid is 50 µs per division. The start-up of the 6-stage double-ladder PMOS charge pump under 10 MHz is shown in Fig The major vertical grid is 5 V per division and the horizontal grid is 100 µs per division. The output voltage of the 4-stage double-ladder charge pump reaches 90% of its maximum voltage in 50 µs, and the output voltage of the 6-stage double-ladder charge pump reaches 90% of its maximum voltage in about 130 µs. To see how far we can extend the voltage range of the 6-stage charge pump, we set the input power supply to 2.4 V which is the beyond the suggested voltage rating for the transistors. The start-up waveform is shown in Fig The output can reach a maximum voltage of 14.9 V. Figure 7.15: Start-up transient of the 4-stage double-ladder PMOS charge pump, with f = 10 MHz, C T = 630 pf, α = 1.5% and β = 1.2%.

99 Chapter 7. Measurement Results 87 Figure 7.16: Start-up transient of the 6-stage double-ladder PMOS charge pump, with f = 10 MHz, C T = 450 pf, α = 1.5% and β = 1.2%. Figure 7.17: Start-up transient of the 6-stage double-ladder PMOS charge pump, with = 2.4 V, f = 10 MHz, C T = 450 pf, α = 1.5% and β = 1.2%.

100 Chapter 7. Measurement Results Conclusion This chapter presents the measurement results of the proposed circuits. The proposed unregulated 2-stage single-branch and voltage-doubler charge pumps work successfully with the clock boosting circuit and have performance close to the simulations. The voltage doubler has a better static characteristic and less output ripple than the single-branch charge pump at the expense of more complicated bootstrapping circuits. The regulated single-branch and voltage-doubler charge pumps also show results close to simulations and can successfully regulated the output voltages to constant voltage levels. The efficiencies of the regulated charge pumps are kept above 70%. The double-ladder charge pumps can successfully generate voltages as high as V (with = 1.8 V) reliably beyond the breakdown voltage limitations of the transistors and capacitors. The double-ladder charge pump is verified to work reliably even after one million cycles of start-up operations. The output voltage can reach 14.9 V with = 2.4 V. The static characteristics show degradations at high load current due to the insufficient boosted voltage of the switches. The problem can be resolved by sizing the switches and boosting capacitors according to the number of stages to reduce voltage loss. However, the main objective of designing the double-ladder charge pump is to generate high voltages using only low-voltage devices, which has been demonstrated by the measurements. The proposed double-ladder design is the first fabricated charge pump that can be integrated with the standard CMOS process and reach a voltage much larger than the suggested voltage rating. The measurement results are in good agreement with the simulations with small variations, which are possibly due to the process variations, unaccounted parasitics, and errors introduced by the equipment.

101 Chapter 8 Conclusion This dissertation presents the design and implementation of charge pumps using the PMOS switches to extend the output voltage range. By using the PMOS transistors and biasing their bulk, the maximum charge pump output voltage is not limited by the transistor breakdown voltages; this allows the designers to use low-voltage transistors for high voltage generations without triple well processes. A clock boosting circuit is also proposed to effectively drive the bootstrapped PMOS switches with only two clock phases. The proposed clock scheme prevents the charging and discharging action of the bootstrapping capacitors to improve charge pump performance. Three types of PMOS-based charge pumps are proposed. The proposed single-branch charge pump is implemented with intermediate voltage cells between stages to reduce the voltage stress of switches. As a result, we can use only low-voltage transistors instead how-voltage devices which need additional layout and fabrication steps. The proposed design also has improved performance and operating frequency range over the conventional designs at costs of additional devices and area. The proposed voltage-doubler charge pump uses cascode PMOS switches that are different from which in the single-branch charge pump. The use of PMOS switches extends the maximum charge pump output voltage range in a standard process. Only low-voltage transistors are used in the design. The voltage doubler also has better static and transient performance than the single branch charge pump because of the cascode bootstrapping PMOS switches. 89

102 Chapter 8. Conclusion 90 In the bootstrapped PMOS double-ladder charge pump, the stage capacitors and bootstrapping capacitors are connected in series so low-voltage MOS capacitors, which have large capacitances per area, can be used. The PMOS double-ladder charge pump is a complete solution to generate a higher DC voltage in a standard low-voltage CMOS digital process. The fabricated circuits were tested and demonstrated to generate voltages as high as V using low-voltage devices with voltage rating of 1.8 V. The proposed regulation circuit consists of a VCO, an op-amp and a voltage divider. The overall regulation scheme occupies a small fraction of the entire charge pump area. The regulated charge pump can produce a constant voltage and efficiency at different load currents. The output also does not experience any oscillation or overshoot under a sudden change of load current. A test chip, consisting of the proposed circuits, was fabricated in the TSMC 0.18-µm CMOS process. The functionality and performance of the proposed circuits are demonstrated and verified through experimental evaluations. The measurement results are in good agreement with the simulations.

103 Appendix A Testing A.1 Introduction This section describes the input and output connections for characterizing the fabricated chip. There are six charge pumps (CPs), on which static and transient measurements are conducted. Static tests are to measure the output voltage characteristics and conversion efficiencies as a function of load currents in steady state, and transient tests are to measure the start-up transients of the charge pumps. 91

104 Appendix A. Testing 92 A.2 Chip layout and pad arrangements V out3 V out6 V ss V ref En3 En6 3 6 V out2 V out5 En2 En5 2 5 V- CLK V ss 1 4 En1 En4 V out1 V out4 Figure A.1: Chip layout and pad arrangements.

105 Appendix A. Testing 93 A.3 Package bonding diagram V ss V out3 V out6 V ref En3 En6 3 6 V out2 V out5 En2 En5 2 5 V- V ss CLK 1 4 En1 V out1 V out4 En4 Figure A.2: Package bonding diagram.

106 Appendix A. Testing 94 A.4 Test board and input/output connections 6 3 V out6 V out3 V out2 5 V out5 En5 En6 V ref En3 En2 V- 2 Clock En4 En1 V out4 V out1 4 1 Figure A.3: PCB connections.

107 Appendix A. Testing 95 A.5 Pin and signal descriptions Table A.1: Pin descriptions Pin Name Type Voltage Description 1 InputOutput 0 V (off),1.8 V (on) Input supply voltage for CP1 2 InputOutput 0 V (off),1.8 V (on) Input supply voltage for CP2 3 InputOutput 0 V (off),1.8 V (on) Input supply voltage for CP3 4 InputOutput 0 V (off),1.8 V (on) Input supply voltage for CP4 5 InputOutput 0 V (off),1.8 V (on) Input supply voltage for CP5 6 InputOutput 0 V (off),1.8 V (on) Input supply voltage for CP6 InputOutput 0 V (off),1.8 V (on) Power for phase and biases generators V SS InputOutput 0 V Global ground En1 Input 0 V (off),1.8 V (on) Enable signal for CP1 En2 Input 0 V (off),1.8 V (on) Enable signal for CP2 En3 Input 0 V (off),1.8 V (on) Enable signal for CP3 En4 Input 0 V (off),1.8 V (on) Enable signal for CP4 En5 Input 0 V (off),1.8 V (on) Enable signal for CP5 En6 Input 0 V (off),1.8 V (on) Enable signal for CP6 V InputOutput 0 V (off),0.9 V (on) Bias to adjust non-overlapping time V ref InputOutput 0 V (off),0.7 V (on) Voltage reference for regulators Clock Input V amp = 1.8 V Clock input for all CPs (1 to 20 MHz) V OUT 1 Output V OUT 1 Max = 5.4 V Output for CP1 V OUT 2 Output V OUT 1 Max = 12.6 V Output for CP2 V OUT 3 Output V OUT 1 Max = 4.2 V Output for CP3 V OUT 4 Output V OUT 1 Max = 9 V Output for CP4 V OUT 5 Output V OUT 1 Max = 5.4 V Output for CP5 V OUT 6 Output V OUT 1 Max = 4.2 V Output for CP6

108 Appendix A. Testing 96 A.6 Test setup for CP1 Table A.2: Pin assignments for static test of CP1 Pin Name Voltage Description V (on) Measure input power 2 0 V (off) CP2 is off 3 0 V (off) CP3 is off 4 0 V (off) CP4 is off 5 0 V (off) CP5 is off 6 0 V (off) CP6 is off 1.8 V Power up the phase generator V SS 0 V Global ground En1 1.8 V(on) Turn on CP1 En2 0 V (off) Turn off CP2 En3 0 V (off) Turn off CP3 En4 0 V (off) Turn off CP4 En5 0 V (off) Turn off CP5 En6 0 V (off) Turn off CP6 V 0.9 V Adjust non-overlapping time V ref 0 V Not used Clock V amp = 1.8 V (on) Frequency = 1 to 20 MHz V OUT 1 0 to 5.4 V Measure output voltage V OUT 2 0 V Grounded V OUT 3 0 V Grounded V OUT 4 0 V Grounded V OUT 5 0 V Grounded V OUT 6 0 V Grounded Table A.3: Pin assignments for transient test of CP1 Pin Name Voltage Description V (on) Power supply for CP1 2 0 V (off) CP2 is off 3 0 V (off) CP3 is off 4 0 V (off) CP4 is off 5 0 V (off) CP5 is off 6 0 V (off) CP6 is off 1.8 V Power up phase generator V SS 0 V Global ground En1 V setup (1.8 V) Apply a setup signal En2 0 V (off) Turn off CP2 En3 0 V (off) Turn off CP3 En4 0 V (off) Turn off CP4 En5 0 V (off) Turn off CP5 En6 0 V (off) Turn off CP6 V 0.9 V Adjust non-overlapping time V ref 0 V Not used Clock V amp = 1.8 V Frequency = 1 to 20 MHz V OUT 1 0 to 5.4 V Measure open circuit start-up transient V OUT 2 0 V Grounded V OUT 3 0 V Grounded V OUT 4 0 V Grounded V OUT 5 0 V Grounded V OUT 6 0 V Grounded

109 Appendix A. Testing 97 A.7 Test setup for CP2 Table A.4: Pin connections for static test of CP2 Pin Name Voltage Description 1 0 V (off) CP1 is off V (on) Measure the input power 3 0 V (off) CP3 is off 4 0 V (off) CP4 is off 5 0 V (off) CP5 is off 6 0 V (off) CP6 is off 1.8 V Power up phase generator V SS 0 V Global ground En1 0 V (off) Turn off CP1 En2 1.8 V(on) Turn on CP2 En3 0 V (off) Turn off CP3 En4 0 V (off) Turn off CP4 En5 0 V (off) Turn off CP5 En6 0 V (off) Turn off CP6 V 0.9 V Adjust non-overlapping time V ref 0 V Not used Clock V amp = 1.8 V Frequency = 1 to 20 MHz V OUT 1 0 V Grounded V OUT 2 0 to 12.6 V Measure output voltage V OUT 3 0 V Grounded V OUT 4 0 V Grounded V OUT 5 0 V Grounded V OUT 6 0 V Grounded Table A.5: Pin connections for transient test of CP2 Pin Name Voltage Description 1 0 V (off) CP1 is off V(on) Power supply for CP2 3 0 V (off) CP3 is off 4 0 V (off) CP4 is off 5 0 V (off) CP5 is off 6 0 V (off) CP6 is off 1.8 V Power up phase generator V SS 0 V Global ground En1 0 V (off) Turn off CP1 En2 V step (1.8 V) Apply a step signal En3 0 V (off) Turn off CP3 En4 0 V (off) Turn off CP4 En5 0 V (off) Turn off CP5 En6 0 V (off) Turn off CP6 V 0.9 V Adjust non-overlapping time V ref 0 V Not used Clock V amp = 1.8 V Frequency = 1 to 20 MHz V OUT 1 0 V Grounded V OUT 2 0 to 12.6 V Measure open circuit start-up transient V OUT 3 0 V Grounded V OUT 4 0 V Grounded V OUT 5 0 V Grounded V OUT 6 0 V Grounded

110 Appendix A. Testing 98 A.8 Test setup for CP3 Table A.6: Pin connections for static test of CP3 Pin Name Voltage Description 1 0 V (off) CP1 is off 2 0 V (off) CP2 is off V (on) Measure input power 4 0 V (off) CP4 is off 5 0 V (off) CP5 is off 6 0 V (off) CP6 is off 1.8 V Power up phase generator and regulation circuits V SS 0 V Global ground En1 0 V (off) Turn off CP1 En2 0 V (off) Turn off CP2 En3 1.8 V (on) Turn on CP3 En4 0 V (off) Turn off CP4 En5 0 V (off) Turn off CP5 En6 0 V (off) Turn off CP6 V 0.9 V Adjust non-overlapping time V ref 0.7 V Regulator reference voltage Clock 0 V Not used V OUT 1 0 V Grounded V OUT 2 0 V Grounded V OUT 3 0 to 4.2 V Measure output voltage V OUT 4 0 V Grounded V OUT 5 0 V Grounded V OUT 6 0 V Grounded Table A.7: Pin connections for transient test of CP3 Pin Name Voltage Description 1 0 V (off) CP1 is off 2 0 V (off) CP2 is off V (on) Power supply of CP3 4 0 V (off) CP4 is off 5 0 V (off) CP5 is off 6 0 V (off) CP6 is off 1.8 V Power up phase generators and regulation circuits V SS 0 V Global ground En1 0 V (off) Turn off CP1 En2 0 V (off) Turn off CP2 En3 1.8 V (on) Turn on CP3 En4 0 V (off) Turn off CP4 En5 0 V (off) Turn off CP5 En6 0 V (off) Turn off CP6 V 0.9 V Adjust non-overlapping time V ref 0.7 V Reference voltage Clock 0 V Not used V OUT 1 0 V keep at ground V OUT 2 0 V keep at ground V OUT 3 0 to 4.2 V Measure open circuit start-up transient V OUT 4 0 V keep at ground V OUT 5 0 V keep at ground V OUT 6 0 V keep at ground

111 Appendix A. Testing 99 A.9 Test setup for CP4 Table A.8: Pin connections for static test of CP4 Pin Name Voltage Description 1 0 V (off) CP1 is off 2 0 V (off) CP2 is off 3 0 V (off) CP3 is off V (on) Measure input power 5 0 V (off) CP5 is off 6 0 V (off) CP6 is off 1.8 V Power up phase generator V SS 0 V Global ground En1 0 V (off) Turn off CP1 En2 0 V (off) Turn off CP2 En3 0 V (off) Turn off CP3 En4 1.8 V(on) Turn on CP4 En5 0 V (off) Turn off CP5 En6 0 V (off) Turn off CP6 V 0.9 V Adjust non-overlapping time V ref 0 V Not used Clock V amp = 1.8 V Frequency = 1 to 40 MHz V OUT 1 0 V Grounded V OUT 2 0 V Grounded V OUT 3 0 V Grounded V OUT 4 0 to 9 V Measure output voltage V OUT 5 0 V Grounded V OUT 6 0 V Grounded Table A.9: Pin connections for static test of CP4 Pin Name Voltage Description 1 0 V (off) CP1 is off 2 0 V (off) CP2 is off 3 0 V (off) CP3 is off V (on) Power supply of CP4 5 0 V (off) CP5 is off 6 0 V (off) CP6 is off 1.8 V Power up phase generator V SS 0 V Global ground En1 0 V (off) Turn off CP1 En2 0 V (off) Turn off CP2 En3 0 V (off) Turn off CP3 En4 V step (1.8 V) Apply a step signal En5 0 V (off) Turn off CP5 En6 0 V (off) Turn off CP6 V 0.9 V Adjust non-overlapping time V ref 0 V Not used Clock V amp = 1.8 V Frequency = 1 to 20 MHz V OUT 1 0 V Grounded V OUT 2 0 V Grounded V OUT 3 0 V Grounded V OUT 4 0 to 9 V Measure open circuit start-up transient V OUT 5 0 V Grounded V OUT 6 0 V Grounded

112 Appendix A. Testing 100 A.10 Test setup for CP5 Table A.10: Pin connections for static test of CP5 Pin Name Voltage Description 1 0 V (off) CP1 is off 2 0 V (off) CP2 is off 3 0 V (off) CP3 is off 4 0 V (off) CP4 is off V (on) Measure input power 6 0 V (off) CP6 is off 1.8 V Power up phase generator V SS 0 V Global ground En1 0 V (off) Turn off CP1 En2 0 V (off) Turn off CP2 En3 0 V (off) Turn off CP3 En4 0 V (off) Turn off CP4 En5 1.8 V(on) Turn on CP5 En6 0 V (off) Turn off CP6 V 0.9 V Adjust non-overlapping time V ref 0 V Not used Clock V amp = 1.8 V Frequency = 1 to 40 MHz V OUT 1 0 V Grounded V OUT 2 0 V Grounded V OUT 3 0 V Grounded V OUT 4 0 V Grounded V OUT 5 0 to 5.4 V Measure output voltage V OUT 6 0 V Grounded Table A.11: Pin connections for static test of CP5 Pin Name Voltage Description 1 0 V (off) CP1 is off 2 0 V (off) CP2 is off 3 0 V (off) CP3 is off 4 0 V (off) CP4 is off V (on) Power supply of CP5 6 0 V (off) CP6 is off 1.8 V Power up phase generator V SS 0 V Global ground En1 0 V (off) Turn off CP1 En2 0 V (off) Turn off CP2 En3 0 V (off) Turn off CP3 En4 0 V (off) Turn off CP4 En5 V step (1.8 V) Apply a step signal En6 0 V (off) Turn off CP6 V 0.9 V Adjust non-overlapping time V ref 0 V Not used Clock V amp = 1.8 V Frequency = 1 to 20 MHz V OUT 1 0 V Grounded V OUT 2 0 V Grounded V OUT 3 0 V Grounded V OUT 4 0 V Grounded V OUT 5 0 to 5.4 V Measure open circuit start-up transient V OUT 6 0 V Grounded

113 Appendix A. Testing 101 A.11 Test setup for CP6 Table A.12: Pin connections for static test of CP6 Pin Name Voltage Description 1 0 V (off) CP1 is off 2 0 V (off) CP2 is off 3 0 V (off) CP3 is off 4 0 V (off) CP4 is off 5 0 V (off) CP5 is off V (on) Measure input power from V Power up phase generator and regulation circuits V SS 0 V Global ground En1 0 V (off) Turn off CP1 En2 0 V (off) Turn off CP2 En3 0 V (off) Turn off CP3 En4 0 V (off) Turn off CP4 En5 0 V (off) Turn off CP5 En6 1.8 V (on) Turn on CP6 V 0.9 V Adjust non-overlapping time V ref 0.7 V Regulator reference voltage Clock 0 V Not used V OUT 1 0 V Grounded V OUT 2 0 V Grounded V OUT 3 0 V Grounded V OUT 4 0 V Grounded V OUT 5 0 V Grounded V OUT V Measure output voltage. Table A.13: Pin connections for transient test of CP6 Pin Name Voltage Description 1 0 V (off) CP1 is off 2 0 V (off) CP2 is off 3 0 V (off) CP3 is off 4 0 V (off) CP4 is off 5 0 V (off) CP5 is off V (on) Measure input power from V Power up phase generator and regulation circuits V SS 0 V Global ground En1 0 V (off) Turn off CP1 En2 0 V (off) Turn off CP2 En3 0 V (off) Turn off CP3 En4 0 V (off) Turn off CP4 En5 0 V (off) Turn off CP5 En6 1.8 V (on) Turn on CP6 V 0.9 V Adjust non-overlapping time V ref 0.7 V Regulator reference voltage Clock 0 V Not used V OUT 1 0 V Grounded V OUT 2 0 V Grounded V OUT 3 0 V Grounded V OUT 4 0 V Grounded V OUT 5 0 V Grounded V OUT 6 0 to 4.2 V Measure open circuit start-up transient

114 Appendix B Schematics B.1 Schematic of the V+ Voltage Generation Circuit Figure B.1: Schematic of the V+ voltage generation circuit to adjust non-overlapping time of the phase generator. 102

115 Appendix B. Schematics 103 B.2 Schematic of the phase generator Figure B.2: Schematic of the phase generator.

116 Appendix B. Schematics 104 B.3 Schematic of the clock boosting circuit Figure B.3: Schematic of the clock boosting circuit.

117 Appendix B. Schematics 105 B.4 Schematic of the 2-stage single branch charge pump Figure B.4: Schematic of the 2-stage single branch charge pump.

118 Appendix B. Schematics 106 B.5 Schematic of the 2-stage voltage-doubler charge pump Figure B.5: Schematic of the 2-stage voltage-doubler charge pump.

119 Appendix B. Schematics 107 B.6 Schematic of the 4-stage doubler-ladder Charge pump Figure B.6: Schematic of the 4-stage double-ladder charge pump.

120 Appendix B. Schematics 108 B.7 Schematic of the 6-stage doubler-ladder charge pump Figure B.7: Schematic of the 6-stage double-ladder charge pump.

121 Appendix B. Schematics 109 B.8 Schematic of the voltage controlled ring oscillator Figure B.8: Schematic of the voltage controlled ring oscillator.

122 Appendix B. Schematics 110 B.9 Schematic of the op-amp and voltage divider Figure B.9: Schematic of the op-amp and voltage divider.

123 Appendix C Layout C.1 Layout of the V+ voltage generation circuit Figure C.1: Layout of the V+ voltage generation circuit to adjust non-overlapping time of the phase generator. 111

124 Appendix C. Layout 112 C.2 Layout of the phase generator and clock boosting Circuit Figure C.2: Layout of the phase generator and clock boosting circuit.

125 Appendix C. Layout 113 C.3 Layout of the 2-stage single branch charge pump Figure C.3: Layout of the 2-stage single branch charge pump.

126 Appendix C. Layout 114 C.4 Layout of the 2-stage voltage-doubler charge pump Figure C.4: Layout of the 2-stage voltage-doubler charge pump.

127 Appendix C. Layout C Layout of the 4-stage doubler-ladder charge pump Figure C.5: Layout of the 4-stage double-ladder charge pump.

128 Appendix C. Layout 116 C.6 Layout of the 6-stage doubler-ladder charge pump Figure C.6: Layout of the 6-stage double-ladder charge pump.

129 Appendix C. Layout 117 C.7 Layout of the voltage controlled ring oscillator Figure C.7: Layout of the voltage-controlled ring oscillator. C.8 Layout of the op-amp and voltage divider Figure C.8: Layout of the op-amp and voltage divider.

130 Appendix C. Layout 118 C.9 Layout of the regulated 2-stage single branch charge pump Figure C.9: Layout of the regulated 2-stage single branch charge pump.

131 Appendix C. Layout 119 C.10 Layout of the regulated 2-stage voltage-doubler charge pump Figure C.10: Layout of the regulated 2-stage voltage-doubler charge pump.