Chapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Transcription

1 Chapter 6 Combinational CMOS Circuit and Logic Design Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

2 Outline Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Advanced CMOS Logic Design I/O Structures

3 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 Pseudo-NMOS Logic A pseudo-nmos inverter A β p β n F V DD V L The low output voltage can be calculated as β P β n ( V DD V tn ) V L = ( V DD V tp 2 for V tn = Vtp = Vt β P V L = ( V DD V T ) 2 β n Thus V L depends strongly on the ratio The logic is also called ratioed logic ) 2 Time β p / β n

4 Pseudo-NMOS Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 An N-input pseudo-nmos gate V out inputs NMOS network Features of pseudo-nmos logic Advantages Low area cost only N+1 transistors are needed for an N- input gate Low input gate-load capacitance C gn Disadvantage Non-zero static power dissipation

5 Pseudo-NMOS XOR Gate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 An example of XOR gate realized with pseudo- NMOS logic The XOR is defined by Y = X + 1 X 2 = X1 X 2 + X1X 2 = X1X 2 + X1 X 2 = X1X 2 + X1 X 2 Y X 1 X 2

6 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6 Goals Noise margin Power consumption Speed Noise margin It is affected by the low output voltage (V L ) V L is determined by β / Speed Choosing Transistor Sizes p β n The larger the W/L of the load transistor, the faster the gate will be, particularly when driving many other gates Unfortunately, this increases the power dissipation and the area of the driver network

7 Choosing Transistor Sizes Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7 Power dissipation A pseudo-nmos logic gate having a 1 output has no static (DC) power dissipation. However, a pseudo-nmos gate having a 0 output has a static power dissipation The static power dissipation is equal to the current of the PMOS load transistor multiplied by the power supply voltage. Thus, the power is given by P dc pc = µ 2 The large PMOS results in large power dissipation Power-reduction methods ox W ( L Select an appropriate PMOS Increase the bias voltage of PMOS ) P ( V gs V tp 2 ) V dd

8 Choosing Transistor Sizes Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8 A simple procedure for choosing transistor sizes of pseudo-nmos logic gates The relative size (W/L) of the PMOS load transistor is chosen as a compromise between speed and size versus power dissipation Once the size of the load transistor has been chosen, then a simple procedure can be used to choose the W/Ls of the NMOS transistors in the NMOS network Let (W/L) eq be equal to one-half of the W/L of the PMOS load transistor For each transistor Q i, determine the maximum number of drive transistors it will be in series, for all possible inputs. Denote this number n i. Take (W/L) i =n i (W/L)eq

9 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9 An Example Choose appropriate sizes for the pseudo-nmos logic gate shown below (W/L) 8 is 5 um/0.8 um (W/L) eq is (5/0.8)/2=3.125 Gate lengths of drive transistors are taken at their minimum 0.8um Q Thus we can obtain 8 5/0.8 Transistor Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Size 2.5um/0.8um 7.5um/0.8um 7.5um/0.8um 10um/0.8um 10um/0.8um 10um/0.8um 10um/0.8um X 1 X 2 X 4 Q 1 Q 2 Q 4 X 5 X 3 X 6 Q 3 Q 6 X 7 Q 5 Q 7 Y

10 Dynamic Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10 To eliminate the static power dissipation of pseudo-nmos logic An alternative technique is to use dynamic precharging called dynamic logic as shown below PR V out inputs NMOS network Normally, during the time the output is being precharged, the NMOS network should not be conducting This is usually not possible

11 Dynamic Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11 Another dynamic logic technique V out inputs NMOS network CLK Precharge Evaluate CLK Two-phase operation: precharge & evaluate This can fully eliminate static power dissipation

12 Examples of Dynamic Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12 Two examples clk C Z=(A+B).C clk A B Y=ABC A B C clk clk

13 Problems of Dynamic Logic Two major problems of dynamic logic Charge sharing Simple single-phase dynamic logic can not be cascaded Charge sharing clk=1 A B C C 1 C 2 C 1 C 2 C A C charge sharing model CVDD = ( C + C1+ C2) V C VA = VDD C+ C + C 1 2 E.g., if C1 = C2 = 0.5C A clk=1 then output voltage is V DD /2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

14 Problems of Dynamic Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14 Simple single-phase dynamic logic can not be cascaded clock N 1 N 2 N1 inputs N Logic N Logic T d1 clock N 2 Erroneous State T d2

15 CMOS Domino Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15 Domino logic can be cascaded The basic structure of domino logic V out inputs NMOS network CLK Some limitations of this structure Each gate must be buffered Only noninverting structures are possible

16 A Domino Cascade Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16 An example of cascaded domino logics Stage 1 Stage 2 Stage 3 V out NMOS network NMOS network NMOS network CLK precharge evaluate

17 Charge-Keeper Circuits Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17 The domino cascade must have an evaluation interval that is long enough to allow every stage time to discharge This means that charge sharing and charge leakage processes that reduce the internal voltage may be limiting factors Two types of modified domino logics can cope with this problem Static version Latched version

18 Charge-Keeper Circuits Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18 Modified domino logics Weak PMOS Weak PMOS Z Z Inputs N-logic Inputs N-logic Block Block Clk Clk Static version Latched version The aspect ratio of the charge-keeper MOS must be small so that it does not interfere with discharge event

19 Complex Domino Gate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19 In a complex domino gate, intermediate nodes have been provided with their own precharge transistor N-logic F N-logic N-logic N-logic CLK

20 Multiple-Output Domino Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20 Multiple-output domino logic (MODL) allows two or more outputs from a single logic gate The basic structure of MODL A B F 1 F 2 CLK

21 A Multiple-Output Domino Logic Gate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21 F 1 D D F 2 A B C D A B C C C C C B B B B F 3 A B A A CLK

22 NP Domino Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22 A further refinement of the domino logic is shown below The domino buffer is removed, while cascaded logic blocks are alternately composed of P- and N- transistors CLK -CLK CLK N-logic P-logic N-logic Other P blocks Other N blocks

23 NP Domino Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23 NP domino logic with multiple fanouts Other N blocks Other P blocks CLK -CLK CLK N-logic P-logic N-logic Other P blocks Other N blocks

24 Advanced CMOS Logic Design Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24 Pass-Transistor Logic

25 Pass-Transistor Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25 Model for pass transistor logic Control signals P i Pass signals V i Product term (F) The product term F=P 1 V 1 +P 2 V 2 + +P n V n The pass variables can take the values {0,1,X i,-x i,z}, where X i and X i are the true and complement of the ith input variable and Z is the high-impedance

26 Pass-Transistor Logics Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26 Different types of pass-transistor logics for twoinput XNOR gate implementation -B B A -A OUT -B B -A A OUT A B OUT A Complementary Single-polarity Cross-coupled

27 Full-Swing Pass-Transistor Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27 Modifying NMOS pass-transistor logic so fulllevel swings are realized B Y A Adding the additional PMOS has another advantages It adds hysteresis to the inverter, which makes it less likely to have glitches

28 Differential Logic Design Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28 Features of the differential logic design Logic inversions are trivially obtained by simply interchanging wires without incurring a time delay The load networks will often consist of two crosscoupled PMOS only. This minimizes both area and the number of series PMOS transistors Disadvantage Two wires must be used to represent every signal, the interconnect area can be significantly greater. In applications in which only a few close gates are being driven, this disadvantage is often not as significant as the advantages Thus differential logic circuits are often a preferable consideration

29 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29 A Fully Differential Logic Circuit One simple and popular approach for realizing differential logic circuit is shown below The inputs to the drive network come in pairs, a singleended signal and its inverse The NMOS network can be divided into two separate networks, one between the inverting output and ground, and a complementary network between the noninverting output and ground V 1 V 1 V n V n V out Fully Differential NMOS Network V out +

30 Examples Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30 Differential CMOS realizations of AND and OR functions AB AB A+B A+B A A B A B A B B

31 Examples Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31 Differential CMOS realization of the function V out =(A+B )C+A E V out V out C E A E A B A B C A

32 Differential Split-Level Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32 Differential split-level (DSL) logic A variation of fully differential logic A compromise between a cross-coupled load with no d.c. power dissipation and a continuously-on load with d.c. power dissipation V out - V out + V ref V ref V 1 V 1 V n V n V - V + Differential NMOS Network

33 Differential Split-Level Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33 Features of DSL logic The loads have some of the features of both continuous loads and cross-coupled load Both outputs begin to change immediately The loads do have d.c. power dissipation, but normally much less than pseudo-nmos gates and dynamic power dissipation The nodes V+, V-, and all internal nodes of the NMOS network have voltage changes between greater than 0V and V ref -V tn This reduced voltage swing increases the speed of the logic gates The maximum drain-source voltage across the NMOS transistors is reduced by about one-half This greatly minimizes the short-channel effects

34 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34 Differential Pass-Transistor Logic It is not necessary to wait until one side goes to low before the other side goes high Pass-transistor networks for most required logic functions exist in which both sides of the crosscoupled loads are driven simultaneously This minimizes the time from when the inputs changes to when the low-to-high transition occurs V 1 V 1 V n V n V out Pass-Transistor Network V out +

35 Differential Pass-Transistor Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35 Other features of pass-transistor logic It removes the ratio requirements on the logic and has guaranteed functionality The cross-coupled loads restore signal levels to full V dd levels, thereby eliminating the voltage drop Examples: AB AB A+B A+B A - A + A - A + A + A - A + A - B - B + B - B +

36 Dynamic Differential Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36 A differential Domino logic gate CLK V out - V out + V 1 V 1 V n V n Differential NMOS Network CLK

37 Dynamic Differential Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37 Features of dynamic Domino logic Its d.c. power dissipation is very small, whereas its its speed still quite good Because of the buffers at the output, its output drive capability is also very good One of major limitations of Domino logic, the difficulty in realizing inverting functions, is eliminated because of the differential nature of the circuits

38 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38 Dynamic Differential Logic When the fan-out is small, the inverters at the output can be eliminated and the inputs to the charge-keeper transistors can be taken from the opposite output CLK V out - V out + V 1 V 1 V n V n Differential NMOS Network CLK

39 Dynamic Differential Logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39 Dynamic differential logics without chargekeeper circuit (abcd)=(0000) -Q clock Q -Q clock Q -d d -d d Differential Inputs clock nmos Combinational Network c -c -c b -b b -b c a -a clock Clocked version A 4-way XOR gate

40 Clocked CMOS (C 2 MOS) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40 Structure of a C 2 MOS gate Ideally, clocks are non-overlapping CLK X CLK=0 CLK=1, f is valid CLK=0, the output is in a high-impedance state. During this time interval, the output voltage is held on C out PMOS CLK CLK Network NMOS Network C out + - f V out

41 Examples of C 2 MOS Logic Gates Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41 B A B CLK A AB CLK CLK A+B A C out CLK B B A C out

42 The Drawback of C 2 MOS Logic Gates The problem of charge leakage Cause that the output node cannot hold the charge on V out very long The basics of charge leakage are shown below V(t) CLK=1 i p V dd V 1 i out V X i out CLK=0 = i n dv i p i = C = C out out dt out dv dt i n Assume i out is a constant I L C out + V out - Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42 0 V ( t ) t I L dv = dt V t = V V ( ) C out I L V ( t h ) = V 1 t h = V X C out C out t h = ( V 1 V X ) I L t h t I C L out t

43 I/O Pads Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43 Types of pads V dd, V ss pad Input pad (ESD) Output pad (driver) I/O pad (ESD+driver) All pads need guard ring for latch-up protection Core-limited pad & pad-limited pad Core-limited pad Pad-limited pad PAD PAD I/O circuitry I/O circuitry

44 ESD Protection Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44 Input pad without electrostatic discharge (ESD) protection PAD Assume I=10uA, C g =0.03pF, and t=1us The voltage that appears on the gate is about 330volts Input pad with ESD protection PAD

45 Tristate & Bidirectional Pads Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45 Tristate pad output-enable OE P OUT N data D Bidirectional pad PAD OE D N X P OUT Z 0 1 PAD

46 Schmitt Trigger Circuit Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46 Voltage transfer curve of Schmitt circuit V out V DD V T- V T+ V DD V in Hysteresis voltage V H =V T+ -V T- When the input is rising, it switches when V in =V T+ When the input is falling, it switches when V in =V T-

47 Schmitt Trigger Circuit Voltage waveform for slow input V out V DD V in V T+ V T- Time Schmitt trigger turns a signal with a very slow transition into a signal with a sharp transition Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47

48 Schmitt Trigger Circuit Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48 A CMOS version of the Schmitt trigger circuit V DD P 1 P 2 V FP P 3 V in V out N 2 V FN N 1 N 3 When the input is rising, the V GS of the transistor N 2 is given by When V, N 2 enters in conduction mode which means GS2 = Vin VFN Then V in V = T+ V GS2 = V Tn V FN = VT + V Tn

49 Summary Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 49 The following topics have been introduced in this chapter CMOS Logic Gate Design Advanced CMOS Logic Design Clocking Strategies I/O Structures