ECE626 Project Switched Capacitor Filter Design

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1 ECE626 Project Switched Capacitor Filter Design Hari Prasath Venkatram Contents I Introduction 2 II Choice of Topology 2 III Poles and Zeros 2 III-ABilinear Transform IV Dynamic Range and Chip Area Scaling 5 V Cascade of Biquads 1 V-A Linear Section V-B High-Q section V-C Low-Q section V-D Opamp-Macro-Model VI Charge Injection and Switches 15 VI-ASwitch Sizing VI-BCharge Injection VI-CChoice of W L VI-DChoice of Switch VI-E Harmonic Distortion VI-F Clock-Generator VIIOffset 2 VII-AFirst Order Stage VII-BBiquad Low Q - Stage VII-CHigh-Q Biquad Stage VII-DFilter Offset Voltage VIIISlew-Rate 22 IX Finite Gain 24 X CDS 27 XI Finite Bandwidth 27 XIIOpamp Design 31

2 I. Introduction The Low pass switched-capacitor filter design is discussed. The first section discusses the choice of topology to achieve the filter specification with minimum components and in a most economical way. Second section discusses about the derivation of H(z) and the location of poles and zeroes in z-domain. Section three discusses about dynamic range scaling and area scaling performed on this filter. Section four discusses about the macro-model implementation of the filter. Section five discusses about the various non-ideal effects in the switched-capacitor filter. Section six discusses the choice of opamptopology and the design of the opamp stage. Section seven concludes the report. The specification for the low-pass filter is II. Choice of Topology Parameter Sampling Frequency DC Gain Passband Ripple in Passband Stopband Gain in Stopband Minimum Capacitor Value 1 MHz db -5 MHz.2 db 1-5 MHz -5 db.5 pf The order of Butterworth filter required to meet this specification is 11. The order of Chebyshev filter required to meet this specification is 6. The order of Elliptic filter required to meet this specification is 5. The most economical filter is elliptic filter. III. Poles and Zeros The Bilinear transform is used for the design of sampled-data filter from the analog counterpart. The bilinear transform relationship between s domain and z domain is Ω s = 2 T tan(ωt 2 ) This translates to the following pass-band and stop-band specification for the analog 5 th order elliptic filter. Sampling frequency is 1 MHz. Ω pass Ω stop = 2 tan( π 2 ) Mrad/s = 2 tan( π 1 ) Mrad/s To give some margin, the filter was designed for.1 db passband ripple and 51 db stopband attenuation. The transfer function of the fifth order s domain filter is H(s) =.3465s 4.931s s s 4.79s s s The magnitude and phase response of the fifth order continuous-time elliptic filter is shown below. The pole-zero map in s domain and z-plane are shown in the following figures. The transfer function of the fifth order elliptic filter as a cascade of linear and biquad sections is given below.

3 Magnitude in db Phase in radians th Order Elliptic Filter in s domain Normalized Frequency axis in rad/s Fig th Order Elliptic Filter in s domain Normalized Frequency axis in rad/s

4 Pole Zero Map Imaginary Axis Fig. 2. Pole-Zero in s domain Real Axis

5 A. Bilinear Transform Trapezoidal intergration is a better approximation in integration. This approximation is used to derive the bilinear s-to-z transformation. s a = 2 T z 1 z 1 This mapping was used to map s-domain poles to z-domain poles. The following tabular column lists the s-domain and z-domain poles. The s-domain poles are normalized to 2/T. Poles & Zeros s-domain z-domain p 1, ±.1695i.975±.31699i p 3, ±.1179i.8513±.2455i p z 1,2 ±.4337i.68334±.739i z 3,4 ±.2833i.85133±.52462i z 5-1 The quality factor of s-domain poles are 4.2 and 1 respectively for the two complex poles. The pole and zero closer to each other were used for forming the biquadratic section. The z-domain transfer function is H(z) =.3286z5.68z z z 2.68z.3286 z z z z z.5828 The frequency response of the z-domain filter is shown in the following figure. The fifth-order transfer function was designed as a cascade of a linear section and two second order sections. The transfer functions of the linear and second order sections are given below. The poles and zeros closer to each were used to form the biquadratic section. z 1 H 1 (z) =.1486 z z z 1 H 2 (z) =.1486 z z z z 1 H 3 (z) =.1486 z z IV. Dynamic Range and Chip Area Scaling The dynamic range scaling is performed to maximize the swing at each node of the filter. This is performed by scaling the capacitors connected to the output of each opamp by peak gain of the corresponding stage with respect to the input. All the capacitors that are either switched or connected permanently to the output of the opamp is scaled by this factor. [1] After performing dynamic range scaling for each output node, area scaling is performed at the input terminal of each opamp. The smallest capacitor connected to the input of the opamp is scaled such that, after scaling it has the minimum capacitor size. This order does not affect the dynamic range scaling. Therefore, Dynamic range scaling is performed first and area scaling performed after dynamic range scaling. The filter output before dynamic-range scaling is shown in the figure. 5 The dyamic range scaled output is shown in the figure. 6

6 Magnitude (db) Phase (degrees) Normalized Frequency ( π rad/sample) th Order z domain Elliptic Filter using Bilinear Transform Fig th Order Elliptic Filter in z domain Normalized Frequency ( π rad/sample)

7 Imaginary Part Z Domain Pole Zero Map Real Part Fig. 4. Pole-Zero in z domain

8 1.8 Individual Responses before DR Scaling Magnitude v oi vi x 1 6 Fig. 5. Magnitude Response before Dynamic-Range Scaling Frequency in Hertz(Hz) x 1 7

9 Dynamic Range Scaled Ouput Magnitude v oi vi x 1 6 Fig. 6. Dynamic Range Scaled Output Frequency in Hertz(Hz) x 1 7

10 V. Cascade of Biquads A linear section and two biquadratic sections were used for simulating the z-domain transfer function. Since one of the poles has a Quality factor of 4.2, a high-q biquad structure was used for this section. The following section explains the transfer function and the macro-model level implementation. The first section is a low-pass filter to reject high frequency noise. The high-q structure is placed in the middle. This order was chosen to reduce sensitivity to power supply noise and fundamental noise. A. Linear Section The linear section was implemented as follows [2]. z 1 H 1 (z) =.1486 z The Linear section was implemented with the following structure. The dynamic range scaled and area scaled capacitor values are shown in the figure 7. B. High-Q section The high-q biquad was used for the pole with quality factor of 4.2. The transfer function implemented using this structure is shown in the figure 8 [2]. H 2 (z) =.1486 z z 1 z z The amount of capacitance spread is higher in a low-q structure. This is because of the fact that the large damping resistor Q ω. This can be eliminated in the high-q structure. The general transfer function for the high-q biquad is as follows. H 3 (z) = (K 3)Z 2 (K 1 K 5 K 2 K 5 2K 3 )z (K 3 K 2 K 5 ) (1)z 2 (K 4 K 5 K 6 K 5 2)z (1 K 5 K 6 ) The above two expressions were compared to derive the values of K i. Dynamic range scaling and Area scaling was performed for the 5 th order filter and the capacitor values are shown in the figure. For clarity, single-ended version is shown. The implementation was done differentially. C. Low-Q section The low Q section was placed in the end. The transfer function implemented using this structure is shown in the figure 9. z z 1 H 3 (z) =.1486 z z The low-q biquad is derived from its continuous-time counterpart Tow-Thomas Biquad. The resistors are replaced with switched-capacitors and the structure is used for implementing the above transfer function. The general transfer function for this low-q structure is shown below. H 3 (z) = (K 2 K 3 )Z 2 (K 1 K 5 K 2 2K 3 )z K 3 (1 K 6 )z 2 (K 4 K 5 K 6 2)z 1

11 V inp C 2 C 3 Φ1 V inn C 1 C A V o1p V inp C 1 V o1p C A Φ1 V inn C 2 C 3 Cap(pF) C C 2 A C 1 C 3 Initial DR Area All Capacitor values in pf Fig. 7. Linear Section Comparing the above two expressions, the values of K i, were determined and dynamic range scaling and area scaling was performed. The corresponding Low-Q strucuture used in the 5 th order elliptic filter is shown in the following figure. Single-ended version is shown for clarity. However, implementation was done in differential version. The Fifth-Order filter used for simulation with switch-sharing is shown in the figure 1 D. Opamp-Macro-Model The opamp macro-model used for the simulation of the filter is shown in the figure 11. The opamp model was used to mimic the actual transistor level design with common mode feedback, finite gain, bandwidth and slew rate limitation. The cascade of biquad sections and the linear section was simulated in cadence with the opamp-macro model and boot-strap switches. The matlab ideal magnitude response and the magnitude response from cadence simulations are shown in the figure. 12. The small deviation(<.1 mdb) is due to the significant number of digits used for the capacitor, opamp gain

12 V in Κ4 Φ1 Κ6 Κ3 Κ1 Φ1 Φ2 Φ2 V off C 1 C 2 Φ1 Κ5 Φ2 V o1 V o2 Φ1 Φ2 V off Cap(pF) Initial DR Area K 1 K 3 K 4 K 5 K 6 C 1 C All Capacitor values are in pf Fig. 8. High-Q Section

13 V in Κ4 Φ1 Κ3 Φ1 Κ6 Φ2 Κ1 Φ1 Φ2 Φ2 V off C 1 C 2 Φ1 Κ5 Φ2 V o1 V o2 Φ1 Φ2 V off Cap(pF) Initial DR Area K 1 K 3 K 4 K 5 K 6 C 1 C All Capacitor values are in pf Fig. 9. Low-Q Section

14 Φ Κ C 1,1 1,1 1 Φ1 Κ 5,1 Φ C 2,1 2 Φ2 Φ2 Φ 2 V o2p Vo3p V o2n V o3n Φ2 Κ 4,1 Κ 3,1 Φ Φ 2 2 Κ Φ1 Κ 5,1 C 2,1 1,1 C 1,1 Κ 3,1 Κ 6,1 Φ Κ C 1,2 1,2 1 Φ1 Φ Κ5,2 1 Φ C 2,2 2 Φ2 Φ2 Φ 2 V o4p V o4n Φ2 Φ 2 Φ Φ Κ 1 Κ 5,2 2 1,2 C 2,2 C 1,2 Φ2 Φ2 V inn V inp V inn V inp C 2 Φ1 Φ2 C 1 Φ2 C 1 C 2 C 3 C 3 C A V o1p V o1n Κ 6,1 Κ 4,1 Κ 4,2 Κ 6,2 Κ 3,2 Κ 3,2 Κ 6,2 Κ 4,2 V o5p V o5n Fig th Order Elliptic Filter

15 v on v on v inn v inp v diff g m v diff g m v diff R R C V cmfb C v op R c R c V cmfb v op Vcm Fig. 11. Opamp Macro-Model and bandwidth. A. Switch Sizing VI. Charge Injection and Switches Considering the model shown in the figure 13 for a typical switch. The voltage at the end of φ 1 is v(nt) = v in (nt)(1 e T 4RonC ) This voltage on the capacitor is discharged during φ 2 into the virtual ground [1]. The charging of the feedback capacitor follows the similar expression. Hence the overall transfer function is H(z) = (1 e T 4RonC ) 2 Z 1 1 Z 1 For the error to be less than.1%, RC product should be less than T. The largest capacitor is.6 15 pf. Switches were designed with minimum channel length. The sampling frequency is 1MHz. B. Charge Injection The relation between R on and q ch is R on 1 15f c kΩ R on q ch = L2 µ q ch = L2 R on µ V error = 15L2 f c C µ = 15L2 f c µ

16 Matlab and Cadence Response Magnitude in db db Line Matlab Response H(z) Cadence Macro Model Response Fig. 12. Matlab and Cadence Plots Normalized Frequency in rad/s

17 C V R on C R on in R on R on C V in C Fig. 13. Switch-Model Substituting the values for f c,l and µ and assuming that half of the channel charge flows into the capacitor, we get V error = 7.5 (.18µ) =.825mV C. Choice of W L The ON-resistance of the switch and the calculation of the switch size is shown below. The value of ON-Resistance calculated before was used. D. Choice of Switch R on = 1 W µc ox L gs V tn ) W L = (1.8.4) 3 W.54µm 1.8V supply and.18µ TSMC model was used for simulations. To maximize the signal input to the filter, transmission gates are preferred over stand-alone NMOS switches. The following switches were compared for their performance. The harmonic distortion of each switch is compared, which relates to the signal dependant charge injection and the non-linear ON-resistance of the switch. Clockfeedthrough introduces a fixed amount of offset and hence should not introduce any harmonic distortion. The boot-strap switch has a fixed Gate-Source voltage, independent of the input voltage. Hence, It introduces least amount of distortion to the signal. The estimated charge-injection due to

18 channel charge and clock-feedthrough was approximately 1.2 mv. The transient simulation shows the pedestal of 1 mv for the bootstrap switch independant of the signal. Hence, Bootstrap switches were used for the filter to minimize the distortion. The third harmonic distortion was at 89 db below the fundamental for a in-band signal tone. E. Harmonic Distortion The harmonic distortion at the output of each switch was simulated. The sampling frequency is 1MHz. The switches were sized according to the sampling bandwidth requirement. A single tone at 3 f 64 s and 1mV peak amplitude with a common mode of.9 V was given at the input of each switch. 64-point DFT was performed at the output of each switch. The following tabular column shows the distortion performance of each switch. Switch 1 st (db) 2 nd (db) 3 rd (db) 4 rd (db) 5 th (db) NMOS Dummy Trans Dummy Bootstrap Dummy The following figure 16 shows the transient response of the five switches considered and the effect of charge injection and clock feedthrough. This can be seen as a pedestal in the hold-mode. This indicates the amount of charge injection resulting from channel charge and the clock-feedthrough. The boot-strap switch has the least amount of charge-injection. The pedestal value is 1.2mV and is independant of the input voltage. F. Clock-Generator The following non-overlapping clock generator was used for generating the clock-phases.

19 b V in V in C C b V in V in b C b C b V dd b V dd b C boot b V in Sampling Switch C Fig. 14. Different Sampling Switches

20 Clk b b Fig. 15. Non-Overlapping Clock Generator VII. Offset The Effect of offset was simulated with Vin= and a input referred opamp offset voltage of 1 mv. The following estimates were used in determining the effect of the offset of each stage of the filter [1]. A. First Order Stage During Steady state, the charge entering the virtual node due to the capacitors which are switched must be zero. Hence V off C 2 (V o1 V off )C 3 = V o1 = V off1 ( C 2 C 3 1) Assuming 1 mv offset and using the values of C 2 = 362fF, C 3 = 215fF, The value of the steady state output voltage due to offset is 2.65 mv. This can be observed from the simulation result also. B. Biquad Low Q - Stage The effect of input referred offset voltage was simulated with Vin= and an input referred opamp offset voltage of 1 mv. The following estimates were used in determining the effect of the offset. V off K 1 (V o1 V off )K 4 C 1 = V o1 = ( K 1 K 4 1)V off = 2.475mV For the intermediate node of the low-q biquad, the effect of the offset is derived as follows, C. High-Q Biquad Stage V off K 5 (V o1 V off )K 6 = V o2 K 5 V o2 = (V o1 V off ) K 6 K 5 V off =.49mV The effect of offset voltage was simulated with Vin= and an input referred opamp offset voltage of 1 mv. The following equations were used in determining the effect of the offset.

21 Sample and Hold Output and Charge Injection Voltage(V) Input NMOS TRANS Gate Dummy TRANS Gate Bootstrap Dummy NMOS Dummy Bootstrap x 1 7 Fig. 16. Transient Output Response Time in second(s) x 1 7

22 K 1 V off K 4 V o2 K 4 C 1 = V o2 = (1 K 1 )V off K 4 = 1.432mV V o1 = V off = 1mV Transient simulation was performed with input referred offset and the steady state output voltages are shown in the figure. The simulated steady state values and the estimated values match. D. Filter Offset Voltage The following equations were derived for the steady filter output voltage with input referred offset in each opamp. The derivation is from the first order section. V o1 = (1 C 2 )V off = 2.67mV C 3 = V off = 1mV V o2 V o3 = V off K 1,2 K 4,2 (V o1 V off ) =.4mV V o4 = (V o5 V off ) K 6,3 K 5,3 V off =.5mV V o5 = V off K 1,3 K 4,3 = 2.475mV K i,j represents the coefficient i in the section j. VIII. Slew-Rate The slew rate is caused by the opamp s maximum current output. Thus, the rate at which the output node is charged is fixed at a particular rate. For a sinusoidal input, the rate of increase of the input is SR = dv in dt = V p ω in The maximum slew-rate occurs at maximum passband frequency and peak amplitude. Therefore, the maximum step in one time period is v = V p ω in T v = V pω in T t at/2 = 2V pω in a The maximum-rate at 1V-Differential input at MHz is around 16V/µs. This could be seen from the distortion spectrum at the output of the filter. The distortion spectrum in shown in the figure. 19.

23 3 x 1 3 Transient Output of Individual Stage with Opamp Offset 2 1 Output Voltage(V) Time in second(s) x x 1 3 Filter Transient with Opamp Offset Voltage 4 Transient Settling Output Voltage(V) mv 1 mv.5 mv.4 mv mv Time in second(s) x 1 6 Fig. 17. Individual and Filter Offset Voltage

24 V inp C 2 C 3 Φ1 V inn C 1 C A V o1p Fig. 18. Slew-Rate Estimation Slew-Rate - Method 2 The Linear section has the worst-case slew-rate limitation. Consider the linear section shown in the figure 18. Assuming the opamp has 2% of one-clock phase to slew and maximum input of 1 V, The worst-case slew-rate is derived as follows, q in = v in (C 1 C 2 ) v out = C 1 C 2 v in C 3 C A SR max =.2v in.5.2 T/2 SR max = 4V/µ s Slew-Rate Fundamental(dB) 3 rd (db) 5 th (db) 5V/µs V/µs V/µs V/µs The distortion for slew-rates greater than 15V/µs is limited mostly by the switch-non linearity. To give a safety margin of 3V/µs, The slew-rate required for the opamp is 18V/µs. IX. Finite Gain The Effect of finite gain was analyzed with respect to the integrator [3], [4]. The effect of finite DC gain on the poles of the filter is considered. The Integrator transfer function with finite DC gain is given by H(z) = Z H(s) = = C 1 Z (C 2 C 1C 2 A )Z C 2 (1 1 A ) 1 st C 1 (1 st) (C 2 C 1C 2 A )(1 st) C 2 (1 1 A ) C 1 C 2 T s C 1 C 2 AT

25 Distortion due to Slew Rate 1 SR = 5 V/µ s SR = 1 V/µ s SR = 15 V/µ s SR =2 V/µ s 2 Magnitude in db Fig. 19. Distortion due to Slew-Rate Frequency in Hertz x 1 7

26 Effect of Finite Gain(1 1) and Bandwidth 5MHz Magnitude Response in db Increasing A dc x 1 6 Fig. 2. Finite Gain Effect Frequency in Hertz(Hz) x 1 7

27 Assuming the DC gain as 1 and highest pole frequency as 5 MHz, the normalized pre-distortion value needed is. The pre-distorted poles are given by pi 2 Pole Ideal Pre-Distorted 1, ±.165i -.16 ±.165i 3, ±.1151i -.57 ±.1151i The effect of finite DC-gain changes s to sσ. The effect of this can be analyzed in the biquad. The Denominator in the biquadratic transfer function changes to s 2 ( ω Q σ 1 σ 2 )s (ω 2 ω σ 1 Q σ 1σ 2 ) The new pole Q can be compared with ideal transfer function. ω Q = ω Q σ 1 σ 2 1 = 1 Q Q 1 ω AT (C 1 C 1 ) C 2 The effect of DC-gain will be large in a high Q. The elliptic filter has two biquads. The quality factor is approximately 1 and 5. Hence the pass-band deviation due to the finite gain can be derived as C 2 σ 1 σ 2 1 A R p = 1 2Q A For the given passband ripple of.2 db, the minimum DC-gain required for the high-q biquad is 54 db approximately. To have some margin due to variation in DC-gain, 6 db DC-Gain was chosen for the opamp used in the filter. The finite-dc gain affects the passband poles with high-q. This can be clearly observed in the figure. 2. The effect of scaling with finite opamp gain is shown in the figure. 23. We can see that the dynamic range scaled system is more close to ideal response when compared with unscaled filter response. The predistorted and ideal response is shown in the figure. 22. X. CDS The finite gain error and phase error in the integrator can be minimized using CDS or CLS. The CDS integrator shown in the figure 21 has a constant gain error and is independant of the frequency [5]. The integrator and the charge transfer expression are given in the figure 21 XI. Finite Bandwidth The finite bandwidth effect with a single-pole finite DC gain amplifier. A v (s) = A dc s ω p 1 Where ω p A dc is the unity gain bandwidth of the integrator [4], [3]. The solution for integrator is shown below [3]. The approximate transfer function is Finite Gain and bandwidth effect is modelled for an

28 C 2 V in C 1 C 3 Φ C C 1 C 2 C 3 V in (n-1) V (n-1)/a V (n-1)(11/a) V (n-1) V (n-1/2)(1/a) V (n-1)(11/a) V (n-1/2)(11/a) V in (n) V (n)/a V (n)(11/a) V (n) Fig. 21. CDS- Integrator Integrator. Single-pole amplifier is assumed with finite DC Gain. V o (Z) V i (Z) V o (Z) V i (Z) = = Z 1 1 Z 1 (1 δ)z 1 1 (1 1 A dc )Z 1 Where δ = (1 k(1 e ωt/2 ))e ωt/2,k=feedback factor. ω - unity gain bandwidth. k is the feedback factor. This manifests itself as a gain error in the integrator. To minimize the effect of finite bandwidth, δ must be much smaller than the permissible tolerance of C 1 C i. Thus, the unity gain frequency is approximately 4-5 times the clock frequency. However, Choosing a higher bandwidth will result in folding of noise. The effect of bandwidth is shown in the figure.25

29 2 Ideal and Predistorted Response.5 Magnitude in db Fig. 22. Predistorted and Ideal Response - Passband Normalized Frequency in rad/s

30 Effect of Finite Gain(1) in DR scaled and unscaled Response Magnitude Response in db x 1 6 Ideal Scaled Unscaled Fig. 23. Predistorted and Ideal Response - Passband Frequency in Hertz(Hz) x 1 7

31 C 2 V in C 1 A Fig. 24. Finite Bandwidth Effect XII. Opamp Design Folded-cascode opamp was chosen for the opamp-design. In-order to maximize the output swing and to minimize the any extra compensation capacitors, folded cascode opamp was chosen [6]. The figure 26 shows the magnitude response of the top-level simulation of the 5 th order elliptic filter with bootstrap switches and folded-cascode opamp. The Ideal response and the macro-model response with finite gain and bandwidth limitations are also shown for comparison. The opamp designed has the following specifications. Parameter DC-Gain Unity Gain Bandwidth Load Capacitance Slew-Rate Common-mode Value 57.8 db 5 MHz 1 pf 18V/µs.9 V The above specifications were derived from the finite-dc gain and bandwidth requirements for the filter specification. The open-loop gain and bandwidth characteristics of the amplifier is shown in the figure. 27. From the bandwidth requirement, the input pair transconductance is calculated. g m,in C L = 2π With effective load capacitance of 1 pf, the transconductance required is 3.14 ms. The bias current required was estimated from the slew-rate requirement. The opamp was over-designed for the slew-rate requirement. The opamp is capable of handling slew-rate of 4V/µs. The bias current was 41µA for the tail current source. The fully differentially opamp schematic is shown in the figure??. The overdrive is 1 mv. The opamp is capable of 2.8 V p p differential swing. Thus, the dynamic range of

32 1 Effect of Finite Gain(1) and Bandwidth 5MHz 5MHz Increasing Bandwidth Magnitude Response in db x 1 6 Fig. 25. Finite Bandwidth Effect Frequency in Hertz(Hz) x 1 7

33 5 th Order Elliptic Filter with Folded Cascode Opamp Magnitude in db db Line.15 DC Gain = x 1 6 Ideal Bootstrap Switch Folded Cascode Opamp Bootstrap Switch Macro Model Opamp Fig. 26. Top-Level Simulation of Filter Frequency in Hertz(Hz) x 1 7

34 6 Open Loop Amplifier Gain and Phase Gain Phase 57.8 db DC Gain Open Loop Gain in db Phase Margin Fig. 27. Open-Loop Amplifier Gain and Phase Characteristics Frequency in Hertz

35 Vdd 55 µa M 9 M 1 Vcmfb V cmfb M 23 M 24 M 25 V b2 M 8 V b4 M 11 M 12 C c C c V b4 M 21 M 2 V b4 1/g m2 1/g m2 2.5 KΩ 2.8 KΩ V M M 1 V on V op V on V op M 19 M 18 M 19 V cm V b3 V - M 5 M 6 V b2 M 13 M 14 V b1 M 3 M 4 M 7 M 15 M 16 M17 Transistor Sizes in µm M 3,M 5,M 4,M 6-26(.5/.5) M 9,M 1-468(.5/.5) M 7,M 8,M 25,M,M 1,M (.5/.5) M 11,M (.5/.5) Common-mode Feedback branch Current density is 1/5 th of the differential branch

36 the filter is maximized. The opamp was design using.18µ TSMC model at 1.8 V supply. The total bias current consumption is 1.1 ma. The impulse-response and step response of the transistor level filter(opamp Bootstrap Switch) is compared with Ideal filter in the figure 3. The transient simulation with 2 V p p input at 5 khz is shown in the figure 31. The clippin near 1 V is due to limitation of the swing at around 1.4 V and at.5 V of the folded cascode amplifier. References [1] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing. Wiley Series on Filters, [2] D. A. Johns and K. Martin, Analog Integrated Circuit Design. Wiley, 25. [3] G. C. Temes, Finite amplifier gain and bandwidth effects in switched-capacitor filters, IEEE JOURNAL OF SOLID-STATE CIRCUITS., vol. 15, pp , 198. [4] K. Martin and A. S. Sedra, Effects of the op amp finite gain and bandwidth on the performance of switched-capacitor filters, IEEE Transactions on Circuits and Systems., vol. 28, pp , [5] G. C. T. K. Haug, F. Maloberti, Switched-capacitor integrators with low finite-gain sensitivity, Electronic Letters, vol. 21, pp , [6] R. Gregorian, Introduction to CMOS Op-Amps and Comparators. Wiley, 1999.

37 Transistor Level Filter Response(V) Impulse response of Transistor Level Filter Time in second(s) x 1 7 Impulse response of Ideal Filter.1 Ideal Filter Response Time in second(s) x 1 7

38 Step Response of Ideal Filter and Transistor Level Filter Time in second(s) x Time in second(s) x 1 7 Step Response of Ideal Filter(V) Step Response of Transistor Level Filter(V) Fig. 3. Impulse Response

39 1.5 Transient response of 2V p p Input sinusoid at 5 khz with Transistor Level Opamp Switch Input Filter Output 1.5 Fig. 31. Transient Response Transient Response Time in Second(s) x 1 5

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