Two- Path Band- Pass Σ- Δ Modulator with 40- MHz IF 72- db DR at 1- MHz Bandwidth Consuming 16 mw

Transcription

1 I. Galdi, E. Bonizzoni, F. Maloberti, G. Manganaro, P. Malcovati: "Two-Path Band- Pass Σ-Δ Modulator with 40-MHz IF 72-dB DR at 1-MHz Bandwidth Consuming 16 mw"; 33rd European Solid State Circuits Conf., ESSCIRC 2007, Munich, September 2007, pp xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

2 Two-Path Band-Pass!" Modulator with 40-MHz IF 72-dB DR at 1-MHz Bandwidth Consuming 16 mw I. Galdi, E. Bonizzoni, F. Maloberti University of Pavia Department of Electronics Via Ferrata, Pavia ITALY ivano.galdi@unipv.it G. Manganaro National Semiconductor Corporation 1 Stiles Road Salem, NH USA gabriele.manganaro@nsc.com P. Malcovati University of Pavia Department of Electrical Engineering Via Ferrata, Pavia ITALY piero.malcovati@unipv.it Abstract A band-pass!" modulator that uses two time interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40-MHz IF provide a signal band of 1 MHz with 72-dB DR and 65.1-dB peak SNR. The circuit, integrated in a 0.18-!m CMOS technology, uses a 60-MHz clock per channel. Experimental results show that the in-band region is not affected by tones caused by mismatches and that a two-tones input causes an IMD signal of 68 db c. The power consumption is 16 mw with 1.8-V supply. I. INTRODUCTION The designer of portable communication systems often examines solutions with!" band-pass converters [1] because of their low power benefit. However, since the multiple zeros of the noise transfer function are at the IF, the noise shaping advantage vanishes when increasing the signal band. Moreover, the position of the IF frequency is almost locked. Instead, a Nyquist-rate converter enables any signal bandwidth and allow positioning the IF anywhere in the Nyquist interval. Nevertheless, the power consumption is not affordable for portable applications as, for instance, for sampling frequencies in the MHz range, the power of a 12-bit converter is several tens of mw [2]. This design offers a viable solution to the problem as it obtains low power while enabling a relatively large bandwidth (2 MHz) so that the IF can be possibly moved within a reasonable range, or the granted frequency band can be fully used for the signal. The used circuit is a 2-path band-pass architecture with 4-bit quantizers. The used scheme avoids the well known limits caused by channel mismatches, that, typically, cause in-band tones. Indeed, the experimental results show a tone free spectrum with a low noise flat region of ±1 MHz around 40 MHz (less than 125 nv/ Hz with a ±1 V differential reference). Therefore, using a 1-MHz signal band, the dynamic range is 72 db FS while the peak SNR is 65.1 db. Each path runs at 60 MHz, leading to a 120-MHz sampling frequency. The power consumption is 16 mw with a 1.8-V supply. II. NTF SYNTHESIS This circuit obtains a band-pass sigma-delta response by synthesizing the noise transfer function (1+#z -1 +z -2 ) 2. The NTF for # =1 gives rise to a pair of zeros on the unity circle around 1/3f s and 2/3f s and no spur zeros elsewhere. With #!1 but close to the unity value, the pair of zeros moves slightly apart increasing the region of band-pass noise shaping. This method is used in this design for trading the noise attenuation at the IF with an increased signal band. Actually, the zero shift does not affect the performance until the shaped quantization noise remains below the floor established by the thermal noise and the finite performance of the op-amps. The architecture synthesizes the expected transfer function starting from a two-path structure. The method is based on the rewriting of the NTF as follows NTF = [(1+ z "2 ) 2 +# 2 z "2 ] + z "1 [ 2#(1+ z "2 )] (1) that outlines two main terms, enclosed in squared brackets, both function of z 2. Therefore, the implementation of those terms would require a circuit able to achieve a z $ z 2 transformation. Moreover, observe that the second term requires a delay by one clock period. As done in [3], the transformation z $ z 2 is granted by a two-path timeinterleaved scheme with each path running at half of the clock frequency. In our case each path should generate an NTF equal to (1 + z -1 ) 2 + # 2 z -1. The result is obtained by the scheme shown in Fig. 1 (with the auxiliary inputs set to zero). Notice that the architecture of Fig. 1 is a second order modulator employing blocks with 1/(1 + z -1 ) transfer functions instead of the one of a conventional integrator. Moreover, there is an extra feedback toward the input made by two terms: one is the analog output and the other is combined with the normal /07/$ IEEE. 248

3 feedback term that is therefore multiplied by 2 before exercising the main DAC. The result is that the combination of the feedbacks yields the quantization error at the input of the block after a delay by z -1. This is what required to implement the last term # 2 z -1 of the path s NTF. result is that a possible DC signal (like the offset mismatch of the second op-amp) into that loop is transformed into a tone at f s /4. Fig. 1 Block diagram of the single path. Fig. 3 Implementation of z -1 /(1 + z -1 ). III. CIRCUIT SCHEMATIC Fig. 2 Block diagram of the modulator. Actually, the block diagram of Fig. 1 obtains # =1. For having a different value, it is enough to change the capacitance used in the analog feedback and to adjust the reference voltage of the main DAC. A possible mismatch between the two corrective actions is not problematic because, possibly, it gives rise to a gain error of the entire modulator. A two-path time-interleaved architecture uses the even input samples in one path and the odd ones on the other path. Therefore, there is one clock period delay between the signals that are processed by the two paths. This delay corresponds to what required by the z -1 term that multiplies the second term enclosed in square brackets in (1). Therefore, a cross-coupled injection of the quantization noises into the auxiliary input realizes the second brackets because the path transfer function is 2#(1 + z -1 ). By inspection, it is easy to verify that the transfer function from the auxiliary input to the output is, actually, (1 + z -1 ). Thus, the cross injection of the quantization noise multiplied by 2 provides the result. The complete block diagram of the modulator is shown in Fig. 2, where the crosscoupled quantization errors are distinguished into the analog and digital components. The output is interpolated at the output to provide the output bit stream at the foreseen clock frequency. A possible offset mismatch of the op-amps used in the first integrators causes a tone at f s /2 while a gain mismatch is equivalent to an attenuation and a modulation of the input signal by f s /2. Therefore, the caused tones are far away from the signal band. Observe that the cross-coupled connections required for injecting the second term of the NTF create a loop of two blocks with transfer function z -1 /(1 + z -1 ). The effect of the loop can be easily studied in the time domain and the The circuit implementation of the transfer function 1/(1 + z -1 ) or z -1 /(1 + z -1 ) requires an inversion of the previous output every clock period. We obtain the same result by modulating by ±1 at f s /2 both input and output of a conventional integrator [3]. The circuit that realizes the ±1 modulation at half of the clock frequency at input and output of an inverting or non inverting integrator is the scheme of Fig. 3. Actually, the square wave modulation at the output of the first integrator and the one at the input of the next one cancels one another just requiring the ±1 switches only at input and output of the entire scheme and in the cross-coupled paths. Moreover, for saving power, the first and the second integrators of the paths share the op-amp [4]. The use of the same of-amp in the first and in the second path is made possible by the z -1 delay between the two decimation by two operations at the input. The integrating capacitors are disconnected from the op-amp output side with a switch during the inactive period. The use of the op-amp in both phases demands for higher bandwidth and slewing, but the overall power consumption diminishes by about 35% than in the case with separate op-amps. As a side benefit of the opamp sharing, there is no offset mismatch in the cross-coupled loop and the tone at f s /4 is caused only by the clock feedthrough associated to the switches connected to the virtual ground. The two op-amps have the same scheme but use different bias currents as requested by the slew-rate and the feedback factors: they are fully-differential mirrored cascode amplifiers with switched capacitor common-mode feedback. The key features are given in Table 1. Observe that the DC gain is pretty low; this feature is made possible by the moderate sensitivity on the gain at the expected overall resolution. The simulation results made at the behavioural level, but including finite gain, bandwidth and slew-rate of the op-amps show that a DC gain as low as 40 db does not degrade the performance that are, instead, determined by the kt/c limit. 249

4 On the contrary, the bandwidth and the slew-rate must be relatively high but the request is met by the used scheme at a reasonable power consumption. The high bandwidth and slew-rate of the second op-amp depend on the feedback factor established by the cross-coupled input with gain 2. TABLE I OP-AMPS PERFORMANCE Feature First op-amp Second op-amp DC gain Unity gain frequency Slew-rate Supply voltage Power consumption 46 db 200 MHz 200 V/µs 1.2 mw 42 db 250 MHz 260 V/µs 2.3 mw equivalent to an IF of 10.7 MHz. The use of a LLP package, whose bonding inductance is much lower than the TQFP, allows a 60 MHz clock per path that increases the IF to 40 MHz. The operation with 16-MHz clock requires an overall power consumption of 10.5 mw while, with an higher clock (60 MHz), the required power, accounting for the increased one consumed in the op-amps for more demanding slew-rate and bandwidth, is 16 mw. The voltage comparators of the two 4-bit flash ADCs are made by a preamplifier with gain 4 followed by a latch. The bias current of each preamplifier is 20 µa. A single resistive divider made by 16 equal 500-% resistors provides the reference voltages of both flash ADCs. The DACs are embedded in the input switched capacitor structure made by 16 unity elements equal to 25 ff. The combinatory digital logics perform the required operations within the clock period, 16.5 ns. The integration capacitances are slightly changed (# = 1.003) to ensure a proper NTF zeros separation. Fig. 5 Measured modulator output spectrum. The measured output spectrum is shown in Fig. 5. The inband noise is almost flat over the used range with a floor equal to 125 nvfs/ Hz, that is slightly more than the expected kt/c contribution (102 nvfs/ Hz ), likely because of the op-amp limits. The spectrum also shows the tone at f N/2 that! that, as described before, is due to the clock is -34 dbfs feedthrough at the input!of the second stages. The associated amplitude (20 mv) slightly diminishes the full scale of the modulator, that, indeed, is much more limited by the quantization noises. Fig. 4 Chip microphotograph. IV. EXPERIMENTAL RESULTS The modulator was integrated using a 0.18-"m single-poly 5-metal CMOS technology. The die, whose microphotograph is shown in Fig. 4, has an active area equal to 0.44 mm2. The reference voltages are external to the circuit and no internal buffer is used for enforcing the strength of the references. This is beneficial for limiting the power consumption, but is problematic for the ringing caused after every switching because of the bonding inductance of the connection from pin to pad. The duration of the ringing limits the usable clock frequency that, for a TQFP package, is about 16 MHz per path 250 Fig. 6 SNR versus input signal amplitude.

5 The SNRs as a function of the input amplitude for three different bandwidths 1 MHz (40 ± 0.5 MHz), 2 MHz (40 ± 1 MHz) and 4 MHz (40 ± 2 MHz) are shown in Fig. 6. Since there are no tones, the SNDR equals the SNR. It can be noted that an increase (as well as a reduction) of the signal band diminishes the SNR as the square of the increase factor (i.e., plain oversampling) until remaining within the flat region, but drops significantly when the signal band reaches the frequency region where the noise ramps up. The peak of the SNR occurs around -6 db FS even if the circuit uses a 4-bit quantization. The result, predicted by simulations at the behavioural level, is due to the relatively large amplification of both quantization errors that show up at the two inputs. is described. Split zeros around the 40 MHz IF provide a dynamic range of 72 db, 69 db and 50 db SNR for signal bands of 1 MHz, 2 MHz, and 4 MHz respectively (full scale signal ±1 V PP differential). The in-band noise floor is about 125 nv/ Hz. The circuit, integrated in a 0.18-"m CMOS technology, uses a 60-MHz clock per channel. For two tones at -14 db FS, the intermodulation is about 68 dbc. The power consumption is 16 mw with 1.8-V supply and can be decreased to 10.5 mw with 16-MHz clock per channel. TABLE II PERFORMANCE SUMMARY f s 60 MHz (x 2) IF 40 MHz Voltage References ±0.5 V Signal Bandwidth up to 4 MHz Peak SNR MHz Band Active Area 0.44 mm 2 Supply Voltage Power Consumption 16 mw IMD 68 dbc DR 72 1 MHz Band ACKNOWLEDGMENT The authors would like to thank Carlos Hinojosa and Jacque Margolycz of National Semiconductor Corporation for their valuable support to this work. REFERENCES Fig. 7 IMD test result. The linearity of the modulator has been evaluated with a two-tone intermodulation (IMD) test (f 1 = MHz, f 2 = MHz). For two tones at -14 db FS (as shown in Fig. 7), the intermodulation tone falling at 2f 2 - f 1 is visible above the noise floor and gives an IMD of about 68 dbc. The result is 3 db better than the remarkable figure obtained in [5] that uses a more complex solution and requires four-five times more of power. The performance of the modulator are summarized in Table 2. Obviously, since the IF frequency is a fixed ratio of the path clock (2/3), scaling down the clock frequency also scales the IF. Thus, for example, the circuit can meet the specification for digitizing the AM/FM radio broadcasting signal, by obtaining 67-dB peak SNR and 72-dB DR, with a reduced power equal to 10.5 mw, made possible by the diminished speed request to the op-amps. V. CONCLUSIONS In this paper a band-pass!" modulator that uses two timeinterleaved second-order modulators and cross coupled paths [1] T. Salo, T. Hollman, S. Lindfors, and K. Halonen, A dual-mode 80MHz bandpass!" modulator for a GSM WCDMA IFreceiver, IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., pp , 461, Feb [2] T.N. Andersen, B. Hernes, A. Briskemyr, F. Telsto, J. Bjornsen, T.E. Bonnerud, and O. Moldsvor, A cost-efficient high-speed 12-bit pipeline ADC in 0.18-"m digital CMOS, IEEE J. Solid- State Circuits, vol. 40, no. 7, pp , July [3] F. Ying and F. Maloberti, A mirror image free two-path bandpass!" modulator with 72 db SNR and 86 db SFDR, IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., vol. 1, pp , Feb [4] K. Nagaraj, F.S. Fetterman, J. Anidjar, S.H. Lewis, and R.G. Renninger, A 250-mW, 8-b, 52-Msamples/s parallelpipelined A/D converter with reduced number of amplifier, IEEE J. Solid-State Circuits, vol. 32, no. 3, pp , March [5] V. Colonna, G. Gandolfi, F. Stefani, and A. Baschirotto, A 10.7-MHz self-calibrated switched-capacitor-based multibit second-order bandpass!" modulator with on-chip switched buffer, IEEE J. Solid-State Circuits, vol. 39, no. 8, pp , August