Integrated Microsystems Laboratory. Franco Maloberti


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1 University of Pavia Integrated Microsystems Laboratory Power Efficient Data Convertes Franco Maloberti
2 OUTLINE Introduction Managing the noise power budget Challenges of Stateoftheart Technologies Analog Poweraware Design Design examples Digital Assisted Analog Conclusions IMS University of Pavia 2
3 Introduction RATIONALE In the fast growing electronic world, analog integrated circuits continue playing an important role for sensing and networking, security and safety, healthcare medical and life science, entertainments and education, and many other applications. Two important and essential features of many modern systems are connectivity and portability. Low power, or better micropower design is very important because having a long battery life or even ensuring batteryless operation are essential features. The reduction of the supply voltage is not imposed by just an evolving IC technology but also by the need of minimum power consumption. Therefore, lowvoltage analog and A/D design is an important research topic. IMS University of Pavia 3
4 Introduction IMS University of Pavia 4
5 Introduction HOW TO MEASURE THE POWER EFFECTIVENESS? IMS University of Pavia 5
6 OUTLINE Introduction Managing the power budget Challenges of Stateoftheart Technologies Analog Poweraware Design Design examples Digital Assisted Analog Conclusions IMS University of Pavia 6
7 Managing the Noise Budget THE RESOLUTION OF A DATA CONVERTER IS NOT MEANINGFUL The bits just represent the accuracy of an ideal conversion system The true parameter is the ENoB (effective number of bit) Or the SNR SNR = 6.02 ENoB That, for a given V DD define V FS and estimate the allowed noise power 2 2 V V noise,tot = FS SNR / The noise power gives the available noise budget for the various noise sources. IMS University of Pavia 7
8 Noise Budget The key issue is to properly assign the available noise budget to the various noise sources Quantization noise Sampling noise Speed related noise Interference (power of tones) Boardlevel noise f 1 + f B V 2 Q = 2 v Q NTF( f ) 2 df f 1 < f in < f 1 + f B f 1 Quantization IMS University of Pavia 8
9 Noise sources Sampling noise 2 V Samp = α kt C S 1 OSR f 1 < f in < f 1 + f B Assumes that the sampling noise is not shaped α > 2 depends on the noise contributed by the opamp or due to multiple sampling Speed related noise Clock jitter V 2 ji = V 2 FS 8 2π( f 1 + f B ) δ ji OSR f 1 < f in < f 1 + f B IMS University of Pavia 9
10 Noise sources Speed related noise Subharmonic tones 2 V harm i 2 = V tone,i Interference/substrate noise White noise floor X f B Tones V 2 sub 2 V board Board level noise Give a small part of the budget to this term IMS University of Pavia 10
11 How to allocate the noise budget? 2 V noise,tot = V 2 2 Q + V Samp + V 2 2 ji + V harm 2 + V sub 2 + V board Estimate the last three terms (to be kept to the minimum with a careful execution) Calculate the residual noise available and assign it At low frequency 2 V ji is negligible (unless CTΣ ) 2 Little budget to means increasing power V Samp V Q 2 Little budget to means more bit or higher noise shaping. IMS University of Pavia 11
12 How to allocate the noise budget? IMS University of Pavia 12
13 OUTLINE Introduction Managing the power budget Challenges of Stateoftheart Technologies Analog Poweraware Design Design examples Digital Assisted Analog Conclusions IMS University of Pavia 13
14 Good and Bad of Technology Increase of speed process f T of CMOS IMS University of Pavia 14
15 Parameters of DSM Transistors Transconductance at saturated carrier velocity Increase the width and/or enlarge the transistor With a 65 nm technology IMS University of Pavia 15
16 Parameters of DSM Transistors Intrinsic gain IMS University of Pavia 16
17 Parameters of DSM Transistors Use of highk oxides causes much more 1/f et al. IMS University of Pavia 17
18 Parameters of DSM Transistors Matching IMS University of Pavia 18
19 Matching Parameter and Matching IMS University of Pavia 19
20 OUTLINE Introduction Managing the power budget Challenges of Stateoftheart Technologies Analog Poweraware Design Design examples Digital Assisted Analog Conclusions IMS University of Pavia 20
21 Analog Power Aware Design DESIGN STRATEGIES Double sampling or Opamp sharing Bandwidth of the Opamp must be a bit higher No time for the virtual ground settling Feedback factor can be time variant Power saving is about 0.3 P opamp IMS University of Pavia 21
22 Power Aware Design Use less Opamp than the order Σ More details and Experimental results J.Ko et ISSCC 05 p = 2 q = 1 G= 2z 1 Patent by TI The adding node requires using one opamp The integration block is 1/(12z 1 +z 2 )=1/(1z 1 ) 2 The NTF is (1z 1 ) 2 Mismatch in capacitances moves the NTF zeros Solution suitable for medium resolution and low OSR IMS University of Pavia 22
23 Power Aware Design More bit or higher OSR in Σ architectures Multibit helps in reducing the power consumption: Second order > double the clock to get 2.5 extra bit Doubling the clock means more than doubling the power 2.5 bit means x = 5.6x the number of levels used in the ADC and DAC (5.6x comparators) Consider a second order Σ with a 2bit DAC P opamp =1 mw; P comp = 30 µw P Σ =2 P opamp + (2 21) P comp + P dig =2.2 mw Doubling the clock frequency P opamp =2 mw; P comp = 40 µw; P Σ = 4.25 mw Using 5.6x comparators (4.5bit) (and a bit more digital) P Σ =2 P opamp + 22 P comp + P dig = 2.8 mw IMS University of Pavia 23
24 Power Aware Design Npath and NTF Synthesis The motivation of this approach is Reduction of power consumption Obtain convenient NTF Basic structure is a set of Σ modulators running at f ck /N that are used in an Npath arrangement z 1 z 2 NTF = (1 z 1 ) L NT F = (1 z 2 ) L The opamps run at half clock frequency; we have two opamps The NTF can be modified adding new terms IMS University of Pavia 24
25 Power Aware Design Design of suitable building blocks The use of well established scheme can be nonoptimal Opamps linearity and gain really necessary? Existing comparator architecture are optimal? Can we trade speed with accuracy even at the block level? Look at the reference generator power needs Use of digital methods to relax the block specs IMS University of Pavia 25
26 OUTLINE Introduction Managing the power budget Challenges of Stateoftheart Technologies Analog Poweraware Design Design examples Digital Assisted Analog Conclusions IMS University of Pavia 26
27 Bandpass Sigma Delta SigmaDelta for DVBH Lowpower SAR Design Examples IMS University of Pavia 27
28 Bandpass SigmaDelta Use of Npath and NTF synthesis IMS University of Pavia 28
29 Bandpass Sigma Delta How to obtain bandpass response The goal is to have NTF= (1+z 1 +z 2 ) 2 NTF = (1+ z 1 + z 2 ) 2 = (1+ 2z 1 + 3z 2 + 2z 3 + z 4 ) = [(1+ 2z 2 + z 4 )+ z 2 ]+ [ 2z 1 + 2z 3 ]= = [ (1+ z 2 ) 2 + z 2 ]+ 2z 1 (1+ z 2 ) [ ] Second order NTF=(1+z 1 ) 2 z z 2 Extra term Delay First order (1+z 1 ) z z 2 I. Galdi, E. Bonizzoni, P. Malcovati, G. Manganaro, F. Maloberti: "40 MHz IF 1 MHz Bandwidth TwoPath Bandpass Σ Modulator with 72 db DR Consuming 16 mw" IEEE Journal of SolidState Circuits, July 2008, pp IMS University of Pavia 29
30 Bandpass Sigma Delta Path structure Secondorder Σ and extra term H(z) = 1 1 z 1 H 1 (z) = 1 1+ z 1 z 1 H 2 (z) = 1+ z 1 IMS University of Pavia 30
31 Bandpass Sigma Delta Modified 2nd order Σ H z z ( z) = ; H ( z) = z Cross coupling Realize the missing terms 1 2 [ 2z (1 + z )] Opamp sharing First integrator Second integrator Obtain split zeros With suitable coefficients Reduced gains IMS University of Pavia 31
32 Bandpass Sigma Delta Implementation technology: 0.18µm singlepoly 5metal CMOS technology 900 µm 1700 µm IMS University of Pavia 32
33 Bandpass Sigma Delta Experimental Results SNR = 65.1 db DR = 72 db BW = 1MHz F s = 120 MHz IF = 40 MHz BW = 1 MHz DR = 72 db BW = 2 MHz DR = 69 db BW = 4 MHz DR = 50 db IMS University of Pavia 33
34 Bandpass Sigma Delta Obtained Experimental Results F s 60 MHz (x 2) IF Voltage References Signal Bandwidth Peak SNR 40 MHz ± 0.5 V up to 4 MHz MHz Band Active Area 0.44 mm 2 Supply Voltage Power Consumption IMD DR 1.8 V 16 mw 68 db c 72 1 MHz Band IMS University of Pavia 34
35 SigmaDelta for DVBH Scaling (to satisfy the power need) of the architecture IMS University of Pavia 35
36 Sigma Delta for DVBH Minimum Requests of Analog Accuracy. MediumHigh Resolutions. Low OSR. Good FoM. CHALLENGE Digital Video BroadcastingHandheld (DVBH) [1] Bandwidth 48MHz Power Consum. <10mW DVBH Environment COMPARABLE CellularRadio Environment Personal Digital Assistant (PDA). Cellular Phones. Pocket PC Equip. HANDHELD Small Size. Light Weight. Long Battery Life. COMMON E. Bonizzoni, A. Pena Perez, F. Maloberti, M. Garcia Andrade: "ThirdOrder Σ Modulator with 61dB SNR and 6MHz Bandwidth Consuming 6 mw"; ESSCIRC 2008, pp IMS University of Pavia 36
37 Sigma Delta for DVBH A. REDUCTION OF THE NUMBERS OF OPAMPS Basic 3 rd Order Σ Modulator, OSR=8:  3 Integrators without delay.  NTF = (1z 1 ) 3.  Feedforward path (Limit 1 st Opamp Swing).  5bit Quantizer. IMS University of Pavia 37
38 Sigma Delta for DVBH 1 st STEP Feedback input 3rd Opamp is moved at the input 2 nd Opamp. Operation: One opamp is eliminated. A thirdorder modulator with only two integrators is made. IMS University of Pavia 38
39 Sigma Delta for DVBH B. REDUCTION OF THE NUMBERS OF COMPARATORS 2 nd STEP Use a 5bit quantizer with reduced input range. Is more convenient to quantize Previous quantization Considering a 5bit quantizer the number of comparators decreases from 31 to 18. IMS University of Pavia 39
40 B. Sigma Delta for DVBH 3 rd STEP REDUCTION OF THE NUMBERS OF COMPARATORS Feedback input Quantizer is moved at the input Double Integrator. Operation: The SR of the 2 nd Opamp is relaxed. IMS University of Pavia 40
41 Sigma Delta for DVBH TWO OPAMPS SCHEME CMFB FullyDifferential Folded Cascode SwitchedCapacitor INTEGRATORS 1 st STAGE Input Capacitor C i = 80 ff 2 nd STAGE (Double Int.) Feedback Capacitors C f = 40 ff Input of the Double Integrator uses two DACs: Avoid interferences. Reduce the Digital Processing. χ Additional Power: 15% of the total. 5bit DAC SCHEME Resistive Divider 32 x R=200 Ω IMS University of Pavia 41
42 Sigma Delta for DVBH CHIP MICROPHOTOGRAPH ThirdOrder Σ Modulator ase erato Pha Gene r CAPACITO RS OTA A1 OTA TA2 DAC 1 rflas H CAPACITO RS DAC 2 DS SP Technology: Metal Levels: Active Area: Package: 0.18μm CMOS Double poly μm 2 40pins LLP Power Supply: 1.8V IMS University of Pavia 42
43 Sigma Delta for DVBH [4] [4] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, and A. Baschirotto, Behavioral Modeling of SwitchedCapacitor SigmaDelta Modulators, IEEE Trans. on Circuits and Systems I: Funamental Theory and Applications, vol. 50, no. 3, pp , March IMS University of Pavia 43
44 Lowpower SAR Design Use of timedomain comparator IMS University of Pavia 44
45 LowPower SAR LOW power is the most relevant design concern for batterypowered mobile applications. Since the ADCs operate at 10s of MS/s with 10b to 12b, the pipeline ADC is the commonly used architecture because of its power efficiency. Recently, the successive approximation resistor (SAR) architecture has reemerged as a valuable alternative to the pipelined solution. The techniques used for low speed can be reused for high speed. This example is a stateoftheart FOM low speed. IMS University of Pavia 45
46 Low Power SAR IMS University of Pavia 46
47 Low Power SAR Use of unity attenuation capacitor and V2T comparator A.Agnes, E. Bonizzoni, P. Malcovati, F. Maloberti: "A 9.4ENOB 1V 3.8µW 100kS/s SAR ADC with Time Domain Comparator"; ISSCC 2008, pp IMS University of Pavia 47
48 LowPower SAR The timedomain Comparator IMS University of Pavia 48
49 LowPower SAR IMS University of Pavia 49
50 OUTLINE Introduction Managing the power budget Challenges of Stateoftheart Technologies Analog Poweraware Design Design examples Digital Assisted Analog Conclusions IMS University of Pavia 50
51 Digital Calibration The real advantage of thin linewidth technologies is the huge number of transistors available with which we can perform complex digital functions and dynamically store huge data Foreground (or offline) calibration, that uses specific timeslots for calibration, and background calibration (or online), that performs the circuit calibration during the normal operation of the circuit Background calibration is more complex than foreground because it requires to ensure normal operation together with calibration. There are two main approaches: the use of circuit redundancy or the use of test terms added to the signal. IMS University of Pavia 51
52 Digital Assisted Analog 0.1nJ 0.1mW/MSps 16.7K IMS University of Pavia 52
53 Digital Control of Analog Circuits Digitally Assistant Analog The digital assistant analog techniques are now in an infancy phase. It is expected that the method will significant grow for helping, in addition to digital calibration, the analog designer in facing the limits of DSM technologies IMS University of Pavia 53
54 Digital Control of Analog Circuits Use of digital representations of signals to improve analog performances of sigmadelta modulators IMS University of Pavia 54
55 OUTLINE Introduction Managing the power budget Challenges of Stateoftheart Technologies Analog Poweraware Design Design examples Digital Assisted Analog Conclusions IMS University of Pavia 55
56 Portable and autonomous applications need power efficient data converters Solutions involve architecture optimization, tradeoff and, it may be, choice of the optimal technology Remember that the optimum can require extrabit in the quantizer to compensate for power and speed needs Examples are just examples and not an indication of a unique path to find the optimum Consider more and more the advantages offered by the digital processing at zero cost. IMS University of Pavia 56
57 Thank you!!! IMS University of Pavia 57
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